From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 593D7C49361 for ; Fri, 18 Jun 2021 09:32:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4184561184 for ; Fri, 18 Jun 2021 09:32:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231445AbhFRJfA (ORCPT ); Fri, 18 Jun 2021 05:35:00 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:5038 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230390AbhFRJe7 (ORCPT ); Fri, 18 Jun 2021 05:34:59 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G5tr01rRkzXh7p; Fri, 18 Jun 2021 17:27:44 +0800 (CST) Received: from dggema757-chm.china.huawei.com (10.1.198.199) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Fri, 18 Jun 2021 17:32:48 +0800 Received: from [127.0.0.1] (10.69.38.203) by dggema757-chm.china.huawei.com (10.1.198.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 18 Jun 2021 17:32:47 +0800 Subject: Re: [PATCH v6 2/2] drivers/perf: hisi: Add driver for HiSilicon PCIe PMU To: Will Deacon , Linuxarm CC: , , , , , References: <1622467951-32114-1-git-send-email-liuqi115@huawei.com> <1622467951-32114-3-git-send-email-liuqi115@huawei.com> <20210611162347.GA16284@willie-the-truck> <20210615093519.GB19878@willie-the-truck> <8e15e8d6-cfe8-0926-0ca1-b162302e52a5@huawei.com> <20210616134257.GA22905@willie-the-truck> <678f7d55-9408-f323-da53-b5afe2595271@huawei.com> <20210617175704.GF24813@willie-the-truck> From: "liuqi (BA)" Message-ID: <0e7f6601-0d18-18da-f19c-d71ce1bc15dc@huawei.com> Date: Fri, 18 Jun 2021 17:32:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20210617175704.GF24813@willie-the-truck> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 8bit X-Originating-IP: [10.69.38.203] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggema757-chm.china.huawei.com (10.1.198.199) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021/6/18 1:57, Will Deacon wrote: > On Thu, Jun 17, 2021 at 07:00:26PM +0800, liuqi (BA) wrote: >> >> >> On 2021/6/16 21:42, Will Deacon wrote: >>> Hi, >>> >>> On Wed, Jun 16, 2021 at 09:54:23AM +0800, liuqi (BA) wrote: >>>> On 2021/6/15 17:35, Will Deacon wrote: >>>>> On Tue, Jun 15, 2021 at 04:57:09PM +0800, liuqi (BA) wrote: >>>>>> On 2021/6/12 0:23, Will Deacon wrote: >>>>>>> On Mon, May 31, 2021 at 09:32:31PM +0800, Qi Liu wrote: >>>>>>>> + /* Process data to set unit of latency as "us". */ >>>>>>>> + if (is_latency_event(idx)) >>>>>>>> + return div64_u64(data * us_per_cycle, data_ext); >>>>>>>> + >>>>>>>> + if (is_bus_util_event(idx)) >>>>>>>> + return div64_u64(data * us_per_cycle, data_ext); >>>>>>>> + >>>>>>>> + if (is_buf_util_event(idx)) >>>>>>>> + return div64_u64(data, data_ext * us_per_cycle); >>>>>>> >>>>>>> Why do we need to do all this division in the kernel? Can't we just expose >>>>>>> the underlying values and let userspace figure out what it wants to do with >>>>>>> the numbers? >>>>>>> >>>>>> Our PMU hardware support 8 sets of counters to count bandwidth, latency and >>>>>> utilization events. >>>>>> >>>>>> For example, when users set latency event, common counter will count delay >>>>>> cycles, and extern counter count number of PCIe packets automaticly. And we >>>>>> do not have a event number for counting number of PCIe packets. >>>>>> >>>>>> So this division cannot move to userspace tool. >>>>> >>>>> Why can't you expose the packet counter as an extra event to userspace? >>>>> >>>> Maybe I didn’t express it clearly. >>>> >>>> As there is no hardware event number for PCIe packets counting, extern >>>> counter count packets *automaticly* when latency events is selected by >>>> users. >>>> >>>> This means users cannot set "config=0xXX" to start packets counting event. >>>> So we can only get the value of counter and extern counter in driver and do >>>> the division, then pass the result to userspace. >>> >>> I still think it would be ideal if we could expose both values to userspace >>> rather than combine them somehow. Hmm. Anyway... >>> >>> I struggled to figure out exactly what's being counted from the >>> documentation patch (please update that). Please can you explain exactly >>> what appears in the HISI_PCIE_CNT and HISI_PCIE_EXT_CNT registers for the >>> different modes of operation? Without that, the ratios you've chosen to >>> report seem rather arbitrary. >>> >> >> PCIe PMU events can be devided into 2 types: one type is counted by >> HISI_PCIE_CNT, the other type is counted by HISI_PCIE_EXT_CNT and >> HISI_PCIE_CNT, including bandwidth events, latency events, buffer >> utilization and bus utilization. >> >> if user sets "event=0x10, subevent=0x02", this means "latency of RX memory >> read" is selected. HISI_PCIE_CNT counts total delay cycles and >> HISI_PCIE_EXT_CNT counts PCIe packets number at the same time. So PMU driver >> could obtain average latency by caculating: HISI_PCIE_CNT / >> HISI_PCIE_EXT_CNT. >> >> if users sets "event=0x04, subevent=0x01", this means bandwidth of RX memory >> read is selected. HISI_PCIE_CNT counts total packet data volume and >> HISI_PCIE_EXT_CNT counts cycles, so PMU driver could obtain average >> bandwidth by caculating: HISI_PCIE_CNT / HISI_PCIE_EXT_CNT. >> >> The same logic is used when calculating bus utilization and buffer >> utilization. Seems I should add this part in Document patch,I 'll do this in >> next version, thanks. >> >>> I also couldn't figure out how the latency event works. For example, I was >>> assuming it would be a filter (a bit like the length), so you could say >>> things like "I'm only interested in packets with a latency higher than x" >>> but it doesn't look like it works that way. >>> >>> Thanks, >>> >> latency is not a filter, PCIe PMU has a group of lactency events, their >> event number are within the latency_events_list, and the above explains how >> latency events work. >> >> PMU drivers have TLP length filter for bandwidth events, users could set >> like "I only interested in bandwidth of packets with TLP length bigger than >> x". > > Thanks for the explanations, I think I get it a bit better now. But I still > think we should be exposing both of the values to userspace instead of > reporting the ratio from which the individual counters are then > unrecoverable. > > It will complicate the driver slightly, but can we instead expose the > events independently and then allowing scheduling some of them in groups? > > That way we just treat HISI_PCIE_CNT and HISI_PCIE_EXT_CNT as separate > counters, but with a scheduling constraint that events in a register pair > must be in the same group. > > Will Hi Will, I got what you mean, treating HISI_PCIE_CNT and HISI_PCIE_EXT_CNT as separate counters is a great idea, but here is a hardware limitation. The behavior of HISI_PCIE_EXT_CNT is controlled by hardware logical, so HISI_PCIE_EXT_CNT only works when latency/bandwidth/... events number are set in HISI_PCIE_EVENT_CTRL. So driver cannot separate this two counters, they must work together because of hardware limitation. We try to expose both values of counters at the same time, but there seems only one "event->count" for driver to expose value. Is there any method to do this? Thanks, Qi > . > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BFBEC48BDF for ; Fri, 18 Jun 2021 09:40:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C65A613C2 for ; Fri, 18 Jun 2021 09:40:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C65A613C2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:CC:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=uU3pWY62eVYG8vgtpM5jghJlvN1X1J0BQcvtN4t8vr4=; b=FWxRieE3BuWgZValvuSn2u42Gf CVIecc/qRnBkIdbbnn3xpuC2gJPmVDkmXScSqwHE2UgRtLBPaTwfXVnUG0710HBO3wfMxd/65feij uXqx98OnQCCp40RaFzQqlykO2a54VVlqKeGS/zji8H3u+cFrTKVgp+pjWdrzr+jSVUxAxlrZe4834 5YeEqcokee3iUGUYiEgMMrF6HLa6MqKfggDvUB3l7lGGGz30gRxJZj818hkXidAGQckXt0NY1jI50 vFxm36XqN9zxQg4MOYdJUidmlIpwwcKV6TF8qDcDj5MbXu4IwvQDqRgU1njDGizalrdDxl1CDKvC2 n9EFdWdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1luAxN-00DXpm-Oj; Fri, 18 Jun 2021 09:38:33 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1luArs-00DURe-Mv for linux-arm-kernel@lists.infradead.org; Fri, 18 Jun 2021 09:32:55 +0000 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G5tr01rRkzXh7p; Fri, 18 Jun 2021 17:27:44 +0800 (CST) Received: from dggema757-chm.china.huawei.com (10.1.198.199) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Fri, 18 Jun 2021 17:32:48 +0800 Received: from [127.0.0.1] (10.69.38.203) by dggema757-chm.china.huawei.com (10.1.198.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 18 Jun 2021 17:32:47 +0800 Subject: Re: [PATCH v6 2/2] drivers/perf: hisi: Add driver for HiSilicon PCIe PMU To: Will Deacon , Linuxarm CC: , , , , , References: <1622467951-32114-1-git-send-email-liuqi115@huawei.com> <1622467951-32114-3-git-send-email-liuqi115@huawei.com> <20210611162347.GA16284@willie-the-truck> <20210615093519.GB19878@willie-the-truck> <8e15e8d6-cfe8-0926-0ca1-b162302e52a5@huawei.com> <20210616134257.GA22905@willie-the-truck> <678f7d55-9408-f323-da53-b5afe2595271@huawei.com> <20210617175704.GF24813@willie-the-truck> From: "liuqi (BA)" Message-ID: <0e7f6601-0d18-18da-f19c-d71ce1bc15dc@huawei.com> Date: Fri, 18 Jun 2021 17:32:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20210617175704.GF24813@willie-the-truck> Content-Language: en-GB X-Originating-IP: [10.69.38.203] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggema757-chm.china.huawei.com (10.1.198.199) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210618_023253_165929_41C7F90E X-CRM114-Status: GOOD ( 36.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CgpPbiAyMDIxLzYvMTggMTo1NywgV2lsbCBEZWFjb24gd3JvdGU6Cj4gT24gVGh1LCBKdW4gMTcs IDIwMjEgYXQgMDc6MDA6MjZQTSArMDgwMCwgbGl1cWkgKEJBKSB3cm90ZToKPj4KPj4KPj4gT24g MjAyMS82LzE2IDIxOjQyLCBXaWxsIERlYWNvbiB3cm90ZToKPj4+IEhpLAo+Pj4KPj4+IE9uIFdl ZCwgSnVuIDE2LCAyMDIxIGF0IDA5OjU0OjIzQU0gKzA4MDAsIGxpdXFpIChCQSkgd3JvdGU6Cj4+ Pj4gT24gMjAyMS82LzE1IDE3OjM1LCBXaWxsIERlYWNvbiB3cm90ZToKPj4+Pj4gT24gVHVlLCBK dW4gMTUsIDIwMjEgYXQgMDQ6NTc6MDlQTSArMDgwMCwgbGl1cWkgKEJBKSB3cm90ZToKPj4+Pj4+ IE9uIDIwMjEvNi8xMiAwOjIzLCBXaWxsIERlYWNvbiB3cm90ZToKPj4+Pj4+PiBPbiBNb24sIE1h eSAzMSwgMjAyMSBhdCAwOTozMjozMVBNICswODAwLCBRaSBMaXUgd3JvdGU6Cj4+Pj4+Pj4+ICsJ LyogUHJvY2VzcyBkYXRhIHRvIHNldCB1bml0IG9mIGxhdGVuY3kgYXMgInVzIi4gKi8KPj4+Pj4+ Pj4gKwlpZiAoaXNfbGF0ZW5jeV9ldmVudChpZHgpKQo+Pj4+Pj4+PiArCQlyZXR1cm4gZGl2NjRf dTY0KGRhdGEgKiB1c19wZXJfY3ljbGUsIGRhdGFfZXh0KTsKPj4+Pj4+Pj4gKwo+Pj4+Pj4+PiAr CWlmIChpc19idXNfdXRpbF9ldmVudChpZHgpKQo+Pj4+Pj4+PiArCQlyZXR1cm4gZGl2NjRfdTY0 KGRhdGEgKiB1c19wZXJfY3ljbGUsIGRhdGFfZXh0KTsKPj4+Pj4+Pj4gKwo+Pj4+Pj4+PiArCWlm IChpc19idWZfdXRpbF9ldmVudChpZHgpKQo+Pj4+Pj4+PiArCQlyZXR1cm4gZGl2NjRfdTY0KGRh dGEsIGRhdGFfZXh0ICogdXNfcGVyX2N5Y2xlKTsKPj4+Pj4+Pgo+Pj4+Pj4+IFdoeSBkbyB3ZSBu ZWVkIHRvIGRvIGFsbCB0aGlzIGRpdmlzaW9uIGluIHRoZSBrZXJuZWw/IENhbid0IHdlIGp1c3Qg ZXhwb3NlCj4+Pj4+Pj4gdGhlIHVuZGVybHlpbmcgdmFsdWVzIGFuZCBsZXQgdXNlcnNwYWNlIGZp Z3VyZSBvdXQgd2hhdCBpdCB3YW50cyB0byBkbyB3aXRoCj4+Pj4+Pj4gdGhlIG51bWJlcnM/Cj4+ Pj4+Pj4KPj4+Pj4+IE91ciBQTVUgaGFyZHdhcmUgc3VwcG9ydCA4IHNldHMgb2YgY291bnRlcnMg dG8gY291bnQgYmFuZHdpZHRoLCBsYXRlbmN5IGFuZAo+Pj4+Pj4gdXRpbGl6YXRpb24gZXZlbnRz Lgo+Pj4+Pj4KPj4+Pj4+IEZvciBleGFtcGxlLCB3aGVuIHVzZXJzIHNldCBsYXRlbmN5IGV2ZW50 LCBjb21tb24gY291bnRlciB3aWxsIGNvdW50IGRlbGF5Cj4+Pj4+PiBjeWNsZXMsIGFuZCBleHRl cm4gY291bnRlciBjb3VudCBudW1iZXIgb2YgUENJZSBwYWNrZXRzIGF1dG9tYXRpY2x5LiBBbmQg d2UKPj4+Pj4+IGRvIG5vdCBoYXZlIGEgZXZlbnQgbnVtYmVyIGZvciBjb3VudGluZyBudW1iZXIg b2YgUENJZSBwYWNrZXRzLgo+Pj4+Pj4KPj4+Pj4+IFNvIHRoaXMgZGl2aXNpb24gY2Fubm90IG1v dmUgdG8gdXNlcnNwYWNlIHRvb2wuCj4+Pj4+Cj4+Pj4+IFdoeSBjYW4ndCB5b3UgZXhwb3NlIHRo ZSBwYWNrZXQgY291bnRlciBhcyBhbiBleHRyYSBldmVudCB0byB1c2Vyc3BhY2U/Cj4+Pj4+Cj4+ Pj4gTWF5YmUgSSBkaWRu4oCZdCBleHByZXNzIGl0IGNsZWFybHkuCj4+Pj4KPj4+PiBBcyB0aGVy ZSBpcyBubyBoYXJkd2FyZSBldmVudCBudW1iZXIgZm9yIFBDSWUgcGFja2V0cyBjb3VudGluZywg ZXh0ZXJuCj4+Pj4gY291bnRlciBjb3VudCBwYWNrZXRzICphdXRvbWF0aWNseSogd2hlbiBsYXRl bmN5IGV2ZW50cyBpcyBzZWxlY3RlZCBieQo+Pj4+IHVzZXJzLgo+Pj4+Cj4+Pj4gVGhpcyBtZWFu cyB1c2VycyBjYW5ub3Qgc2V0ICJjb25maWc9MHhYWCIgdG8gc3RhcnQgcGFja2V0cyBjb3VudGlu ZyBldmVudC4KPj4+PiBTbyB3ZSBjYW4gb25seSBnZXQgdGhlIHZhbHVlIG9mIGNvdW50ZXIgYW5k IGV4dGVybiBjb3VudGVyIGluIGRyaXZlciBhbmQgZG8KPj4+PiB0aGUgZGl2aXNpb24sIHRoZW4g cGFzcyB0aGUgcmVzdWx0IHRvIHVzZXJzcGFjZS4KPj4+Cj4+PiBJIHN0aWxsIHRoaW5rIGl0IHdv dWxkIGJlIGlkZWFsIGlmIHdlIGNvdWxkIGV4cG9zZSBib3RoIHZhbHVlcyB0byB1c2Vyc3BhY2UK Pj4+IHJhdGhlciB0aGFuIGNvbWJpbmUgdGhlbSBzb21laG93LiBIbW0uIEFueXdheS4uLgo+Pj4K Pj4+IEkgc3RydWdnbGVkIHRvIGZpZ3VyZSBvdXQgZXhhY3RseSB3aGF0J3MgYmVpbmcgY291bnRl ZCBmcm9tIHRoZQo+Pj4gZG9jdW1lbnRhdGlvbiBwYXRjaCAocGxlYXNlIHVwZGF0ZSB0aGF0KS4g UGxlYXNlIGNhbiB5b3UgZXhwbGFpbiBleGFjdGx5Cj4+PiB3aGF0IGFwcGVhcnMgaW4gdGhlIEhJ U0lfUENJRV9DTlQgYW5kIEhJU0lfUENJRV9FWFRfQ05UIHJlZ2lzdGVycyBmb3IgdGhlCj4+PiBk aWZmZXJlbnQgbW9kZXMgb2Ygb3BlcmF0aW9uPyBXaXRob3V0IHRoYXQsIHRoZSByYXRpb3MgeW91 J3ZlIGNob3NlbiB0bwo+Pj4gcmVwb3J0IHNlZW0gcmF0aGVyIGFyYml0cmFyeS4KPj4+Cj4+Cj4+ IFBDSWUgUE1VIGV2ZW50cyBjYW4gYmUgZGV2aWRlZCBpbnRvIDIgdHlwZXM6IG9uZSB0eXBlIGlz IGNvdW50ZWQgYnkKPj4gSElTSV9QQ0lFX0NOVCwgdGhlIG90aGVyIHR5cGUgaXMgY291bnRlZCBi eSBISVNJX1BDSUVfRVhUX0NOVCBhbmQKPj4gSElTSV9QQ0lFX0NOVCwgaW5jbHVkaW5nIGJhbmR3 aWR0aCBldmVudHMsIGxhdGVuY3kgZXZlbnRzLCBidWZmZXIKPj4gdXRpbGl6YXRpb24gYW5kIGJ1 cyB1dGlsaXphdGlvbi4KPj4KPj4gaWYgdXNlciBzZXRzICJldmVudD0weDEwLCBzdWJldmVudD0w eDAyIiwgdGhpcyBtZWFucyAibGF0ZW5jeSBvZiBSWCBtZW1vcnkKPj4gcmVhZCIgaXMgc2VsZWN0 ZWQuIEhJU0lfUENJRV9DTlQgY291bnRzIHRvdGFsIGRlbGF5IGN5Y2xlcyBhbmQKPj4gSElTSV9Q Q0lFX0VYVF9DTlQgY291bnRzIFBDSWUgcGFja2V0cyBudW1iZXIgYXQgdGhlIHNhbWUgdGltZS4g U28gUE1VIGRyaXZlcgo+PiBjb3VsZCBvYnRhaW4gYXZlcmFnZSBsYXRlbmN5IGJ5IGNhY3VsYXRp bmc6IEhJU0lfUENJRV9DTlQgLwo+PiBISVNJX1BDSUVfRVhUX0NOVC4KPj4KPj4gaWYgdXNlcnMg c2V0cyAiZXZlbnQ9MHgwNCwgc3ViZXZlbnQ9MHgwMSIsIHRoaXMgbWVhbnMgYmFuZHdpZHRoIG9m IFJYIG1lbW9yeQo+PiByZWFkIGlzIHNlbGVjdGVkLiBISVNJX1BDSUVfQ05UIGNvdW50cyB0b3Rh bCBwYWNrZXQgZGF0YSB2b2x1bWUgYW5kCj4+IEhJU0lfUENJRV9FWFRfQ05UIGNvdW50cyBjeWNs ZXMsIHNvIFBNVSBkcml2ZXIgY291bGQgb2J0YWluIGF2ZXJhZ2UKPj4gYmFuZHdpZHRoIGJ5IGNh Y3VsYXRpbmc6IEhJU0lfUENJRV9DTlQgLyBISVNJX1BDSUVfRVhUX0NOVC4KPj4KPj4gVGhlIHNh bWUgbG9naWMgaXMgdXNlZCB3aGVuIGNhbGN1bGF0aW5nIGJ1cyB1dGlsaXphdGlvbiBhbmQgYnVm ZmVyCj4+IHV0aWxpemF0aW9uLiBTZWVtcyBJIHNob3VsZCBhZGQgdGhpcyBwYXJ0IGluIERvY3Vt ZW50IHBhdGNoLEkgJ2xsIGRvIHRoaXMgaW4KPj4gbmV4dCB2ZXJzaW9uLCB0aGFua3MuCj4+Cj4+ PiBJIGFsc28gY291bGRuJ3QgZmlndXJlIG91dCBob3cgdGhlIGxhdGVuY3kgZXZlbnQgd29ya3Mu IEZvciBleGFtcGxlLCBJIHdhcwo+Pj4gYXNzdW1pbmcgaXQgd291bGQgYmUgYSBmaWx0ZXIgKGEg Yml0IGxpa2UgdGhlIGxlbmd0aCksIHNvIHlvdSBjb3VsZCBzYXkKPj4+IHRoaW5ncyBsaWtlICJJ J20gb25seSBpbnRlcmVzdGVkIGluIHBhY2tldHMgd2l0aCBhIGxhdGVuY3kgaGlnaGVyIHRoYW4g eCIKPj4+IGJ1dCBpdCBkb2Vzbid0IGxvb2sgbGlrZSBpdCB3b3JrcyB0aGF0IHdheS4KPj4+Cj4+ PiBUaGFua3MsCj4+Pgo+PiBsYXRlbmN5IGlzIG5vdCBhIGZpbHRlciwgUENJZSBQTVUgaGFzIGEg Z3JvdXAgb2YgbGFjdGVuY3kgZXZlbnRzLCB0aGVpcgo+PiBldmVudCBudW1iZXIgYXJlIHdpdGhp biB0aGUgbGF0ZW5jeV9ldmVudHNfbGlzdCwgYW5kIHRoZSBhYm92ZSBleHBsYWlucyBob3cKPj4g bGF0ZW5jeSBldmVudHMgd29yay4KPj4KPj4gUE1VIGRyaXZlcnMgaGF2ZSBUTFAgbGVuZ3RoIGZp bHRlciBmb3IgYmFuZHdpZHRoIGV2ZW50cywgdXNlcnMgY291bGQgc2V0Cj4+IGxpa2UgIkkgb25s eSBpbnRlcmVzdGVkIGluIGJhbmR3aWR0aCBvZiBwYWNrZXRzIHdpdGggVExQIGxlbmd0aCBiaWdn ZXIgdGhhbgo+PiB4Ii4KPiAKPiBUaGFua3MgZm9yIHRoZSBleHBsYW5hdGlvbnMsIEkgdGhpbmsg SSBnZXQgaXQgYSBiaXQgYmV0dGVyIG5vdy4gQnV0IEkgc3RpbGwKPiB0aGluayB3ZSBzaG91bGQg YmUgZXhwb3NpbmcgYm90aCBvZiB0aGUgdmFsdWVzIHRvIHVzZXJzcGFjZSBpbnN0ZWFkIG9mCj4g cmVwb3J0aW5nIHRoZSByYXRpbyBmcm9tIHdoaWNoIHRoZSBpbmRpdmlkdWFsIGNvdW50ZXJzIGFy ZSB0aGVuCj4gdW5yZWNvdmVyYWJsZS4KPiAKPiBJdCB3aWxsIGNvbXBsaWNhdGUgdGhlIGRyaXZl ciBzbGlnaHRseSwgYnV0IGNhbiB3ZSBpbnN0ZWFkIGV4cG9zZSB0aGUKPiBldmVudHMgaW5kZXBl bmRlbnRseSBhbmQgdGhlbiBhbGxvd2luZyBzY2hlZHVsaW5nIHNvbWUgb2YgdGhlbSBpbiBncm91 cHM/Cj4gCj4gVGhhdCB3YXkgd2UganVzdCB0cmVhdCBISVNJX1BDSUVfQ05UIGFuZCBISVNJX1BD SUVfRVhUX0NOVCBhcyBzZXBhcmF0ZQo+IGNvdW50ZXJzLCBidXQgd2l0aCBhIHNjaGVkdWxpbmcg Y29uc3RyYWludCB0aGF0IGV2ZW50cyBpbiBhIHJlZ2lzdGVyIHBhaXIKPiBtdXN0IGJlIGluIHRo ZSBzYW1lIGdyb3VwLgo+IAo+IFdpbGwKCkhpIFdpbGwsCgpJIGdvdCB3aGF0IHlvdSBtZWFuLCB0 cmVhdGluZyBISVNJX1BDSUVfQ05UIGFuZCBISVNJX1BDSUVfRVhUX0NOVCBhcyAKc2VwYXJhdGUg Y291bnRlcnMgaXMgYSBncmVhdCBpZGVhLCBidXQgaGVyZSBpcyBhIGhhcmR3YXJlIGxpbWl0YXRp b24uCgpUaGUgYmVoYXZpb3Igb2YgSElTSV9QQ0lFX0VYVF9DTlQgaXMgY29udHJvbGxlZCBieSBo YXJkd2FyZSBsb2dpY2FsLCBzbyAKSElTSV9QQ0lFX0VYVF9DTlQgb25seSB3b3JrcyB3aGVuIGxh dGVuY3kvYmFuZHdpZHRoLy4uLiBldmVudHMgbnVtYmVyIAphcmUgc2V0IGluIEhJU0lfUENJRV9F VkVOVF9DVFJMLiBTbyBkcml2ZXIgY2Fubm90IHNlcGFyYXRlIHRoaXMgdHdvIApjb3VudGVycywg dGhleSBtdXN0IHdvcmsgdG9nZXRoZXIgYmVjYXVzZSBvZiBoYXJkd2FyZSBsaW1pdGF0aW9uLgoK V2UgdHJ5IHRvIGV4cG9zZSBib3RoIHZhbHVlcyBvZiBjb3VudGVycyBhdCB0aGUgc2FtZSB0aW1l LCBidXQgdGhlcmUgCnNlZW1zIG9ubHkgb25lICJldmVudC0+Y291bnQiIGZvciBkcml2ZXIgdG8g ZXhwb3NlIHZhbHVlLiBJcyB0aGVyZSBhbnkgCm1ldGhvZCB0byBkbyB0aGlzPwoKVGhhbmtzLApR aQoKPiAuCj4gCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5p bmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8v bGludXgtYXJtLWtlcm5lbAo=