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Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/06/2020 09:13, Chao Hao wrote: > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > in MISC_CTRL register. > F_MMU_STANDARD_AXI_MODE_BIT: > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > standard AXI protocol), iommu will send urgent read command firstly > compare with normal read command to improve performance. Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. Does this mean that you will send a 'urgent read command' which is not described in the specifications instead of a normal read command? > F_MMU_IN_ORDER_WR_EN: > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > will re-order write command and send more higher priority write command > instead of sending write command in order. The feature be controlled > by OUT_ORDER_EN macro definition. > > Cc: Matthias Brugger > Suggested-by: Yong Wu > Signed-off-by: Chao Hao > --- > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > drivers/iommu/mtk_iommu.h | 1 + > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 8f81df6cbe51..67b46b5d83d9 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -42,6 +42,9 @@ > #define F_INVLD_EN1 BIT(1) > > #define REG_MMU_MISC_CTRL 0x048 > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? > + > #define REG_MMU_DCM_DIS 0x050 > > #define REG_MMU_CTRL_REG 0x110 > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > } > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); We only need to read regval in the else branch. > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > /* The register is called STANDARD_AXI_MODE in this case */ > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > + regval = 0; > + } else { > + /* For mm_iommu, it can improve performance by the setting */ > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > + regval &= ~F_MMU_IN_ORDER_WR_EN; > } > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > dev_name(data->dev), (void *)data)) { > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index 7cc39f729263..4b780b651ef4 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -22,6 +22,7 @@ > #define HAS_BCLK BIT(1) > #define HAS_VLD_PA_RNG BIT(2) > #define RESET_AXI BIT(3) > +#define OUT_ORDER_EN BIT(4) Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the write path. > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > ((((pdata)->flags) & (_x)) == (_x)) > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF6BAC433E0 for ; Mon, 29 Jun 2020 09:28:19 +0000 (UTC) Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 72ECD233F6 for ; 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MISC_CTRL register To: Chao Hao , Joerg Roedel , Rob Herring References: <20200629071310.1557-1-chao.hao@mediatek.com> <20200629071310.1557-5-chao.hao@mediatek.com> From: Matthias Brugger Autocrypt: addr=matthias.bgg@gmail.com; prefer-encrypt=mutual; keydata= mQINBFP1zgUBEAC21D6hk7//0kOmsUrE3eZ55kjc9DmFPKIz6l4NggqwQjBNRHIMh04BbCMY fL3eT7ZsYV5nur7zctmJ+vbszoOASXUpfq8M+S5hU2w7sBaVk5rpH9yW8CUWz2+ZpQXPJcFa OhLZuSKB1F5JcvLbETRjNzNU7B3TdS2+zkgQQdEyt7Ij2HXGLJ2w+yG2GuR9/iyCJRf10Okq gTh//XESJZ8S6KlOWbLXRE+yfkKDXQx2Jr1XuVvM3zPqH5FMg8reRVFsQ+vI0b+OlyekT/Xe 0Hwvqkev95GG6x7yseJwI+2ydDH6M5O7fPKFW5mzAdDE2g/K9B4e2tYK6/rA7Fq4cqiAw1+u EgO44+eFgv082xtBez5WNkGn18vtw0LW3ESmKh19u6kEGoi0WZwslCNaGFrS4M7OH+aOJeqK fx5dIv2CEbxc6xnHY7dwkcHikTA4QdbdFeUSuj4YhIZ+0QlDVtS1QEXyvZbZky7ur9rHkZvP ZqlUsLJ2nOqsmahMTIQ8Mgx9SLEShWqD4kOF4zNfPJsgEMB49KbS2o9jxbGB+JKupjNddfxZ HlH1KF8QwCMZEYaTNogrVazuEJzx6JdRpR3sFda/0x5qjTadwIW6Cl9tkqe2h391dOGX1eOA 1ntn9O/39KqSrWNGvm+1raHK+Ev1yPtn0Wxn+0oy1tl67TxUjQARAQABtClNYXR0aGlhcyBC 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In-Reply-To: <20200629071310.1557-5-chao.hao@mediatek.com> Content-Language: en-US Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Evan Green , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 29/06/2020 09:13, Chao Hao wrote: > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > in MISC_CTRL register. > F_MMU_STANDARD_AXI_MODE_BIT: > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > standard AXI protocol), iommu will send urgent read command firstly > compare with normal read command to improve performance. Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. Does this mean that you will send a 'urgent read command' which is not described in the specifications instead of a normal read command? > F_MMU_IN_ORDER_WR_EN: > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > will re-order write command and send more higher priority write command > instead of sending write command in order. The feature be controlled > by OUT_ORDER_EN macro definition. > > Cc: Matthias Brugger > Suggested-by: Yong Wu > Signed-off-by: Chao Hao > --- > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > drivers/iommu/mtk_iommu.h | 1 + > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 8f81df6cbe51..67b46b5d83d9 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -42,6 +42,9 @@ > #define F_INVLD_EN1 BIT(1) > > #define REG_MMU_MISC_CTRL 0x048 > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? > + > #define REG_MMU_DCM_DIS 0x050 > > #define REG_MMU_CTRL_REG 0x110 > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > } > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); We only need to read regval in the else branch. > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > /* The register is called STANDARD_AXI_MODE in this case */ > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > + regval = 0; > + } else { > + /* For mm_iommu, it can improve performance by the setting */ > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > + regval &= ~F_MMU_IN_ORDER_WR_EN; > } > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > dev_name(data->dev), (void *)data)) { > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index 7cc39f729263..4b780b651ef4 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -22,6 +22,7 @@ > #define HAS_BCLK BIT(1) > #define HAS_VLD_PA_RNG BIT(2) > #define RESET_AXI BIT(3) > +#define OUT_ORDER_EN BIT(4) Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the write path. > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > ((((pdata)->flags) & (_x)) == (_x)) > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13D72C433E0 for ; Mon, 29 Jun 2020 09:28:27 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) 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Setting MISC_CTRL register To: Chao Hao , Joerg Roedel , Rob Herring References: <20200629071310.1557-1-chao.hao@mediatek.com> <20200629071310.1557-5-chao.hao@mediatek.com> From: Matthias Brugger Autocrypt: addr=matthias.bgg@gmail.com; prefer-encrypt=mutual; keydata= mQINBFP1zgUBEAC21D6hk7//0kOmsUrE3eZ55kjc9DmFPKIz6l4NggqwQjBNRHIMh04BbCMY fL3eT7ZsYV5nur7zctmJ+vbszoOASXUpfq8M+S5hU2w7sBaVk5rpH9yW8CUWz2+ZpQXPJcFa OhLZuSKB1F5JcvLbETRjNzNU7B3TdS2+zkgQQdEyt7Ij2HXGLJ2w+yG2GuR9/iyCJRf10Okq gTh//XESJZ8S6KlOWbLXRE+yfkKDXQx2Jr1XuVvM3zPqH5FMg8reRVFsQ+vI0b+OlyekT/Xe 0Hwvqkev95GG6x7yseJwI+2ydDH6M5O7fPKFW5mzAdDE2g/K9B4e2tYK6/rA7Fq4cqiAw1+u EgO44+eFgv082xtBez5WNkGn18vtw0LW3ESmKh19u6kEGoi0WZwslCNaGFrS4M7OH+aOJeqK fx5dIv2CEbxc6xnHY7dwkcHikTA4QdbdFeUSuj4YhIZ+0QlDVtS1QEXyvZbZky7ur9rHkZvP ZqlUsLJ2nOqsmahMTIQ8Mgx9SLEShWqD4kOF4zNfPJsgEMB49KbS2o9jxbGB+JKupjNddfxZ HlH1KF8QwCMZEYaTNogrVazuEJzx6JdRpR3sFda/0x5qjTadwIW6Cl9tkqe2h391dOGX1eOA 1ntn9O/39KqSrWNGvm+1raHK+Ev1yPtn0Wxn+0oy1tl67TxUjQARAQABtClNYXR0aGlhcyBC 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In-Reply-To: <20200629071310.1557-5-chao.hao@mediatek.com> Content-Language: en-US X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Evan Green , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, Yong Wu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On 29/06/2020 09:13, Chao Hao wrote: > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > in MISC_CTRL register. > F_MMU_STANDARD_AXI_MODE_BIT: > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > standard AXI protocol), iommu will send urgent read command firstly > compare with normal read command to improve performance. Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. Does this mean that you will send a 'urgent read command' which is not described in the specifications instead of a normal read command? > F_MMU_IN_ORDER_WR_EN: > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > will re-order write command and send more higher priority write command > instead of sending write command in order. The feature be controlled > by OUT_ORDER_EN macro definition. > > Cc: Matthias Brugger > Suggested-by: Yong Wu > Signed-off-by: Chao Hao > --- > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > drivers/iommu/mtk_iommu.h | 1 + > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 8f81df6cbe51..67b46b5d83d9 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -42,6 +42,9 @@ > #define F_INVLD_EN1 BIT(1) > > #define REG_MMU_MISC_CTRL 0x048 > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? > + > #define REG_MMU_DCM_DIS 0x050 > > #define REG_MMU_CTRL_REG 0x110 > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > } > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); We only need to read regval in the else branch. > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > /* The register is called STANDARD_AXI_MODE in this case */ > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > + regval = 0; > + } else { > + /* For mm_iommu, it can improve performance by the setting */ > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > + regval &= ~F_MMU_IN_ORDER_WR_EN; > } > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > dev_name(data->dev), (void *)data)) { > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index 7cc39f729263..4b780b651ef4 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -22,6 +22,7 @@ > #define HAS_BCLK BIT(1) > #define HAS_VLD_PA_RNG BIT(2) > #define RESET_AXI BIT(3) > +#define OUT_ORDER_EN BIT(4) Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the write path. > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > ((((pdata)->flags) & (_x)) == (_x)) > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9434C433DF for ; Mon, 29 Jun 2020 09:29:51 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org 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Subject: Re: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register To: Chao Hao , Joerg Roedel , Rob Herring References: <20200629071310.1557-1-chao.hao@mediatek.com> <20200629071310.1557-5-chao.hao@mediatek.com> From: Matthias Brugger Autocrypt: addr=matthias.bgg@gmail.com; prefer-encrypt=mutual; keydata= mQINBFP1zgUBEAC21D6hk7//0kOmsUrE3eZ55kjc9DmFPKIz6l4NggqwQjBNRHIMh04BbCMY fL3eT7ZsYV5nur7zctmJ+vbszoOASXUpfq8M+S5hU2w7sBaVk5rpH9yW8CUWz2+ZpQXPJcFa OhLZuSKB1F5JcvLbETRjNzNU7B3TdS2+zkgQQdEyt7Ij2HXGLJ2w+yG2GuR9/iyCJRf10Okq gTh//XESJZ8S6KlOWbLXRE+yfkKDXQx2Jr1XuVvM3zPqH5FMg8reRVFsQ+vI0b+OlyekT/Xe 0Hwvqkev95GG6x7yseJwI+2ydDH6M5O7fPKFW5mzAdDE2g/K9B4e2tYK6/rA7Fq4cqiAw1+u EgO44+eFgv082xtBez5WNkGn18vtw0LW3ESmKh19u6kEGoi0WZwslCNaGFrS4M7OH+aOJeqK fx5dIv2CEbxc6xnHY7dwkcHikTA4QdbdFeUSuj4YhIZ+0QlDVtS1QEXyvZbZky7ur9rHkZvP ZqlUsLJ2nOqsmahMTIQ8Mgx9SLEShWqD4kOF4zNfPJsgEMB49KbS2o9jxbGB+JKupjNddfxZ HlH1KF8QwCMZEYaTNogrVazuEJzx6JdRpR3sFda/0x5qjTadwIW6Cl9tkqe2h391dOGX1eOA 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x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <20200629071310.1557-5-chao.hao@mediatek.com> Content-Language: en-US X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Evan Green , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, Yong Wu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 29/06/2020 09:13, Chao Hao wrote: > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > in MISC_CTRL register. > F_MMU_STANDARD_AXI_MODE_BIT: > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > standard AXI protocol), iommu will send urgent read command firstly > compare with normal read command to improve performance. Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. Does this mean that you will send a 'urgent read command' which is not described in the specifications instead of a normal read command? > F_MMU_IN_ORDER_WR_EN: > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > will re-order write command and send more higher priority write command > instead of sending write command in order. The feature be controlled > by OUT_ORDER_EN macro definition. > > Cc: Matthias Brugger > Suggested-by: Yong Wu > Signed-off-by: Chao Hao > --- > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > drivers/iommu/mtk_iommu.h | 1 + > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 8f81df6cbe51..67b46b5d83d9 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -42,6 +42,9 @@ > #define F_INVLD_EN1 BIT(1) > > #define REG_MMU_MISC_CTRL 0x048 > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? > + > #define REG_MMU_DCM_DIS 0x050 > > #define REG_MMU_CTRL_REG 0x110 > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > } > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); We only need to read regval in the else branch. > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > /* The register is called STANDARD_AXI_MODE in this case */ > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > + regval = 0; > + } else { > + /* For mm_iommu, it can improve performance by the setting */ > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > + regval &= ~F_MMU_IN_ORDER_WR_EN; > } > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > dev_name(data->dev), (void *)data)) { > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index 7cc39f729263..4b780b651ef4 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -22,6 +22,7 @@ > #define HAS_BCLK BIT(1) > #define HAS_VLD_PA_RNG BIT(2) > #define RESET_AXI BIT(3) > +#define OUT_ORDER_EN BIT(4) Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the write path. > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > ((((pdata)->flags) & (_x)) == (_x)) > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel