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* [Intel-gfx] [PATCH 0/2] Use TGL stepping info and add ADLS platform changes
@ 2021-01-08 23:18 Aditya Swarup
  2021-01-08 23:18 ` [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs Aditya Swarup
                   ` (4 more replies)
  0 siblings, 5 replies; 24+ messages in thread
From: Aditya Swarup @ 2021-01-08 23:18 UTC (permalink / raw)
  To: intel-gfx

1. Change TGL REVID enums/macros to TGL stepping info to apply TGL WAs.
2. Add ADL-S platform info and PCI IDs and add TGL style stepping macros
   for applying WAs. 

Aditya Swarup (1):
  drm/i915/tgl: Use TGL stepping info for applying WAs

Caz Yokoyama (1):
  drm/i915/adl_s: Add ADL-S platform info and PCI ids

 .../drm/i915/display/intel_display_power.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 34 +++++---
 drivers/gpu/drm/i915/i915_drv.h               | 79 ++++++++++++-------
 drivers/gpu/drm/i915/i915_pci.c               | 13 +++
 drivers/gpu/drm/i915/intel_device_info.c      |  1 +
 drivers/gpu/drm/i915/intel_device_info.h      |  1 +
 drivers/gpu/drm/i915/intel_pm.c               |  2 +-
 include/drm/i915_pciids.h                     | 11 +++
 10 files changed, 104 insertions(+), 45 deletions(-)

-- 
2.27.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-08 23:18 [Intel-gfx] [PATCH 0/2] Use TGL stepping info and add ADLS platform changes Aditya Swarup
@ 2021-01-08 23:18 ` Aditya Swarup
  2021-01-08 23:44   ` Matt Roper
  2021-01-08 23:18 ` [Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 24+ messages in thread
From: Aditya Swarup @ 2021-01-08 23:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

TGL adds another level of indirection for applying WA based on stepping
information rather than PCI REVID. So change TGL_REVID enum into
stepping enum and use PCI REVID as index into revid to stepping table to
fetch correct display and GT stepping for application of WAs as
suggested by Matt Roper.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 .../drm/i915/display/intel_display_power.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
 drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
 drivers/gpu/drm/i915/intel_pm.c               |  2 +-
 6 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d52374f01316..bb04b502a442 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	int config, i;
 
 	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
-	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
 		/* Wa_1409767108:tgl,dg1 */
 		table = wa_1409767108_buddy_page_masks;
 	else
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c24ae69426cf..a93717178957 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	if (dev_priv->psr.psr2_sel_fetch_enabled) {
 		/* WA 1408330847 */
-		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
 		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
 			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	/* WA 1408330847 */
 	if (dev_priv->psr.psr2_sel_fetch_enabled &&
-	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
 	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index cf3589fd0ddb..4ce32df3855f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 {
 	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
 	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
 		return false;
 
 	return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c21a9726326a..111d01e2f81e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
 	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
 };
 
-const struct i915_rev_steppings tgl_uy_revids[] = {
-	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
-	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
-	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
-	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
+const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
+	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
+	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
+	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
+	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
 };
 
 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
-const struct i915_rev_steppings tgl_revids[] = {
-	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
-	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
+const struct i915_rev_steppings tgl_revid_step_tbl[] = {
+	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
+	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
 };
 
 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
@@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	gen12_gt_workarounds_init(i915, wal);
 
 	/* Wa_1409420604:tgl */
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
 			    CPSSUNIT_CLKGATE_DIS);
 
 	/* Wa_1607087056:tgl also know as BUG:1409180338 */
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 
 	/* Wa_1408615072:tgl[a0] */
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
 			    VSUNIT_CLKGATE_DIS_TGL);
 }
@@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	struct drm_i915_private *i915 = engine->i915;
 
 	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
-	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
 		/*
 		 * Wa_1607138336:tgl[a0],dg1[a0]
 		 * Wa_1607063988:tgl[a0],dg1[a0]
@@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
 	}
 
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
 		/*
 		 * Wa_1606679103:tgl
 		 * (see also Wa_1606682166:icl)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5e5bcef20e33..11d6e8abde46 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
 	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
 
 enum {
-	TGL_REVID_A0,
-	TGL_REVID_B0,
-	TGL_REVID_B1,
-	TGL_REVID_C0,
-	TGL_REVID_D0,
+	STEP_A0,
+	STEP_B0,
+	STEP_B1,
+	STEP_C0,
+	STEP_D0,
 };
 
-#define TGL_UY_REVIDS_SIZE	4
-#define TGL_REVIDS_SIZE		2
+#define TGL_UY_REVID_STEP_TBL_SIZE	4
+#define TGL_REVID_STEP_TBL_SIZE		2
 
-extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
-extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
+extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
+extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
 
 static inline const struct i915_rev_steppings *
-tgl_revids_get(struct drm_i915_private *dev_priv)
+tgl_stepping_get(struct drm_i915_private *dev_priv)
 {
 	u8 revid = INTEL_REVID(dev_priv);
 	u8 size;
-	const struct i915_rev_steppings *tgl_revid_tbl;
+	const struct i915_rev_steppings *revid_step_tbl;
 
 	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
-		tgl_revid_tbl = tgl_uy_revids;
-		size = ARRAY_SIZE(tgl_uy_revids);
+		revid_step_tbl = tgl_uy_revid_step_tbl;
+		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
 	} else {
-		tgl_revid_tbl = tgl_revids;
-		size = ARRAY_SIZE(tgl_revids);
+		revid_step_tbl = tgl_revid_step_tbl;
+		size = ARRAY_SIZE(tgl_revid_step_tbl);
 	}
 
 	revid = min_t(u8, revid, size - 1);
 
-	return &tgl_revid_tbl[revid];
+	return &revid_step_tbl[revid];
 }
 
-#define IS_TGL_DISP_REVID(p, since, until) \
+#define IS_TGL_DISP_STEPPING(p, since, until) \
 	(IS_TIGERLAKE(p) && \
-	 tgl_revids_get(p)->disp_stepping >= (since) && \
-	 tgl_revids_get(p)->disp_stepping <= (until))
+	 tgl_stepping_get(p)->disp_stepping >= (since) && \
+	 tgl_stepping_get(p)->disp_stepping <= (until))
 
-#define IS_TGL_UY_GT_REVID(p, since, until) \
+#define IS_TGL_UY_GT_STEPPING(p, since, until) \
 	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
-	 tgl_revids_get(p)->gt_stepping >= (since) && \
-	 tgl_revids_get(p)->gt_stepping <= (until))
+	 tgl_stepping_get(p)->gt_stepping >= (since) && \
+	 tgl_stepping_get(p)->gt_stepping <= (until))
 
-#define IS_TGL_GT_REVID(p, since, until) \
+#define IS_TGL_GT_STEPPING(p, since, until) \
 	(IS_TIGERLAKE(p) && \
 	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
-	 tgl_revids_get(p)->gt_stepping >= (since) && \
-	 tgl_revids_get(p)->gt_stepping <= (until))
+	 tgl_stepping_get(p)->gt_stepping >= (since) && \
+	 tgl_stepping_get(p)->gt_stepping <= (until))
 
 #define RKL_REVID_A0		0x0
 #define RKL_REVID_B0		0x1
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bbc73df7f753..319acca2630b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
 	/* Wa_1409825376:tgl (pre-prod)*/
-	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
+	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
 		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   TGL_VRH_GATING_DIS);
 
-- 
2.27.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids
  2021-01-08 23:18 [Intel-gfx] [PATCH 0/2] Use TGL stepping info and add ADLS platform changes Aditya Swarup
  2021-01-08 23:18 ` [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs Aditya Swarup
@ 2021-01-08 23:18 ` Aditya Swarup
  2021-01-09  0:20   ` Matt Roper
  2021-01-09  2:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use TGL stepping info and add ADLS platform changes Patchwork
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 24+ messages in thread
From: Aditya Swarup @ 2021-01-08 23:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi

From: Caz Yokoyama <caz.yokoyama@intel.com>

- Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been
  removed from ADLS. Disable PSR2 till we enable software/
  manual tracking.

v2:
- Add support for different ADLS SOC steppings to select
  correct GT/DISP stepping based on Bspec 53655 based on
  feedback from Matt Roper.(aswarup)

v3:
- Make display/gt steppings info generic for reuse with TGL and ADLS.
- Modify the macros to reuse tgl_revids_get()
- Add HTI support to adls device info.(mdroper)

v4:
- Rebase on TGL patch for applying WAs based on stepping info from
  Matt Roper's feedback.(aswarup)

Bspec: 53597
Bspec: 53648
Bspec: 53655
Bspec: 48028
Bspec: 53650
BSpec: 50422

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 ++++++
 drivers/gpu/drm/i915/i915_drv.h             | 27 ++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_pci.c             | 13 ++++++++++
 drivers/gpu/drm/i915/intel_device_info.c    |  1 +
 drivers/gpu/drm/i915/intel_device_info.h    |  1 +
 include/drm/i915_pciids.h                   | 11 +++++++++
 6 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 111d01e2f81e..c89bd653af17 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -84,6 +84,14 @@ const struct i915_rev_steppings tgl_revid_step_tbl[] = {
 	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
 };
 
+const struct i915_rev_steppings adls_revid_step_tbl[] = {
+	[ADLS_REVID_A0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
+	[ADLS_REVID_A2] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
+	[ADLS_REVID_B0] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
+	[ADLS_REVID_G0] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
+	[ADLS_REVID_C0] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
+};
+
 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
 {
 	wal->name = name;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11d6e8abde46..8d8a046a7b0c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1417,6 +1417,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
+#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
@@ -1560,6 +1561,7 @@ extern const struct i915_rev_steppings kbl_revids[];
 
 enum {
 	STEP_A0,
+	STEP_A2,
 	STEP_B0,
 	STEP_B1,
 	STEP_C0,
@@ -1568,9 +1570,11 @@ enum {
 
 #define TGL_UY_REVID_STEP_TBL_SIZE	4
 #define TGL_REVID_STEP_TBL_SIZE		2
+#define ADLS_REVID_STEP_TBL_SIZE	13
 
 extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
 extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
+extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];
 
 static inline const struct i915_rev_steppings *
 tgl_stepping_get(struct drm_i915_private *dev_priv)
@@ -1579,7 +1583,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
 	u8 size;
 	const struct i915_rev_steppings *revid_step_tbl;
 
-	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		revid_step_tbl = adls_revid_step_tbl;
+		size = ARRAY_SIZE(adls_revid_step_tbl);
+	} else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
 		revid_step_tbl = tgl_uy_revid_step_tbl;
 		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
 	} else {
@@ -1621,6 +1628,24 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
 #define IS_DG1_REVID(p, since, until) \
 	(IS_DG1(p) && IS_REVID(p, since, until))
 
+#define ADLS_REVID_A0		0x0
+#define ADLS_REVID_A2		0x1
+#define ADLS_REVID_B0		0x4
+#define ADLS_REVID_G0		0x8
+#define ADLS_REVID_C0		0xC /*Same as H0 ADLS SOC stepping*/
+
+extern const struct i915_rev_steppings adls_revids[];
+
+#define IS_ADLS_DISP_STEPPING(p, since, until) \
+	(IS_ALDERLAKE_S(p) && \
+	 tgl_stepping_get(p)->disp_stepping >= (since) && \
+	 tgl_stepping_get(p)->disp_stepping <= (until))
+
+#define IS_ADLS_GT_STEPPING(p, since, until) \
+	(IS_ALDERLAKE_S(p) && \
+	 tgl_stepping_get(p)->gt_stepping >= (since) && \
+	 tgl_stepping_get(p)->gt_stepping <= (until))
+
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 11fe790b1969..26e4bf8bb4ef 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -925,6 +925,18 @@ static const struct intel_device_info dg1_info __maybe_unused = {
 	.ppgtt_size = 47,
 };
 
+static const struct intel_device_info adl_s_info = {
+	GEN12_FEATURES,
+	PLATFORM(INTEL_ALDERLAKE_S),
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+	.require_force_probe = 1,
+	.display.has_hti = 1,
+	.display.has_psr_hw_tracking = 0,
+	.platform_engine_mask =
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+	.dma_mask_size = 46,
+};
+
 #undef GEN
 #undef PLATFORM
 
@@ -1001,6 +1013,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_JSL_IDS(&jsl_info),
 	INTEL_TGL_12_IDS(&tgl_info),
 	INTEL_RKL_IDS(&rkl_info),
+	INTEL_ADLS_IDS(&adl_s_info),
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f2d5ae59081e..699412c14c1d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -66,6 +66,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(TIGERLAKE),
 	PLATFORM_NAME(ROCKETLAKE),
 	PLATFORM_NAME(DG1),
+	PLATFORM_NAME(ALDERLAKE_S),
 };
 #undef PLATFORM_NAME
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 17d0fdb94d2d..d09857cdc954 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -84,6 +84,7 @@ enum intel_platform {
 	INTEL_TIGERLAKE,
 	INTEL_ROCKETLAKE,
 	INTEL_DG1,
+	INTEL_ALDERLAKE_S,
 	INTEL_MAX_PLATFORMS
 };
 
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 931e46191047..ebd0dd1c35b3 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -634,4 +634,15 @@
 	INTEL_VGA_DEVICE(0x4907, info), \
 	INTEL_VGA_DEVICE(0x4908, info)
 
+/* ADL-S */
+#define INTEL_ADLS_IDS(info) \
+	INTEL_VGA_DEVICE(0x4680, info), \
+	INTEL_VGA_DEVICE(0x4681, info), \
+	INTEL_VGA_DEVICE(0x4682, info), \
+	INTEL_VGA_DEVICE(0x4683, info), \
+	INTEL_VGA_DEVICE(0x4690, info), \
+	INTEL_VGA_DEVICE(0x4691, info), \
+	INTEL_VGA_DEVICE(0x4692, info), \
+	INTEL_VGA_DEVICE(0x4693, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
2.27.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-08 23:18 ` [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs Aditya Swarup
@ 2021-01-08 23:44   ` Matt Roper
  2021-01-11 20:13     ` Jani Nikula
  0 siblings, 1 reply; 24+ messages in thread
From: Matt Roper @ 2021-01-08 23:44 UTC (permalink / raw)
  To: Aditya Swarup; +Cc: intel-gfx, Lucas De Marchi

On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
> TGL adds another level of indirection for applying WA based on stepping
> information rather than PCI REVID. So change TGL_REVID enum into
> stepping enum and use PCI REVID as index into revid to stepping table to
> fetch correct display and GT stepping for application of WAs as
> suggested by Matt Roper.

So to clarify the goal is to rename "revid" -> "stepping" because the
values like "A1," "C0," etc. are't the actual PCI revision ID, but
rather descriptions of the stepping of a given IP block; the enum values
we use to represent those are arbitrary and don't matter as long as
they're monotonically increasing for comparisons.  The PCI revision ID
is just the input we use today to deduce what the IP steppings are, and
there's talk that we could determine the IP steppings in a different way
at some point in the future.

Furthermore, since the same scheme will be used at least for ADL-S, we
should drop the "TGL" prefix since there's no need to name these general
enum values in a platform-specific manner.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

We should probably make the same kind of change to KBL (and use the same
stepping enum) too since it has the same kind of extra indirection as
TGL/ADL-S, but we can do that as a followup patch.


Matt

> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
>  drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>  6 files changed, 43 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d52374f01316..bb04b502a442 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>  	int config, i;
>  
>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
>  		/* Wa_1409767108:tgl,dg1 */
>  		table = wa_1409767108_buddy_page_masks;
>  	else
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index c24ae69426cf..a93717178957 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
>  		/* WA 1408330847 */
> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> +		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  
>  	/* WA 1408330847 */
>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> +	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index cf3589fd0ddb..4ce32df3855f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>  {
>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
>  		return false;
>  
>  	return plane_id < PLANE_SPRITE4;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c21a9726326a..111d01e2f81e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
>  	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
>  };
>  
> -const struct i915_rev_steppings tgl_uy_revids[] = {
> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
> +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
> +	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
> +	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
>  };
>  
>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
> -const struct i915_rev_steppings tgl_revids[] = {
> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
> +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>  };
>  
>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
> @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  	gen12_gt_workarounds_init(i915, wal);
>  
>  	/* Wa_1409420604:tgl */
> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>  		wa_write_or(wal,
>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>  			    CPSSUNIT_CLKGATE_DIS);
>  
>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>  
>  	/* Wa_1408615072:tgl[a0] */
> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>  			    VSUNIT_CLKGATE_DIS_TGL);
>  }
> @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  	struct drm_i915_private *i915 = engine->i915;
>  
>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> +	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>  		/*
>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>  		 * Wa_1607063988:tgl[a0],dg1[a0]
> @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>  	}
>  
> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>  		/*
>  		 * Wa_1606679103:tgl
>  		 * (see also Wa_1606682166:icl)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5e5bcef20e33..11d6e8abde46 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
>  
>  enum {
> -	TGL_REVID_A0,
> -	TGL_REVID_B0,
> -	TGL_REVID_B1,
> -	TGL_REVID_C0,
> -	TGL_REVID_D0,
> +	STEP_A0,
> +	STEP_B0,
> +	STEP_B1,
> +	STEP_C0,
> +	STEP_D0,
>  };
>  
> -#define TGL_UY_REVIDS_SIZE	4
> -#define TGL_REVIDS_SIZE		2
> +#define TGL_UY_REVID_STEP_TBL_SIZE	4
> +#define TGL_REVID_STEP_TBL_SIZE		2
>  
> -extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
> -extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
> +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
> +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
>  
>  static inline const struct i915_rev_steppings *
> -tgl_revids_get(struct drm_i915_private *dev_priv)
> +tgl_stepping_get(struct drm_i915_private *dev_priv)
>  {
>  	u8 revid = INTEL_REVID(dev_priv);
>  	u8 size;
> -	const struct i915_rev_steppings *tgl_revid_tbl;
> +	const struct i915_rev_steppings *revid_step_tbl;
>  
>  	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> -		tgl_revid_tbl = tgl_uy_revids;
> -		size = ARRAY_SIZE(tgl_uy_revids);
> +		revid_step_tbl = tgl_uy_revid_step_tbl;
> +		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>  	} else {
> -		tgl_revid_tbl = tgl_revids;
> -		size = ARRAY_SIZE(tgl_revids);
> +		revid_step_tbl = tgl_revid_step_tbl;
> +		size = ARRAY_SIZE(tgl_revid_step_tbl);
>  	}
>  
>  	revid = min_t(u8, revid, size - 1);
>  
> -	return &tgl_revid_tbl[revid];
> +	return &revid_step_tbl[revid];
>  }
>  
> -#define IS_TGL_DISP_REVID(p, since, until) \
> +#define IS_TGL_DISP_STEPPING(p, since, until) \
>  	(IS_TIGERLAKE(p) && \
> -	 tgl_revids_get(p)->disp_stepping >= (since) && \
> -	 tgl_revids_get(p)->disp_stepping <= (until))
> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
> +	 tgl_stepping_get(p)->disp_stepping <= (until))
>  
> -#define IS_TGL_UY_GT_REVID(p, since, until) \
> +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
>  	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
> -	 tgl_revids_get(p)->gt_stepping <= (until))
> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>  
> -#define IS_TGL_GT_REVID(p, since, until) \
> +#define IS_TGL_GT_STEPPING(p, since, until) \
>  	(IS_TIGERLAKE(p) && \
>  	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
> -	 tgl_revids_get(p)->gt_stepping <= (until))
> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>  
>  #define RKL_REVID_A0		0x0
>  #define RKL_REVID_B0		0x1
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bbc73df7f753..319acca2630b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>  
>  	/* Wa_1409825376:tgl (pre-prod)*/
> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
> +	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>  			   TGL_VRH_GATING_DIS);
>  
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids
  2021-01-08 23:18 ` [Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
@ 2021-01-09  0:20   ` Matt Roper
  2021-01-11 19:37     ` Aditya Swarup
  0 siblings, 1 reply; 24+ messages in thread
From: Matt Roper @ 2021-01-09  0:20 UTC (permalink / raw)
  To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi

On Fri, Jan 08, 2021 at 03:18:53PM -0800, Aditya Swarup wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
> 
> - Add the initial platform information for Alderlake-S.
> - Specify ppgtt_size value
> - Add dma_mask_size
> - Add ADLS REVIDs
> - HW tracking(Selective Update Tracking Enable) has been
>   removed from ADLS. Disable PSR2 till we enable software/
>   manual tracking.
> 
> v2:
> - Add support for different ADLS SOC steppings to select
>   correct GT/DISP stepping based on Bspec 53655 based on
>   feedback from Matt Roper.(aswarup)
> 
> v3:
> - Make display/gt steppings info generic for reuse with TGL and ADLS.
> - Modify the macros to reuse tgl_revids_get()
> - Add HTI support to adls device info.(mdroper)
> 
> v4:
> - Rebase on TGL patch for applying WAs based on stepping info from
>   Matt Roper's feedback.(aswarup)
> 
> Bspec: 53597
> Bspec: 53648
> Bspec: 53655
> Bspec: 48028
> Bspec: 53650
> BSpec: 50422
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 ++++++
>  drivers/gpu/drm/i915/i915_drv.h             | 27 ++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_pci.c             | 13 ++++++++++
>  drivers/gpu/drm/i915/intel_device_info.c    |  1 +
>  drivers/gpu/drm/i915/intel_device_info.h    |  1 +
>  include/drm/i915_pciids.h                   | 11 +++++++++
>  6 files changed, 60 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 111d01e2f81e..c89bd653af17 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -84,6 +84,14 @@ const struct i915_rev_steppings tgl_revid_step_tbl[] = {
>  	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>  };
>  
> +const struct i915_rev_steppings adls_revid_step_tbl[] = {
> +	[ADLS_REVID_A0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
> +	[ADLS_REVID_A2] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
> +	[ADLS_REVID_B0] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
> +	[ADLS_REVID_G0] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
> +	[ADLS_REVID_C0] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
> +};

Now that we've disassociated IP steppings from revision ID, I don't
think we should use stepping terminology for the constant inputs to the
array anymore.  The terms you're using seem to roughly correspond to
what the bspec refers to as "SOC stepping" but even that's not terribly
accurate since, for example, PCI revision ID 0xC is used for SoC
steppings C0, C1, D0, and H0.  I'd just use the exact numeric PCI ID as
documented in the bspec to remove any ambiguity:

        const struct i915_rev_steppings adls_revid_step_tbl[] = {
                [0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
                [0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
                [0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
                [0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
                [0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
        };

That also matches how we're indexing into the TGL arrays.


Matt

> +
>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>  {
>  	wal->name = name;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 11d6e8abde46..8d8a046a7b0c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1417,6 +1417,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>  #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>  				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>  #define IS_BDW_ULT(dev_priv) \
> @@ -1560,6 +1561,7 @@ extern const struct i915_rev_steppings kbl_revids[];
>  
>  enum {
>  	STEP_A0,
> +	STEP_A2,
>  	STEP_B0,
>  	STEP_B1,
>  	STEP_C0,
> @@ -1568,9 +1570,11 @@ enum {
>  
>  #define TGL_UY_REVID_STEP_TBL_SIZE	4
>  #define TGL_REVID_STEP_TBL_SIZE		2
> +#define ADLS_REVID_STEP_TBL_SIZE	13
>  
>  extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
>  extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
> +extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];
>  
>  static inline const struct i915_rev_steppings *
>  tgl_stepping_get(struct drm_i915_private *dev_priv)
> @@ -1579,7 +1583,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
>  	u8 size;
>  	const struct i915_rev_steppings *revid_step_tbl;
>  
> -	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> +	if (IS_ALDERLAKE_S(dev_priv)) {
> +		revid_step_tbl = adls_revid_step_tbl;
> +		size = ARRAY_SIZE(adls_revid_step_tbl);
> +	} else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>  		revid_step_tbl = tgl_uy_revid_step_tbl;
>  		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>  	} else {
> @@ -1621,6 +1628,24 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
>  #define IS_DG1_REVID(p, since, until) \
>  	(IS_DG1(p) && IS_REVID(p, since, until))
>  
> +#define ADLS_REVID_A0		0x0
> +#define ADLS_REVID_A2		0x1
> +#define ADLS_REVID_B0		0x4
> +#define ADLS_REVID_G0		0x8
> +#define ADLS_REVID_C0		0xC /*Same as H0 ADLS SOC stepping*/
> +
> +extern const struct i915_rev_steppings adls_revids[];
> +
> +#define IS_ADLS_DISP_STEPPING(p, since, until) \
> +	(IS_ALDERLAKE_S(p) && \
> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
> +	 tgl_stepping_get(p)->disp_stepping <= (until))
> +
> +#define IS_ADLS_GT_STEPPING(p, since, until) \
> +	(IS_ALDERLAKE_S(p) && \
> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
> +	 tgl_stepping_get(p)->gt_stepping <= (until))
> +
>  #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
>  #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
>  #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 11fe790b1969..26e4bf8bb4ef 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -925,6 +925,18 @@ static const struct intel_device_info dg1_info __maybe_unused = {
>  	.ppgtt_size = 47,
>  };
>  
> +static const struct intel_device_info adl_s_info = {
> +	GEN12_FEATURES,
> +	PLATFORM(INTEL_ALDERLAKE_S),
> +	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> +	.require_force_probe = 1,
> +	.display.has_hti = 1,
> +	.display.has_psr_hw_tracking = 0,
> +	.platform_engine_mask =
> +		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> +	.dma_mask_size = 46,
> +};
> +
>  #undef GEN
>  #undef PLATFORM
>  
> @@ -1001,6 +1013,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_JSL_IDS(&jsl_info),
>  	INTEL_TGL_12_IDS(&tgl_info),
>  	INTEL_RKL_IDS(&rkl_info),
> +	INTEL_ADLS_IDS(&adl_s_info),
>  	{0, 0, 0}
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index f2d5ae59081e..699412c14c1d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -66,6 +66,7 @@ static const char * const platform_names[] = {
>  	PLATFORM_NAME(TIGERLAKE),
>  	PLATFORM_NAME(ROCKETLAKE),
>  	PLATFORM_NAME(DG1),
> +	PLATFORM_NAME(ALDERLAKE_S),
>  };
>  #undef PLATFORM_NAME
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 17d0fdb94d2d..d09857cdc954 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -84,6 +84,7 @@ enum intel_platform {
>  	INTEL_TIGERLAKE,
>  	INTEL_ROCKETLAKE,
>  	INTEL_DG1,
> +	INTEL_ALDERLAKE_S,
>  	INTEL_MAX_PLATFORMS
>  };
>  
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 931e46191047..ebd0dd1c35b3 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -634,4 +634,15 @@
>  	INTEL_VGA_DEVICE(0x4907, info), \
>  	INTEL_VGA_DEVICE(0x4908, info)
>  
> +/* ADL-S */
> +#define INTEL_ADLS_IDS(info) \
> +	INTEL_VGA_DEVICE(0x4680, info), \
> +	INTEL_VGA_DEVICE(0x4681, info), \
> +	INTEL_VGA_DEVICE(0x4682, info), \
> +	INTEL_VGA_DEVICE(0x4683, info), \
> +	INTEL_VGA_DEVICE(0x4690, info), \
> +	INTEL_VGA_DEVICE(0x4691, info), \
> +	INTEL_VGA_DEVICE(0x4692, info), \
> +	INTEL_VGA_DEVICE(0x4693, info)
> +
>  #endif /* _I915_PCIIDS_H */
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use TGL stepping info and add ADLS platform changes
  2021-01-08 23:18 [Intel-gfx] [PATCH 0/2] Use TGL stepping info and add ADLS platform changes Aditya Swarup
  2021-01-08 23:18 ` [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs Aditya Swarup
  2021-01-08 23:18 ` [Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
@ 2021-01-09  2:21 ` Patchwork
  2021-01-09  2:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2021-01-09 10:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  4 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2021-01-09  2:21 UTC (permalink / raw)
  To: Aditya Swarup; +Cc: intel-gfx

== Series Details ==

Series: Use TGL stepping info and add ADLS platform changes
URL   : https://patchwork.freedesktop.org/series/85639/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8370ee3ba04f drm/i915/tgl: Use TGL stepping info for applying WAs
-:198: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#198: FILE: drivers/gpu/drm/i915/i915_drv.h:1595:
+#define IS_TGL_DISP_STEPPING(p, since, until) \
 	(IS_TIGERLAKE(p) && \
+	 tgl_stepping_get(p)->disp_stepping >= (since) && \
+	 tgl_stepping_get(p)->disp_stepping <= (until))

-:206: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#206: FILE: drivers/gpu/drm/i915/i915_drv.h:1600:
+#define IS_TGL_UY_GT_STEPPING(p, since, until) \
 	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
+	 tgl_stepping_get(p)->gt_stepping >= (since) && \
+	 tgl_stepping_get(p)->gt_stepping <= (until))

-:214: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#214: FILE: drivers/gpu/drm/i915/i915_drv.h:1605:
+#define IS_TGL_GT_STEPPING(p, since, until) \
 	(IS_TIGERLAKE(p) && \
 	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
+	 tgl_stepping_get(p)->gt_stepping >= (since) && \
+	 tgl_stepping_get(p)->gt_stepping <= (until))

total: 0 errors, 0 warnings, 3 checks, 182 lines checked
6e0b18efc188 drm/i915/adl_s: Add ADL-S platform info and PCI ids
-:123: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#123: FILE: drivers/gpu/drm/i915/i915_drv.h:1639:
+#define IS_ADLS_DISP_STEPPING(p, since, until) \
+	(IS_ALDERLAKE_S(p) && \
+	 tgl_stepping_get(p)->disp_stepping >= (since) && \
+	 tgl_stepping_get(p)->disp_stepping <= (until))

-:128: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#128: FILE: drivers/gpu/drm/i915/i915_drv.h:1644:
+#define IS_ADLS_GT_STEPPING(p, since, until) \
+	(IS_ALDERLAKE_S(p) && \
+	 tgl_stepping_get(p)->gt_stepping >= (since) && \
+	 tgl_stepping_get(p)->gt_stepping <= (until))

-:200: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#200: FILE: include/drm/i915_pciids.h:638:
+#define INTEL_ADLS_IDS(info) \
+	INTEL_VGA_DEVICE(0x4680, info), \
+	INTEL_VGA_DEVICE(0x4681, info), \
+	INTEL_VGA_DEVICE(0x4682, info), \
+	INTEL_VGA_DEVICE(0x4683, info), \
+	INTEL_VGA_DEVICE(0x4690, info), \
+	INTEL_VGA_DEVICE(0x4691, info), \
+	INTEL_VGA_DEVICE(0x4692, info), \
+	INTEL_VGA_DEVICE(0x4693, info)

-:200: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#200: FILE: include/drm/i915_pciids.h:638:
+#define INTEL_ADLS_IDS(info) \
+	INTEL_VGA_DEVICE(0x4680, info), \
+	INTEL_VGA_DEVICE(0x4681, info), \
+	INTEL_VGA_DEVICE(0x4682, info), \
+	INTEL_VGA_DEVICE(0x4683, info), \
+	INTEL_VGA_DEVICE(0x4690, info), \
+	INTEL_VGA_DEVICE(0x4691, info), \
+	INTEL_VGA_DEVICE(0x4692, info), \
+	INTEL_VGA_DEVICE(0x4693, info)

total: 1 errors, 0 warnings, 3 checks, 128 lines checked


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for Use TGL stepping info and add ADLS platform changes
  2021-01-08 23:18 [Intel-gfx] [PATCH 0/2] Use TGL stepping info and add ADLS platform changes Aditya Swarup
                   ` (2 preceding siblings ...)
  2021-01-09  2:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use TGL stepping info and add ADLS platform changes Patchwork
@ 2021-01-09  2:50 ` Patchwork
  2021-01-09 10:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  4 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2021-01-09  2:50 UTC (permalink / raw)
  To: Aditya Swarup; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 3949 bytes --]

== Series Details ==

Series: Use TGL stepping info and add ADLS platform changes
URL   : https://patchwork.freedesktop.org/series/85639/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9570 -> Patchwork_19303
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/index.html

Known issues
------------

  Here are the changes found in Patchwork_19303 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@memory-alloc:
    - fi-tgl-y:           NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-tgl-y/igt@amdgpu/amd_basic@memory-alloc.html

  * igt@gem_huc_copy@huc-copy:
    - fi-byt-j1900:       NOTRUN -> [SKIP][2] ([fdo#109271]) +27 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-byt-j1900/igt@gem_huc_copy@huc-copy.html

  * igt@gem_render_tiled_blits@basic:
    - fi-tgl-y:           [PASS][3] -> [DMESG-WARN][4] ([i915#402])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-tgl-y/igt@gem_render_tiled_blits@basic.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-byt-j1900:       NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-byt-j1900/igt@kms_chamelium@hdmi-crc-fast.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - fi-tgl-y:           [DMESG-WARN][6] ([i915#402]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s0:
    - fi-tgl-u2:          [FAIL][8] ([i915#1888]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-kbl-7500u:       [DMESG-WARN][10] ([i915#2868]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (42 -> 38)
------------------------------

  Additional (1): fi-byt-j1900 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9570 -> Patchwork_19303

  CI-20190529: 20190529
  CI_DRM_9570: 0c67d33cc01c40bc40213adb42e6420db337bb84 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5952: c946985af198e8f859c3c08fd562b09686fa387b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19303: 6e0b18efc188ea6ba3d95227f5422c87974ecb81 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6e0b18efc188 drm/i915/adl_s: Add ADL-S platform info and PCI ids
8370ee3ba04f drm/i915/tgl: Use TGL stepping info for applying WAs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for Use TGL stepping info and add ADLS platform changes
  2021-01-08 23:18 [Intel-gfx] [PATCH 0/2] Use TGL stepping info and add ADLS platform changes Aditya Swarup
                   ` (3 preceding siblings ...)
  2021-01-09  2:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-01-09 10:58 ` Patchwork
  4 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2021-01-09 10:58 UTC (permalink / raw)
  To: Aditya Swarup; +Cc: intel-gfx


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== Series Details ==

Series: Use TGL stepping info and add ADLS platform changes
URL   : https://patchwork.freedesktop.org/series/85639/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9570_full -> Patchwork_19303_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19303_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2}:
    - shard-iclb:         [SKIP][1] ([i915#2920]) -> [SKIP][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html

  
Known issues
------------

  Here are the changes found in Patchwork_19303_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_whisper@basic-queues-all:
    - shard-glk:          [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-glk4/igt@gem_exec_whisper@basic-queues-all.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-glk9/igt@gem_exec_whisper@basic-queues-all.html

  * igt@gem_render_copy@linear-to-vebox-yf-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][5] ([i915#768]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb1/igt@gem_render_copy@linear-to-vebox-yf-tiled.html

  * igt@kms_chamelium@hdmi-hpd-after-suspend:
    - shard-iclb:         NOTRUN -> [SKIP][6] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb1/igt@kms_chamelium@hdmi-hpd-after-suspend.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
    - shard-skl:          NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl8/igt@kms_chamelium@vga-hpd-after-suspend.html

  * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
    - shard-tglb:         NOTRUN -> [SKIP][8] ([fdo#109284] / [fdo#111827]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-tglb8/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
    - shard-iclb:         NOTRUN -> [SKIP][9] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb1/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
    - shard-skl:          NOTRUN -> [FAIL][10] ([i915#54])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([i915#54]) +9 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
    - shard-iclb:         NOTRUN -> [SKIP][13] ([fdo#109278] / [fdo#109279])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html
    - shard-tglb:         NOTRUN -> [SKIP][14] ([fdo#109279])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][15] ([fdo#109274])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb1/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          NOTRUN -> [FAIL][16] ([i915#2122]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate@b-edp1:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#2122]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl5/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl5/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
    - shard-tglb:         NOTRUN -> [SKIP][19] ([i915#2587])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-tglb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
    - shard-skl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2642])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-iclb:         NOTRUN -> [SKIP][21] ([fdo#109280]) +5 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][22] ([fdo#111825]) +6 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-tglb8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-iclb:         NOTRUN -> [SKIP][23] ([fdo#109278]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][24] ([fdo#108145] / [i915#265])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-d-tiling-yf:
    - shard-skl:          NOTRUN -> [SKIP][27] ([fdo#109271]) +27 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl8/igt@kms_plane_lowres@pipe-d-tiling-yf.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         NOTRUN -> [SKIP][28] ([fdo#109441])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb1/igt@kms_psr@psr2_basic.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#1542])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl7/igt@perf@polling-parameterized.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl8/igt@perf@polling-parameterized.html

  
#### Possible fixes ####

  * {igt@gem_exec_fair@basic-none-share@rcs0}:
    - shard-iclb:         [FAIL][33] ([i915#2842]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html

  * {igt@gem_exec_fair@basic-none-solo@rcs0}:
    - shard-glk:          [FAIL][35] ([i915#2842]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-glk8/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-glk2/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * {igt@gem_exec_fair@basic-pace-solo@rcs0}:
    - shard-kbl:          [FAIL][37] ([i915#2842]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * {igt@gem_exec_fair@basic-pace@vcs1}:
    - shard-kbl:          [SKIP][39] ([fdo#109271]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html

  * {igt@gem_exec_schedule@u-fairslice@rcs0}:
    - shard-iclb:         [DMESG-WARN][41] ([i915#2803]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb5/igt@gem_exec_schedule@u-fairslice@rcs0.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb1/igt@gem_exec_schedule@u-fairslice@rcs0.html
    - shard-skl:          [DMESG-WARN][43] ([i915#1610] / [i915#2803]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl2/igt@gem_exec_schedule@u-fairslice@rcs0.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl6/igt@gem_exec_schedule@u-fairslice@rcs0.html

  * {igt@gem_exec_schedule@u-fairslice@vcs0}:
    - shard-tglb:         [DMESG-WARN][45] ([i915#2803]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-tglb5/igt@gem_exec_schedule@u-fairslice@vcs0.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-tglb8/igt@gem_exec_schedule@u-fairslice@vcs0.html

  * {igt@gem_spin_batch@resubmit-all@rcs0}:
    - shard-iclb:         [FAIL][47] -> [PASS][48] +3 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb4/igt@gem_spin_batch@resubmit-all@rcs0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb8/igt@gem_spin_batch@resubmit-all@rcs0.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][49] ([i915#454]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb2/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-skl:          [INCOMPLETE][51] ([i915#151]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl1/igt@i915_pm_rpm@system-suspend-modeset.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl8/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@i915_selftest@live@gt_heartbeat:
    - shard-skl:          [DMESG-FAIL][53] ([i915#2291] / [i915#541]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl4/igt@i915_selftest@live@gt_heartbeat.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl8/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen:
    - shard-skl:          [FAIL][55] ([i915#54]) -> [PASS][56] +5 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled:
    - shard-skl:          [FAIL][57] ([i915#177] / [i915#52] / [i915#54]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl7/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl10/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [FAIL][59] ([i915#79]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
    - shard-skl:          [FAIL][61] ([i915#2122]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][65] ([fdo#109441]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          [FAIL][67] ([i915#454]) -> [INCOMPLETE][68] ([i915#198])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-skl6/igt@i915_pm_dc@dc6-psr.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-skl2/igt@i915_pm_dc@dc6-psr.html

  * igt@runner@aborted:
    - shard-iclb:         ([FAIL][69], [FAIL][70], [FAIL][71]) ([i915#1814] / [i915#2295] / [i915#2426] / [i915#2724]) -> ([FAIL][72], [FAIL][73]) ([i915#1814] / [i915#2295] / [i915#2724])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb5/igt@runner@aborted.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb2/igt@runner@aborted.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-iclb5/igt@runner@aborted.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb7/igt@runner@aborted.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-iclb3/igt@runner@aborted.html
    - shard-tglb:         ([FAIL][74], [FAIL][75], [FAIL][76]) ([i915#1814] / [i915#2295] / [i915#2426] / [i915#2667] / [i915#2803] / [i915#456]) -> ([FAIL][77], [FAIL][78]) ([i915#1814] / [i915#2295] / [i915#2667] / [i915#456])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-tglb8/igt@runner@aborted.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-tglb2/igt@runner@aborted.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9570/shard-tglb5/igt@runner@aborted.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-tglb8/igt@runner@aborted.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/shard-tglb1/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
  [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2667]: https://gitlab.freedesktop.org/drm/intel/issues/2667
  [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
  [i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795
  [i915#2803]: https://gitlab.freedesktop.org/drm/intel/issues/2803
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9570 -> Patchwork_19303

  CI-20190529: 20190529
  CI_DRM_9570: 0c67d33cc01c40bc40213adb42e6420db337bb84 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5952: c946985af198e8f859c3c08fd562b09686fa387b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19303: 6e0b18efc188ea6ba3d95227f5422c87974ecb81 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19303/index.html

[-- Attachment #1.2: Type: text/html, Size: 23796 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids
  2021-01-09  0:20   ` Matt Roper
@ 2021-01-11 19:37     ` Aditya Swarup
  0 siblings, 0 replies; 24+ messages in thread
From: Aditya Swarup @ 2021-01-11 19:37 UTC (permalink / raw)
  To: Matt Roper; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi

On 1/8/21 4:20 PM, Matt Roper wrote:
> On Fri, Jan 08, 2021 at 03:18:53PM -0800, Aditya Swarup wrote:
>> From: Caz Yokoyama <caz.yokoyama@intel.com>
>>
>> - Add the initial platform information for Alderlake-S.
>> - Specify ppgtt_size value
>> - Add dma_mask_size
>> - Add ADLS REVIDs
>> - HW tracking(Selective Update Tracking Enable) has been
>>   removed from ADLS. Disable PSR2 till we enable software/
>>   manual tracking.
>>
>> v2:
>> - Add support for different ADLS SOC steppings to select
>>   correct GT/DISP stepping based on Bspec 53655 based on
>>   feedback from Matt Roper.(aswarup)
>>
>> v3:
>> - Make display/gt steppings info generic for reuse with TGL and ADLS.
>> - Modify the macros to reuse tgl_revids_get()
>> - Add HTI support to adls device info.(mdroper)
>>
>> v4:
>> - Rebase on TGL patch for applying WAs based on stepping info from
>>   Matt Roper's feedback.(aswarup)
>>
>> Bspec: 53597
>> Bspec: 53648
>> Bspec: 53655
>> Bspec: 48028
>> Bspec: 53650
>> BSpec: 50422
>>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 ++++++
>>  drivers/gpu/drm/i915/i915_drv.h             | 27 ++++++++++++++++++++-
>>  drivers/gpu/drm/i915/i915_pci.c             | 13 ++++++++++
>>  drivers/gpu/drm/i915/intel_device_info.c    |  1 +
>>  drivers/gpu/drm/i915/intel_device_info.h    |  1 +
>>  include/drm/i915_pciids.h                   | 11 +++++++++
>>  6 files changed, 60 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 111d01e2f81e..c89bd653af17 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -84,6 +84,14 @@ const struct i915_rev_steppings tgl_revid_step_tbl[] = {
>>  	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>>  };
>>  
>> +const struct i915_rev_steppings adls_revid_step_tbl[] = {
>> +	[ADLS_REVID_A0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
>> +	[ADLS_REVID_A2] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
>> +	[ADLS_REVID_B0] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
>> +	[ADLS_REVID_G0] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
>> +	[ADLS_REVID_C0] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
>> +};
> 
> Now that we've disassociated IP steppings from revision ID, I don't
> think we should use stepping terminology for the constant inputs to the
> array anymore.  The terms you're using seem to roughly correspond to
> what the bspec refers to as "SOC stepping" but even that's not terribly
> accurate since, for example, PCI revision ID 0xC is used for SoC
> steppings C0, C1, D0, and H0.  I'd just use the exact numeric PCI ID as
> documented in the bspec to remove any ambiguity:
> 
>         const struct i915_rev_steppings adls_revid_step_tbl[] = {
>                 [0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
>                 [0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
>                 [0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
>                 [0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
>                 [0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
>         };
> 
> That also matches how we're indexing into the TGL arrays.

I don't think there is a difference between SOC steppings and PCI ids from display and graphics perspective.
As in all the SOC steppings that share the same PCI IDs have the same display and graphics stepping. 

But I do agree with you that changing the index to numeric PCI IDs perhaps removes ambiguity and makes it 
consitent with the tables used for earlier platforms. I have sent a v2 addressing this change.

aswarup
> 
> 
> Matt
> 
>> +
>>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>>  {
>>  	wal->name = name;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 11d6e8abde46..8d8a046a7b0c 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1417,6 +1417,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>>  #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
>> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
>>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>>  				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>>  #define IS_BDW_ULT(dev_priv) \
>> @@ -1560,6 +1561,7 @@ extern const struct i915_rev_steppings kbl_revids[];
>>  
>>  enum {
>>  	STEP_A0,
>> +	STEP_A2,
>>  	STEP_B0,
>>  	STEP_B1,
>>  	STEP_C0,
>> @@ -1568,9 +1570,11 @@ enum {
>>  
>>  #define TGL_UY_REVID_STEP_TBL_SIZE	4
>>  #define TGL_REVID_STEP_TBL_SIZE		2
>> +#define ADLS_REVID_STEP_TBL_SIZE	13
>>  
>>  extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
>>  extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
>> +extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];
>>  
>>  static inline const struct i915_rev_steppings *
>>  tgl_stepping_get(struct drm_i915_private *dev_priv)
>> @@ -1579,7 +1583,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
>>  	u8 size;
>>  	const struct i915_rev_steppings *revid_step_tbl;
>>  
>> -	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>> +	if (IS_ALDERLAKE_S(dev_priv)) {
>> +		revid_step_tbl = adls_revid_step_tbl;
>> +		size = ARRAY_SIZE(adls_revid_step_tbl);
>> +	} else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>>  		revid_step_tbl = tgl_uy_revid_step_tbl;
>>  		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>>  	} else {
>> @@ -1621,6 +1628,24 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
>>  #define IS_DG1_REVID(p, since, until) \
>>  	(IS_DG1(p) && IS_REVID(p, since, until))
>>  
>> +#define ADLS_REVID_A0		0x0
>> +#define ADLS_REVID_A2		0x1
>> +#define ADLS_REVID_B0		0x4
>> +#define ADLS_REVID_G0		0x8
>> +#define ADLS_REVID_C0		0xC /*Same as H0 ADLS SOC stepping*/
>> +
>> +extern const struct i915_rev_steppings adls_revids[];
>> +
>> +#define IS_ADLS_DISP_STEPPING(p, since, until) \
>> +	(IS_ALDERLAKE_S(p) && \
>> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
>> +	 tgl_stepping_get(p)->disp_stepping <= (until))
>> +
>> +#define IS_ADLS_GT_STEPPING(p, since, until) \
>> +	(IS_ALDERLAKE_S(p) && \
>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>> +
>>  #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
>>  #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
>>  #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 11fe790b1969..26e4bf8bb4ef 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -925,6 +925,18 @@ static const struct intel_device_info dg1_info __maybe_unused = {
>>  	.ppgtt_size = 47,
>>  };
>>  
>> +static const struct intel_device_info adl_s_info = {
>> +	GEN12_FEATURES,
>> +	PLATFORM(INTEL_ALDERLAKE_S),
>> +	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>> +	.require_force_probe = 1,
>> +	.display.has_hti = 1,
>> +	.display.has_psr_hw_tracking = 0,
>> +	.platform_engine_mask =
>> +		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>> +	.dma_mask_size = 46,
>> +};
>> +
>>  #undef GEN
>>  #undef PLATFORM
>>  
>> @@ -1001,6 +1013,7 @@ static const struct pci_device_id pciidlist[] = {
>>  	INTEL_JSL_IDS(&jsl_info),
>>  	INTEL_TGL_12_IDS(&tgl_info),
>>  	INTEL_RKL_IDS(&rkl_info),
>> +	INTEL_ADLS_IDS(&adl_s_info),
>>  	{0, 0, 0}
>>  };
>>  MODULE_DEVICE_TABLE(pci, pciidlist);
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index f2d5ae59081e..699412c14c1d 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -66,6 +66,7 @@ static const char * const platform_names[] = {
>>  	PLATFORM_NAME(TIGERLAKE),
>>  	PLATFORM_NAME(ROCKETLAKE),
>>  	PLATFORM_NAME(DG1),
>> +	PLATFORM_NAME(ALDERLAKE_S),
>>  };
>>  #undef PLATFORM_NAME
>>  
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 17d0fdb94d2d..d09857cdc954 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -84,6 +84,7 @@ enum intel_platform {
>>  	INTEL_TIGERLAKE,
>>  	INTEL_ROCKETLAKE,
>>  	INTEL_DG1,
>> +	INTEL_ALDERLAKE_S,
>>  	INTEL_MAX_PLATFORMS
>>  };
>>  
>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> index 931e46191047..ebd0dd1c35b3 100644
>> --- a/include/drm/i915_pciids.h
>> +++ b/include/drm/i915_pciids.h
>> @@ -634,4 +634,15 @@
>>  	INTEL_VGA_DEVICE(0x4907, info), \
>>  	INTEL_VGA_DEVICE(0x4908, info)
>>  
>> +/* ADL-S */
>> +#define INTEL_ADLS_IDS(info) \
>> +	INTEL_VGA_DEVICE(0x4680, info), \
>> +	INTEL_VGA_DEVICE(0x4681, info), \
>> +	INTEL_VGA_DEVICE(0x4682, info), \
>> +	INTEL_VGA_DEVICE(0x4683, info), \
>> +	INTEL_VGA_DEVICE(0x4690, info), \
>> +	INTEL_VGA_DEVICE(0x4691, info), \
>> +	INTEL_VGA_DEVICE(0x4692, info), \
>> +	INTEL_VGA_DEVICE(0x4693, info)
>> +
>>  #endif /* _I915_PCIIDS_H */
>> -- 
>> 2.27.0
>>
> 

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^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-08 23:44   ` Matt Roper
@ 2021-01-11 20:13     ` Jani Nikula
  2021-01-11 20:18       ` Jani Nikula
                         ` (2 more replies)
  0 siblings, 3 replies; 24+ messages in thread
From: Jani Nikula @ 2021-01-11 20:13 UTC (permalink / raw)
  To: Matt Roper, Aditya Swarup; +Cc: intel-gfx, Lucas De Marchi

On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
>> TGL adds another level of indirection for applying WA based on stepping
>> information rather than PCI REVID. So change TGL_REVID enum into
>> stepping enum and use PCI REVID as index into revid to stepping table to
>> fetch correct display and GT stepping for application of WAs as
>> suggested by Matt Roper.
>
> So to clarify the goal is to rename "revid" -> "stepping" because the
> values like "A1," "C0," etc. are't the actual PCI revision ID, but
> rather descriptions of the stepping of a given IP block; the enum values
> we use to represent those are arbitrary and don't matter as long as
> they're monotonically increasing for comparisons.  The PCI revision ID
> is just the input we use today to deduce what the IP steppings are, and
> there's talk that we could determine the IP steppings in a different way
> at some point in the future.
>
> Furthermore, since the same scheme will be used at least for ADL-S, we
> should drop the "TGL" prefix since there's no need to name these general
> enum values in a platform-specific manner.
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> We should probably make the same kind of change to KBL (and use the same
> stepping enum) too since it has the same kind of extra indirection as
> TGL/ADL-S, but we can do that as a followup patch.

FWIW I have a wip series changing the whole thing to abstract steppings
enums that are shared between platforms, but it's in a bit of limbo
because the previous revid changes were applied to drm-intel-gt-next,
and it's fallen pretty far out of sync with drm-intel-next. All of this
really belongs to drm-intel-next, but can't do that until the branches
sync up again.

My series also completely hides the arrays into a separate .c file,
because the externs with direct array access are turning into
nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
the actual array definition to have the sizes in sync, but the compiler
does not check that. Really.

IDK, feels like this merging this series is going to be extra churn.


BR,
Jani.


>
>
> Matt
>
>> 
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> ---
>>  .../drm/i915/display/intel_display_power.c    |  2 +-
>>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
>>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
>>  drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
>>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>>  6 files changed, 43 insertions(+), 43 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index d52374f01316..bb04b502a442 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>>  	int config, i;
>>  
>>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
>>  		/* Wa_1409767108:tgl,dg1 */
>>  		table = wa_1409767108_buddy_page_masks;
>>  	else
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index c24ae69426cf..a93717178957 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>  
>>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
>>  		/* WA 1408330847 */
>> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>> +		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>  
>>  	/* WA 1408330847 */
>>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
>> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>> +	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index cf3589fd0ddb..4ce32df3855f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>>  {
>>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
>>  		return false;
>>  
>>  	return plane_id < PLANE_SPRITE4;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index c21a9726326a..111d01e2f81e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
>>  	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
>>  };
>>  
>> -const struct i915_rev_steppings tgl_uy_revids[] = {
>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
>> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
>> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
>> +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
>> +	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
>> +	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
>>  };
>>  
>>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>> -const struct i915_rev_steppings tgl_revids[] = {
>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
>> +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>>  };
>>  
>>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>> @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>  	gen12_gt_workarounds_init(i915, wal);
>>  
>>  	/* Wa_1409420604:tgl */
>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>  		wa_write_or(wal,
>>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>>  			    CPSSUNIT_CLKGATE_DIS);
>>  
>>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>  		wa_write_or(wal,
>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>>  
>>  	/* Wa_1408615072:tgl[a0] */
>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>>  			    VSUNIT_CLKGATE_DIS_TGL);
>>  }
>> @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  	struct drm_i915_private *i915 = engine->i915;
>>  
>>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>> +	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>  		/*
>>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>>  		 * Wa_1607063988:tgl[a0],dg1[a0]
>> @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>>  	}
>>  
>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>  		/*
>>  		 * Wa_1606679103:tgl
>>  		 * (see also Wa_1606682166:icl)
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 5e5bcef20e33..11d6e8abde46 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
>>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
>>  
>>  enum {
>> -	TGL_REVID_A0,
>> -	TGL_REVID_B0,
>> -	TGL_REVID_B1,
>> -	TGL_REVID_C0,
>> -	TGL_REVID_D0,
>> +	STEP_A0,
>> +	STEP_B0,
>> +	STEP_B1,
>> +	STEP_C0,
>> +	STEP_D0,
>>  };
>>  
>> -#define TGL_UY_REVIDS_SIZE	4
>> -#define TGL_REVIDS_SIZE		2
>> +#define TGL_UY_REVID_STEP_TBL_SIZE	4
>> +#define TGL_REVID_STEP_TBL_SIZE		2
>>  
>> -extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
>> -extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
>> +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
>> +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
>>  
>>  static inline const struct i915_rev_steppings *
>> -tgl_revids_get(struct drm_i915_private *dev_priv)
>> +tgl_stepping_get(struct drm_i915_private *dev_priv)
>>  {
>>  	u8 revid = INTEL_REVID(dev_priv);
>>  	u8 size;
>> -	const struct i915_rev_steppings *tgl_revid_tbl;
>> +	const struct i915_rev_steppings *revid_step_tbl;
>>  
>>  	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>> -		tgl_revid_tbl = tgl_uy_revids;
>> -		size = ARRAY_SIZE(tgl_uy_revids);
>> +		revid_step_tbl = tgl_uy_revid_step_tbl;
>> +		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>>  	} else {
>> -		tgl_revid_tbl = tgl_revids;
>> -		size = ARRAY_SIZE(tgl_revids);
>> +		revid_step_tbl = tgl_revid_step_tbl;
>> +		size = ARRAY_SIZE(tgl_revid_step_tbl);
>>  	}
>>  
>>  	revid = min_t(u8, revid, size - 1);
>>  
>> -	return &tgl_revid_tbl[revid];
>> +	return &revid_step_tbl[revid];
>>  }
>>  
>> -#define IS_TGL_DISP_REVID(p, since, until) \
>> +#define IS_TGL_DISP_STEPPING(p, since, until) \
>>  	(IS_TIGERLAKE(p) && \
>> -	 tgl_revids_get(p)->disp_stepping >= (since) && \
>> -	 tgl_revids_get(p)->disp_stepping <= (until))
>> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
>> +	 tgl_stepping_get(p)->disp_stepping <= (until))
>>  
>> -#define IS_TGL_UY_GT_REVID(p, since, until) \
>> +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
>>  	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>  
>> -#define IS_TGL_GT_REVID(p, since, until) \
>> +#define IS_TGL_GT_STEPPING(p, since, until) \
>>  	(IS_TIGERLAKE(p) && \
>>  	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>  
>>  #define RKL_REVID_A0		0x0
>>  #define RKL_REVID_B0		0x1
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index bbc73df7f753..319acca2630b 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>  
>>  	/* Wa_1409825376:tgl (pre-prod)*/
>> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>> +	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>  			   TGL_VRH_GATING_DIS);
>>  
>> -- 
>> 2.27.0
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 20:13     ` Jani Nikula
@ 2021-01-11 20:18       ` Jani Nikula
  2021-01-11 20:57         ` Matt Roper
  2021-01-11 20:20       ` Aditya Swarup
  2021-01-12  2:04       ` Lucas De Marchi
  2 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-01-11 20:18 UTC (permalink / raw)
  To: Matt Roper, Aditya Swarup; +Cc: intel-gfx, Lucas De Marchi

On Mon, 11 Jan 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
>>> TGL adds another level of indirection for applying WA based on stepping
>>> information rather than PCI REVID. So change TGL_REVID enum into
>>> stepping enum and use PCI REVID as index into revid to stepping table to
>>> fetch correct display and GT stepping for application of WAs as
>>> suggested by Matt Roper.
>>
>> So to clarify the goal is to rename "revid" -> "stepping" because the
>> values like "A1," "C0," etc. are't the actual PCI revision ID, but
>> rather descriptions of the stepping of a given IP block; the enum values
>> we use to represent those are arbitrary and don't matter as long as
>> they're monotonically increasing for comparisons.  The PCI revision ID
>> is just the input we use today to deduce what the IP steppings are, and
>> there's talk that we could determine the IP steppings in a different way
>> at some point in the future.
>>
>> Furthermore, since the same scheme will be used at least for ADL-S, we
>> should drop the "TGL" prefix since there's no need to name these general
>> enum values in a platform-specific manner.
>>
>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>
>> We should probably make the same kind of change to KBL (and use the same
>> stepping enum) too since it has the same kind of extra indirection as
>> TGL/ADL-S, but we can do that as a followup patch.
>
> FWIW I have a wip series changing the whole thing to abstract steppings
> enums that are shared between platforms, but it's in a bit of limbo
> because the previous revid changes were applied to drm-intel-gt-next,
> and it's fallen pretty far out of sync with drm-intel-next. All of this
> really belongs to drm-intel-next, but can't do that until the branches
> sync up again.

Btw this series doesn't apply to drm-intel-next either, for the same
reason, and the ADL-S platform definition and PCI IDs must *not* be
applied to drm-intel-gt-next.

BR,
Jani.

>
> My series also completely hides the arrays into a separate .c file,
> because the externs with direct array access are turning into
> nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
> the actual array definition to have the sizes in sync, but the compiler
> does not check that. Really.
>
> IDK, feels like this merging this series is going to be extra churn.
>
>
> BR,
> Jani.
>
>
>>
>>
>> Matt
>>
>>> 
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>>> ---
>>>  .../drm/i915/display/intel_display_power.c    |  2 +-
>>>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
>>>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
>>>  drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
>>>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>>>  6 files changed, 43 insertions(+), 43 deletions(-)
>>> 
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> index d52374f01316..bb04b502a442 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>>>  	int config, i;
>>>  
>>>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
>>>  		/* Wa_1409767108:tgl,dg1 */
>>>  		table = wa_1409767108_buddy_page_masks;
>>>  	else
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index c24ae69426cf..a93717178957 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>>  
>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
>>>  		/* WA 1408330847 */
>>> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>> +		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>>>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>>> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>>  
>>>  	/* WA 1408330847 */
>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
>>> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>> +	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>>>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> index cf3589fd0ddb..4ce32df3855f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>>>  {
>>>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>>>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
>>>  		return false;
>>>  
>>>  	return plane_id < PLANE_SPRITE4;
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index c21a9726326a..111d01e2f81e 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
>>>  	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
>>>  };
>>>  
>>> -const struct i915_rev_steppings tgl_uy_revids[] = {
>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
>>> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
>>> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
>>> +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
>>> +	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
>>> +	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
>>>  };
>>>  
>>>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>>> -const struct i915_rev_steppings tgl_revids[] = {
>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
>>> +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>>>  };
>>>  
>>>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>>> @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>>  	gen12_gt_workarounds_init(i915, wal);
>>>  
>>>  	/* Wa_1409420604:tgl */
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>  		wa_write_or(wal,
>>>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>>>  			    CPSSUNIT_CLKGATE_DIS);
>>>  
>>>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>  		wa_write_or(wal,
>>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>>>  
>>>  	/* Wa_1408615072:tgl[a0] */
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>>>  			    VSUNIT_CLKGATE_DIS_TGL);
>>>  }
>>> @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>  	struct drm_i915_private *i915 = engine->i915;
>>>  
>>>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>>> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>> +	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>  		/*
>>>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>>>  		 * Wa_1607063988:tgl[a0],dg1[a0]
>>> @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>>>  	}
>>>  
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>  		/*
>>>  		 * Wa_1606679103:tgl
>>>  		 * (see also Wa_1606682166:icl)
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 5e5bcef20e33..11d6e8abde46 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
>>>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
>>>  
>>>  enum {
>>> -	TGL_REVID_A0,
>>> -	TGL_REVID_B0,
>>> -	TGL_REVID_B1,
>>> -	TGL_REVID_C0,
>>> -	TGL_REVID_D0,
>>> +	STEP_A0,
>>> +	STEP_B0,
>>> +	STEP_B1,
>>> +	STEP_C0,
>>> +	STEP_D0,
>>>  };
>>>  
>>> -#define TGL_UY_REVIDS_SIZE	4
>>> -#define TGL_REVIDS_SIZE		2
>>> +#define TGL_UY_REVID_STEP_TBL_SIZE	4
>>> +#define TGL_REVID_STEP_TBL_SIZE		2
>>>  
>>> -extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
>>> -extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
>>> +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
>>> +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
>>>  
>>>  static inline const struct i915_rev_steppings *
>>> -tgl_revids_get(struct drm_i915_private *dev_priv)
>>> +tgl_stepping_get(struct drm_i915_private *dev_priv)
>>>  {
>>>  	u8 revid = INTEL_REVID(dev_priv);
>>>  	u8 size;
>>> -	const struct i915_rev_steppings *tgl_revid_tbl;
>>> +	const struct i915_rev_steppings *revid_step_tbl;
>>>  
>>>  	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>>> -		tgl_revid_tbl = tgl_uy_revids;
>>> -		size = ARRAY_SIZE(tgl_uy_revids);
>>> +		revid_step_tbl = tgl_uy_revid_step_tbl;
>>> +		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>>>  	} else {
>>> -		tgl_revid_tbl = tgl_revids;
>>> -		size = ARRAY_SIZE(tgl_revids);
>>> +		revid_step_tbl = tgl_revid_step_tbl;
>>> +		size = ARRAY_SIZE(tgl_revid_step_tbl);
>>>  	}
>>>  
>>>  	revid = min_t(u8, revid, size - 1);
>>>  
>>> -	return &tgl_revid_tbl[revid];
>>> +	return &revid_step_tbl[revid];
>>>  }
>>>  
>>> -#define IS_TGL_DISP_REVID(p, since, until) \
>>> +#define IS_TGL_DISP_STEPPING(p, since, until) \
>>>  	(IS_TIGERLAKE(p) && \
>>> -	 tgl_revids_get(p)->disp_stepping >= (since) && \
>>> -	 tgl_revids_get(p)->disp_stepping <= (until))
>>> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
>>> +	 tgl_stepping_get(p)->disp_stepping <= (until))
>>>  
>>> -#define IS_TGL_UY_GT_REVID(p, since, until) \
>>> +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
>>>  	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>  
>>> -#define IS_TGL_GT_REVID(p, since, until) \
>>> +#define IS_TGL_GT_STEPPING(p, since, until) \
>>>  	(IS_TIGERLAKE(p) && \
>>>  	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>  
>>>  #define RKL_REVID_A0		0x0
>>>  #define RKL_REVID_B0		0x1
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index bbc73df7f753..319acca2630b 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>>  
>>>  	/* Wa_1409825376:tgl (pre-prod)*/
>>> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>>> +	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
>>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>>  			   TGL_VRH_GATING_DIS);
>>>  
>>> -- 
>>> 2.27.0
>>> 

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 20:13     ` Jani Nikula
  2021-01-11 20:18       ` Jani Nikula
@ 2021-01-11 20:20       ` Aditya Swarup
  2021-01-12 16:11         ` Jani Nikula
  2021-01-12  2:04       ` Lucas De Marchi
  2 siblings, 1 reply; 24+ messages in thread
From: Aditya Swarup @ 2021-01-11 20:20 UTC (permalink / raw)
  To: Jani Nikula, Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On 1/11/21 12:13 PM, Jani Nikula wrote:
> On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
>>> TGL adds another level of indirection for applying WA based on stepping
>>> information rather than PCI REVID. So change TGL_REVID enum into
>>> stepping enum and use PCI REVID as index into revid to stepping table to
>>> fetch correct display and GT stepping for application of WAs as
>>> suggested by Matt Roper.
>>
>> So to clarify the goal is to rename "revid" -> "stepping" because the
>> values like "A1," "C0," etc. are't the actual PCI revision ID, but
>> rather descriptions of the stepping of a given IP block; the enum values
>> we use to represent those are arbitrary and don't matter as long as
>> they're monotonically increasing for comparisons.  The PCI revision ID
>> is just the input we use today to deduce what the IP steppings are, and
>> there's talk that we could determine the IP steppings in a different way
>> at some point in the future.
>>
>> Furthermore, since the same scheme will be used at least for ADL-S, we
>> should drop the "TGL" prefix since there's no need to name these general
>> enum values in a platform-specific manner.
>>
>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>
>> We should probably make the same kind of change to KBL (and use the same
>> stepping enum) too since it has the same kind of extra indirection as
>> TGL/ADL-S, but we can do that as a followup patch.
> 
> FWIW I have a wip series changing the whole thing to abstract steppings
> enums that are shared between platforms, but it's in a bit of limbo
> because the previous revid changes were applied to drm-intel-gt-next,
> and it's fallen pretty far out of sync with drm-intel-next. All of this
> really belongs to drm-intel-next, but can't do that until the branches
> sync up again.
> 
> My series also completely hides the arrays into a separate .c file,
> because the externs with direct array access are turning into
> nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
> the actual array definition to have the sizes in sync, but the compiler
> does not check that. Really.
> 
> IDK, feels like this merging this series is going to be extra churn.

We need ADLS support on drm-tip by WW05 and I don't think this should change anything
as far as rebase is concerned as it will be just deletion of this entire section to move 
into the separate stepping/revid file in your implementation. 

I think as a stop gap and to achieve the goal of ADLS patches being pushed in, these patches
look good enough. If extern/array declaration was a concern, why were the KBL/TGL pathces accepted
in the first place?

I will be happy to help with the rebase but the process of pushing ADLS patches is stuck because of this.

Regards,
aswarup
> 
> 
> BR,
> Jani.
> 
> 
>>
>>
>> Matt
>>
>>>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>>> ---
>>>  .../drm/i915/display/intel_display_power.c    |  2 +-
>>>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
>>>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
>>>  drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
>>>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>>>  6 files changed, 43 insertions(+), 43 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> index d52374f01316..bb04b502a442 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>>>  	int config, i;
>>>  
>>>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
>>>  		/* Wa_1409767108:tgl,dg1 */
>>>  		table = wa_1409767108_buddy_page_masks;
>>>  	else
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index c24ae69426cf..a93717178957 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>>  
>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
>>>  		/* WA 1408330847 */
>>> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>> +		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>>>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>>> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>>  
>>>  	/* WA 1408330847 */
>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
>>> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>> +	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>>>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> index cf3589fd0ddb..4ce32df3855f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>>>  {
>>>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>>>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
>>>  		return false;
>>>  
>>>  	return plane_id < PLANE_SPRITE4;
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index c21a9726326a..111d01e2f81e 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
>>>  	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
>>>  };
>>>  
>>> -const struct i915_rev_steppings tgl_uy_revids[] = {
>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
>>> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
>>> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
>>> +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
>>> +	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
>>> +	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
>>>  };
>>>  
>>>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>>> -const struct i915_rev_steppings tgl_revids[] = {
>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
>>> +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>>>  };
>>>  
>>>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>>> @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>>  	gen12_gt_workarounds_init(i915, wal);
>>>  
>>>  	/* Wa_1409420604:tgl */
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>  		wa_write_or(wal,
>>>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>>>  			    CPSSUNIT_CLKGATE_DIS);
>>>  
>>>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>  		wa_write_or(wal,
>>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>>>  
>>>  	/* Wa_1408615072:tgl[a0] */
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>>>  			    VSUNIT_CLKGATE_DIS_TGL);
>>>  }
>>> @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>  	struct drm_i915_private *i915 = engine->i915;
>>>  
>>>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>>> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>> +	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>  		/*
>>>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>>>  		 * Wa_1607063988:tgl[a0],dg1[a0]
>>> @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>>>  	}
>>>  
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>  		/*
>>>  		 * Wa_1606679103:tgl
>>>  		 * (see also Wa_1606682166:icl)
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 5e5bcef20e33..11d6e8abde46 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
>>>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
>>>  
>>>  enum {
>>> -	TGL_REVID_A0,
>>> -	TGL_REVID_B0,
>>> -	TGL_REVID_B1,
>>> -	TGL_REVID_C0,
>>> -	TGL_REVID_D0,
>>> +	STEP_A0,
>>> +	STEP_B0,
>>> +	STEP_B1,
>>> +	STEP_C0,
>>> +	STEP_D0,
>>>  };
>>>  
>>> -#define TGL_UY_REVIDS_SIZE	4
>>> -#define TGL_REVIDS_SIZE		2
>>> +#define TGL_UY_REVID_STEP_TBL_SIZE	4
>>> +#define TGL_REVID_STEP_TBL_SIZE		2
>>>  
>>> -extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
>>> -extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
>>> +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
>>> +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
>>>  
>>>  static inline const struct i915_rev_steppings *
>>> -tgl_revids_get(struct drm_i915_private *dev_priv)
>>> +tgl_stepping_get(struct drm_i915_private *dev_priv)
>>>  {
>>>  	u8 revid = INTEL_REVID(dev_priv);
>>>  	u8 size;
>>> -	const struct i915_rev_steppings *tgl_revid_tbl;
>>> +	const struct i915_rev_steppings *revid_step_tbl;
>>>  
>>>  	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>>> -		tgl_revid_tbl = tgl_uy_revids;
>>> -		size = ARRAY_SIZE(tgl_uy_revids);
>>> +		revid_step_tbl = tgl_uy_revid_step_tbl;
>>> +		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>>>  	} else {
>>> -		tgl_revid_tbl = tgl_revids;
>>> -		size = ARRAY_SIZE(tgl_revids);
>>> +		revid_step_tbl = tgl_revid_step_tbl;
>>> +		size = ARRAY_SIZE(tgl_revid_step_tbl);
>>>  	}
>>>  
>>>  	revid = min_t(u8, revid, size - 1);
>>>  
>>> -	return &tgl_revid_tbl[revid];
>>> +	return &revid_step_tbl[revid];
>>>  }
>>>  
>>> -#define IS_TGL_DISP_REVID(p, since, until) \
>>> +#define IS_TGL_DISP_STEPPING(p, since, until) \
>>>  	(IS_TIGERLAKE(p) && \
>>> -	 tgl_revids_get(p)->disp_stepping >= (since) && \
>>> -	 tgl_revids_get(p)->disp_stepping <= (until))
>>> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
>>> +	 tgl_stepping_get(p)->disp_stepping <= (until))
>>>  
>>> -#define IS_TGL_UY_GT_REVID(p, since, until) \
>>> +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
>>>  	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>  
>>> -#define IS_TGL_GT_REVID(p, since, until) \
>>> +#define IS_TGL_GT_STEPPING(p, since, until) \
>>>  	(IS_TIGERLAKE(p) && \
>>>  	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>  
>>>  #define RKL_REVID_A0		0x0
>>>  #define RKL_REVID_B0		0x1
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index bbc73df7f753..319acca2630b 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>>  
>>>  	/* Wa_1409825376:tgl (pre-prod)*/
>>> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>>> +	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
>>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>>  			   TGL_VRH_GATING_DIS);
>>>  
>>> -- 
>>> 2.27.0
>>>
> 

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 20:18       ` Jani Nikula
@ 2021-01-11 20:57         ` Matt Roper
  2021-01-11 21:25           ` Lucas De Marchi
  2021-01-11 22:58           ` Aditya Swarup
  0 siblings, 2 replies; 24+ messages in thread
From: Matt Roper @ 2021-01-11 20:57 UTC (permalink / raw)
  To: Jani Nikula; +Cc: Lucas De Marchi, intel-gfx

On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
> On Mon, 11 Jan 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> >> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
> >>> TGL adds another level of indirection for applying WA based on stepping
> >>> information rather than PCI REVID. So change TGL_REVID enum into
> >>> stepping enum and use PCI REVID as index into revid to stepping table to
> >>> fetch correct display and GT stepping for application of WAs as
> >>> suggested by Matt Roper.
> >>
> >> So to clarify the goal is to rename "revid" -> "stepping" because the
> >> values like "A1," "C0," etc. are't the actual PCI revision ID, but
> >> rather descriptions of the stepping of a given IP block; the enum values
> >> we use to represent those are arbitrary and don't matter as long as
> >> they're monotonically increasing for comparisons.  The PCI revision ID
> >> is just the input we use today to deduce what the IP steppings are, and
> >> there's talk that we could determine the IP steppings in a different way
> >> at some point in the future.
> >>
> >> Furthermore, since the same scheme will be used at least for ADL-S, we
> >> should drop the "TGL" prefix since there's no need to name these general
> >> enum values in a platform-specific manner.
> >>
> >> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> >>
> >> We should probably make the same kind of change to KBL (and use the same
> >> stepping enum) too since it has the same kind of extra indirection as
> >> TGL/ADL-S, but we can do that as a followup patch.
> >
> > FWIW I have a wip series changing the whole thing to abstract steppings
> > enums that are shared between platforms, but it's in a bit of limbo
> > because the previous revid changes were applied to drm-intel-gt-next,
> > and it's fallen pretty far out of sync with drm-intel-next. All of this
> > really belongs to drm-intel-next, but can't do that until the branches
> > sync up again.
> 
> Btw this series doesn't apply to drm-intel-next either, for the same
> reason, and the ADL-S platform definition and PCI IDs must *not* be
> applied to drm-intel-gt-next.

So to clarify, it looks like we have a bunch of revid changes to the
display code that got merged to the gt-next tree but not to the
intel-next tree?  Should we be going back and also merging /
cherry-picking those over to intel-next since that's where the display
changes are supposed to go, or is it too late to do that cleanly at this
point?

Going forward, what should the general strategy be for stuff like
platform definitions and such?  Merge such enablement patches to both
intel-next and gt-next at the same time so that the basic definitions
are available to both trees?  It seems like the whole split into two
trees really isn't working well and is just leading to more mistakes and
bottlenecks.  What benefit are we supposed to be getting from this
split?


Matt


> 
> BR,
> Jani.
> 
> >
> > My series also completely hides the arrays into a separate .c file,
> > because the externs with direct array access are turning into
> > nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
> > the actual array definition to have the sizes in sync, but the compiler
> > does not check that. Really.
> >
> > IDK, feels like this merging this series is going to be extra churn.
> >
> >
> > BR,
> > Jani.
> >
> >
> >>
> >>
> >> Matt
> >>
> >>> 
> >>> Cc: Matt Roper <matthew.d.roper@intel.com>
> >>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> >>> Cc: José Roberto de Souza <jose.souza@intel.com>
> >>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> >>> ---
> >>>  .../drm/i915/display/intel_display_power.c    |  2 +-
> >>>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
> >>>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
> >>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
> >>>  drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
> >>>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
> >>>  6 files changed, 43 insertions(+), 43 deletions(-)
> >>> 
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> >>> index d52374f01316..bb04b502a442 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> >>> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> >>>  	int config, i;
> >>>  
> >>>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> >>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> >>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
> >>>  		/* Wa_1409767108:tgl,dg1 */
> >>>  		table = wa_1409767108_buddy_page_masks;
> >>>  	else
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> >>> index c24ae69426cf..a93717178957 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >>> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> >>>  
> >>>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
> >>>  		/* WA 1408330847 */
> >>> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> >>> +		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
> >>>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> >>>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> >>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> >>> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> >>>  
> >>>  	/* WA 1408330847 */
> >>>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
> >>> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> >>> +	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
> >>>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> >>>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> >>>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> >>> index cf3589fd0ddb..4ce32df3855f 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> >>> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
> >>>  {
> >>>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> >>>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> >>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> >>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
> >>>  		return false;
> >>>  
> >>>  	return plane_id < PLANE_SPRITE4;
> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>> index c21a9726326a..111d01e2f81e 100644
> >>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >>> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
> >>>  	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
> >>>  };
> >>>  
> >>> -const struct i915_rev_steppings tgl_uy_revids[] = {
> >>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
> >>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
> >>> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
> >>> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
> >>> +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
> >>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
> >>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
> >>> +	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
> >>> +	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
> >>>  };
> >>>  
> >>>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
> >>> -const struct i915_rev_steppings tgl_revids[] = {
> >>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
> >>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
> >>> +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
> >>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
> >>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
> >>>  };
> >>>  
> >>>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
> >>> @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> >>>  	gen12_gt_workarounds_init(i915, wal);
> >>>  
> >>>  	/* Wa_1409420604:tgl */
> >>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> >>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
> >>>  		wa_write_or(wal,
> >>>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
> >>>  			    CPSSUNIT_CLKGATE_DIS);
> >>>  
> >>>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
> >>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> >>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
> >>>  		wa_write_or(wal,
> >>>  			    SLICE_UNIT_LEVEL_CLKGATE,
> >>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> >>>  
> >>>  	/* Wa_1408615072:tgl[a0] */
> >>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> >>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
> >>>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> >>>  			    VSUNIT_CLKGATE_DIS_TGL);
> >>>  }
> >>> @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >>>  	struct drm_i915_private *i915 = engine->i915;
> >>>  
> >>>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> >>> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> >>> +	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
> >>>  		/*
> >>>  		 * Wa_1607138336:tgl[a0],dg1[a0]
> >>>  		 * Wa_1607063988:tgl[a0],dg1[a0]
> >>> @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >>>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> >>>  	}
> >>>  
> >>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> >>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
> >>>  		/*
> >>>  		 * Wa_1606679103:tgl
> >>>  		 * (see also Wa_1606682166:icl)
> >>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >>> index 5e5bcef20e33..11d6e8abde46 100644
> >>> --- a/drivers/gpu/drm/i915/i915_drv.h
> >>> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >>> @@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
> >>>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
> >>>  
> >>>  enum {
> >>> -	TGL_REVID_A0,
> >>> -	TGL_REVID_B0,
> >>> -	TGL_REVID_B1,
> >>> -	TGL_REVID_C0,
> >>> -	TGL_REVID_D0,
> >>> +	STEP_A0,
> >>> +	STEP_B0,
> >>> +	STEP_B1,
> >>> +	STEP_C0,
> >>> +	STEP_D0,
> >>>  };
> >>>  
> >>> -#define TGL_UY_REVIDS_SIZE	4
> >>> -#define TGL_REVIDS_SIZE		2
> >>> +#define TGL_UY_REVID_STEP_TBL_SIZE	4
> >>> +#define TGL_REVID_STEP_TBL_SIZE		2
> >>>  
> >>> -extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
> >>> -extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
> >>> +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
> >>> +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
> >>>  
> >>>  static inline const struct i915_rev_steppings *
> >>> -tgl_revids_get(struct drm_i915_private *dev_priv)
> >>> +tgl_stepping_get(struct drm_i915_private *dev_priv)
> >>>  {
> >>>  	u8 revid = INTEL_REVID(dev_priv);
> >>>  	u8 size;
> >>> -	const struct i915_rev_steppings *tgl_revid_tbl;
> >>> +	const struct i915_rev_steppings *revid_step_tbl;
> >>>  
> >>>  	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> >>> -		tgl_revid_tbl = tgl_uy_revids;
> >>> -		size = ARRAY_SIZE(tgl_uy_revids);
> >>> +		revid_step_tbl = tgl_uy_revid_step_tbl;
> >>> +		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
> >>>  	} else {
> >>> -		tgl_revid_tbl = tgl_revids;
> >>> -		size = ARRAY_SIZE(tgl_revids);
> >>> +		revid_step_tbl = tgl_revid_step_tbl;
> >>> +		size = ARRAY_SIZE(tgl_revid_step_tbl);
> >>>  	}
> >>>  
> >>>  	revid = min_t(u8, revid, size - 1);
> >>>  
> >>> -	return &tgl_revid_tbl[revid];
> >>> +	return &revid_step_tbl[revid];
> >>>  }
> >>>  
> >>> -#define IS_TGL_DISP_REVID(p, since, until) \
> >>> +#define IS_TGL_DISP_STEPPING(p, since, until) \
> >>>  	(IS_TIGERLAKE(p) && \
> >>> -	 tgl_revids_get(p)->disp_stepping >= (since) && \
> >>> -	 tgl_revids_get(p)->disp_stepping <= (until))
> >>> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
> >>> +	 tgl_stepping_get(p)->disp_stepping <= (until))
> >>>  
> >>> -#define IS_TGL_UY_GT_REVID(p, since, until) \
> >>> +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
> >>>  	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
> >>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
> >>> -	 tgl_revids_get(p)->gt_stepping <= (until))
> >>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
> >>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
> >>>  
> >>> -#define IS_TGL_GT_REVID(p, since, until) \
> >>> +#define IS_TGL_GT_STEPPING(p, since, until) \
> >>>  	(IS_TIGERLAKE(p) && \
> >>>  	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
> >>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
> >>> -	 tgl_revids_get(p)->gt_stepping <= (until))
> >>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
> >>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
> >>>  
> >>>  #define RKL_REVID_A0		0x0
> >>>  #define RKL_REVID_B0		0x1
> >>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >>> index bbc73df7f753..319acca2630b 100644
> >>> --- a/drivers/gpu/drm/i915/intel_pm.c
> >>> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >>> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> >>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> >>>  
> >>>  	/* Wa_1409825376:tgl (pre-prod)*/
> >>> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
> >>> +	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
> >>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
> >>>  			   TGL_VRH_GATING_DIS);
> >>>  
> >>> -- 
> >>> 2.27.0
> >>> 
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 20:57         ` Matt Roper
@ 2021-01-11 21:25           ` Lucas De Marchi
  2021-01-12 16:24             ` Jani Nikula
  2021-01-12 17:33             ` Vivi, Rodrigo
  2021-01-11 22:58           ` Aditya Swarup
  1 sibling, 2 replies; 24+ messages in thread
From: Lucas De Marchi @ 2021-01-11 21:25 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Mon, Jan 11, 2021 at 12:57:43PM -0800, Matt Roper wrote:
>On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
>> On Mon, 11 Jan 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>> > On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>> >> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
>> >>> TGL adds another level of indirection for applying WA based on stepping
>> >>> information rather than PCI REVID. So change TGL_REVID enum into
>> >>> stepping enum and use PCI REVID as index into revid to stepping table to
>> >>> fetch correct display and GT stepping for application of WAs as
>> >>> suggested by Matt Roper.
>> >>
>> >> So to clarify the goal is to rename "revid" -> "stepping" because the
>> >> values like "A1," "C0," etc. are't the actual PCI revision ID, but
>> >> rather descriptions of the stepping of a given IP block; the enum values
>> >> we use to represent those are arbitrary and don't matter as long as
>> >> they're monotonically increasing for comparisons.  The PCI revision ID
>> >> is just the input we use today to deduce what the IP steppings are, and
>> >> there's talk that we could determine the IP steppings in a different way
>> >> at some point in the future.
>> >>
>> >> Furthermore, since the same scheme will be used at least for ADL-S, we
>> >> should drop the "TGL" prefix since there's no need to name these general
>> >> enum values in a platform-specific manner.
>> >>
>> >> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>> >>
>> >> We should probably make the same kind of change to KBL (and use the same
>> >> stepping enum) too since it has the same kind of extra indirection as
>> >> TGL/ADL-S, but we can do that as a followup patch.
>> >
>> > FWIW I have a wip series changing the whole thing to abstract steppings
>> > enums that are shared between platforms, but it's in a bit of limbo
>> > because the previous revid changes were applied to drm-intel-gt-next,
>> > and it's fallen pretty far out of sync with drm-intel-next. All of this
>> > really belongs to drm-intel-next, but can't do that until the branches
>> > sync up again.
>>
>> Btw this series doesn't apply to drm-intel-next either, for the same
>> reason, and the ADL-S platform definition and PCI IDs must *not* be
>> applied to drm-intel-gt-next.
>
>So to clarify, it looks like we have a bunch of revid changes to the
>display code that got merged to the gt-next tree but not to the
>intel-next tree?  Should we be going back and also merging /
>cherry-picking those over to intel-next since that's where the display
>changes are supposed to go, or is it too late to do that cleanly at this
>point?

it was my mistake to merge them to drm-intel-gt-next. They should have
been in drm-intel-next.

>
>Going forward, what should the general strategy be for stuff like
>platform definitions and such?  Merge such enablement patches to both

last time we talked about this was regarding dg1 AFAIR and the consensus
was to create a topic branch and that topic branch to be merged in both
branches. That would avoid having 2 commits in different branches.

Not sure if it would work out nicely for getting test on CI though.
Since the changes are spread through the codebase, we could very easily
hit a situation that this topic branch creates conflicts for other
patches getting merged on either drm-intel-next or drm-intel-gt-next.

+Joonas, +Rodrigo

Lucas De Marchi

>intel-next and gt-next at the same time so that the basic definitions
>are available to both trees?  It seems like the whole split into two
>trees really isn't working well and is just leading to more mistakes and
>bottlenecks.  What benefit are we supposed to be getting from this
>split?
>
>
>Matt
>
>
>>
>> BR,
>> Jani.
>>
>> >
>> > My series also completely hides the arrays into a separate .c file,
>> > because the externs with direct array access are turning into
>> > nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
>> > the actual array definition to have the sizes in sync, but the compiler
>> > does not check that. Really.
>> >
>> > IDK, feels like this merging this series is going to be extra churn.
>> >
>> >
>> > BR,
>> > Jani.
>> >
>> >
>> >>
>> >>
>> >> Matt
>> >>
>> >>>
>> >>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> >>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> >>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> >>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> >>> ---
>> >>>  .../drm/i915/display/intel_display_power.c    |  2 +-
>> >>>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
>> >>>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>> >>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
>> >>>  drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
>> >>>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>> >>>  6 files changed, 43 insertions(+), 43 deletions(-)
>> >>>
>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> >>> index d52374f01316..bb04b502a442 100644
>> >>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> >>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> >>> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>> >>>  	int config, i;
>> >>>
>> >>>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>> >>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>> >>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
>> >>>  		/* Wa_1409767108:tgl,dg1 */
>> >>>  		table = wa_1409767108_buddy_page_masks;
>> >>>  	else
>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> >>> index c24ae69426cf..a93717178957 100644
>> >>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> >>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> >>> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>> >>>
>> >>>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
>> >>>  		/* WA 1408330847 */
>> >>> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>> >>> +		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>> >>>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>> >>>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>> >>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>> >>> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>> >>>
>> >>>  	/* WA 1408330847 */
>> >>>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
>> >>> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>> >>> +	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>> >>>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>> >>>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>> >>>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>> index cf3589fd0ddb..4ce32df3855f 100644
>> >>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>> >>>  {
>> >>>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>> >>>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>> >>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
>> >>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
>> >>>  		return false;
>> >>>
>> >>>  	return plane_id < PLANE_SPRITE4;
>> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> >>> index c21a9726326a..111d01e2f81e 100644
>> >>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> >>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> >>> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
>> >>>  	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
>> >>>  };
>> >>>
>> >>> -const struct i915_rev_steppings tgl_uy_revids[] = {
>> >>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
>> >>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
>> >>> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
>> >>> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
>> >>> +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
>> >>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
>> >>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
>> >>> +	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
>> >>> +	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
>> >>>  };
>> >>>
>> >>>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>> >>> -const struct i915_rev_steppings tgl_revids[] = {
>> >>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
>> >>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
>> >>> +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
>> >>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
>> >>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>> >>>  };
>> >>>
>> >>>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>> >>> @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> >>>  	gen12_gt_workarounds_init(i915, wal);
>> >>>
>> >>>  	/* Wa_1409420604:tgl */
>> >>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> >>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>> >>>  		wa_write_or(wal,
>> >>>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>> >>>  			    CPSSUNIT_CLKGATE_DIS);
>> >>>
>> >>>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
>> >>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> >>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>> >>>  		wa_write_or(wal,
>> >>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>> >>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>> >>>
>> >>>  	/* Wa_1408615072:tgl[a0] */
>> >>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> >>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>> >>>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>> >>>  			    VSUNIT_CLKGATE_DIS_TGL);
>> >>>  }
>> >>> @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> >>>  	struct drm_i915_private *i915 = engine->i915;
>> >>>
>> >>>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>> >>> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>> >>> +	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>> >>>  		/*
>> >>>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>> >>>  		 * Wa_1607063988:tgl[a0],dg1[a0]
>> >>> @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> >>>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>> >>>  	}
>> >>>
>> >>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>> >>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>> >>>  		/*
>> >>>  		 * Wa_1606679103:tgl
>> >>>  		 * (see also Wa_1606682166:icl)
>> >>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> >>> index 5e5bcef20e33..11d6e8abde46 100644
>> >>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> >>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> >>> @@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
>> >>>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
>> >>>
>> >>>  enum {
>> >>> -	TGL_REVID_A0,
>> >>> -	TGL_REVID_B0,
>> >>> -	TGL_REVID_B1,
>> >>> -	TGL_REVID_C0,
>> >>> -	TGL_REVID_D0,
>> >>> +	STEP_A0,
>> >>> +	STEP_B0,
>> >>> +	STEP_B1,
>> >>> +	STEP_C0,
>> >>> +	STEP_D0,
>> >>>  };
>> >>>
>> >>> -#define TGL_UY_REVIDS_SIZE	4
>> >>> -#define TGL_REVIDS_SIZE		2
>> >>> +#define TGL_UY_REVID_STEP_TBL_SIZE	4
>> >>> +#define TGL_REVID_STEP_TBL_SIZE		2
>> >>>
>> >>> -extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
>> >>> -extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
>> >>> +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
>> >>> +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
>> >>>
>> >>>  static inline const struct i915_rev_steppings *
>> >>> -tgl_revids_get(struct drm_i915_private *dev_priv)
>> >>> +tgl_stepping_get(struct drm_i915_private *dev_priv)
>> >>>  {
>> >>>  	u8 revid = INTEL_REVID(dev_priv);
>> >>>  	u8 size;
>> >>> -	const struct i915_rev_steppings *tgl_revid_tbl;
>> >>> +	const struct i915_rev_steppings *revid_step_tbl;
>> >>>
>> >>>  	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>> >>> -		tgl_revid_tbl = tgl_uy_revids;
>> >>> -		size = ARRAY_SIZE(tgl_uy_revids);
>> >>> +		revid_step_tbl = tgl_uy_revid_step_tbl;
>> >>> +		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>> >>>  	} else {
>> >>> -		tgl_revid_tbl = tgl_revids;
>> >>> -		size = ARRAY_SIZE(tgl_revids);
>> >>> +		revid_step_tbl = tgl_revid_step_tbl;
>> >>> +		size = ARRAY_SIZE(tgl_revid_step_tbl);
>> >>>  	}
>> >>>
>> >>>  	revid = min_t(u8, revid, size - 1);
>> >>>
>> >>> -	return &tgl_revid_tbl[revid];
>> >>> +	return &revid_step_tbl[revid];
>> >>>  }
>> >>>
>> >>> -#define IS_TGL_DISP_REVID(p, since, until) \
>> >>> +#define IS_TGL_DISP_STEPPING(p, since, until) \
>> >>>  	(IS_TIGERLAKE(p) && \
>> >>> -	 tgl_revids_get(p)->disp_stepping >= (since) && \
>> >>> -	 tgl_revids_get(p)->disp_stepping <= (until))
>> >>> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
>> >>> +	 tgl_stepping_get(p)->disp_stepping <= (until))
>> >>>
>> >>> -#define IS_TGL_UY_GT_REVID(p, since, until) \
>> >>> +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
>> >>>  	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>> >>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>> >>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>> >>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>> >>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>> >>>
>> >>> -#define IS_TGL_GT_REVID(p, since, until) \
>> >>> +#define IS_TGL_GT_STEPPING(p, since, until) \
>> >>>  	(IS_TIGERLAKE(p) && \
>> >>>  	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>> >>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>> >>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>> >>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>> >>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>> >>>
>> >>>  #define RKL_REVID_A0		0x0
>> >>>  #define RKL_REVID_B0		0x1
>> >>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> >>> index bbc73df7f753..319acca2630b 100644
>> >>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> >>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> >>> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>> >>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>> >>>
>> >>>  	/* Wa_1409825376:tgl (pre-prod)*/
>> >>> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>> >>> +	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
>> >>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>> >>>  			   TGL_VRH_GATING_DIS);
>> >>>
>> >>> --
>> >>> 2.27.0
>> >>>
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 20:57         ` Matt Roper
  2021-01-11 21:25           ` Lucas De Marchi
@ 2021-01-11 22:58           ` Aditya Swarup
  2021-01-12 16:32             ` Jani Nikula
  1 sibling, 1 reply; 24+ messages in thread
From: Aditya Swarup @ 2021-01-11 22:58 UTC (permalink / raw)
  To: Matt Roper, Jani Nikula; +Cc: intel-gfx, Lucas De Marchi

On 1/11/21 12:57 PM, Matt Roper wrote:
> On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
>> On Mon, 11 Jan 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>> On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>>>> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
>>>>> TGL adds another level of indirection for applying WA based on stepping
>>>>> information rather than PCI REVID. So change TGL_REVID enum into
>>>>> stepping enum and use PCI REVID as index into revid to stepping table to
>>>>> fetch correct display and GT stepping for application of WAs as
>>>>> suggested by Matt Roper.
>>>>
>>>> So to clarify the goal is to rename "revid" -> "stepping" because the
>>>> values like "A1," "C0," etc. are't the actual PCI revision ID, but
>>>> rather descriptions of the stepping of a given IP block; the enum values
>>>> we use to represent those are arbitrary and don't matter as long as
>>>> they're monotonically increasing for comparisons.  The PCI revision ID
>>>> is just the input we use today to deduce what the IP steppings are, and
>>>> there's talk that we could determine the IP steppings in a different way
>>>> at some point in the future.
>>>>
>>>> Furthermore, since the same scheme will be used at least for ADL-S, we
>>>> should drop the "TGL" prefix since there's no need to name these general
>>>> enum values in a platform-specific manner.
>>>>
>>>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>>>
>>>> We should probably make the same kind of change to KBL (and use the same
>>>> stepping enum) too since it has the same kind of extra indirection as
>>>> TGL/ADL-S, but we can do that as a followup patch.
>>>
>>> FWIW I have a wip series changing the whole thing to abstract steppings
>>> enums that are shared between platforms, but it's in a bit of limbo
>>> because the previous revid changes were applied to drm-intel-gt-next,
>>> and it's fallen pretty far out of sync with drm-intel-next. All of this
>>> really belongs to drm-intel-next, but can't do that until the branches
>>> sync up again.
>>
>> Btw this series doesn't apply to drm-intel-next either, for the same
>> reason, and the ADL-S platform definition and PCI IDs must *not* be
>> applied to drm-intel-gt-next.

The reason behind this patch not cleanly applying on drm-intel-next is because
drm/i915/tgl: Add bound checks and simplify TGL REVID macros
isn't present on that branch but present on gt-next. 

The patch doesn't apply on gt-next because of a conflict in the following hunk:
        /* Wa_1409825376:tgl (pre-prod)*/
-       if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
+       if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))

which can be easily fixed during backmerge process as I was able apply the patch
cleanly on gt-next. 
I don't understand the "must *not*" reasoning behind not applying this patch on gt-next.

It was common consesus during initial review that separating stepping/revid parsing in a 
separate .c file will be pushed in after ADLS changes and adding this patch won't add any extra
churn, just a minor rebase for your approach.

Regards,
aswarup

> 
> So to clarify, it looks like we have a bunch of revid changes to the
> display code that got merged to the gt-next tree but not to the
> intel-next tree?  Should we be going back and also merging /
> cherry-picking those over to intel-next since that's where the display
> changes are supposed to go, or is it too late to do that cleanly at this
> point?
> 
> Going forward, what should the general strategy be for stuff like
> platform definitions and such?  Merge such enablement patches to both
> intel-next and gt-next at the same time so that the basic definitions
> are available to both trees?  It seems like the whole split into two
> trees really isn't working well and is just leading to more mistakes and
> bottlenecks.  What benefit are we supposed to be getting from this
> split?> 
> 
> Matt
> 
> 
>>
>> BR,
>> Jani.
>>
>>>
>>> My series also completely hides the arrays into a separate .c file,
>>> because the externs with direct array access are turning into
>>> nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
>>> the actual array definition to have the sizes in sync, but the compiler
>>> does not check that. Really.
>>>
>>> IDK, feels like this merging this series is going to be extra churn.
>>>
>>>
>>> BR,
>>> Jani.
>>>
>>>
>>>>
>>>>
>>>> Matt
>>>>
>>>>>
>>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>>>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>>>>> ---
>>>>>  .../drm/i915/display/intel_display_power.c    |  2 +-
>>>>>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
>>>>>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>>>>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
>>>>>  drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
>>>>>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>>>>>  6 files changed, 43 insertions(+), 43 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>>>> index d52374f01316..bb04b502a442 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>>>> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>>>>>  	int config, i;
>>>>>  
>>>>>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>>>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>>>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
>>>>>  		/* Wa_1409767108:tgl,dg1 */
>>>>>  		table = wa_1409767108_buddy_page_masks;
>>>>>  	else
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> index c24ae69426cf..a93717178957 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>>>>  
>>>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
>>>>>  		/* WA 1408330847 */
>>>>> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>>>> +		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>>>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>>>>>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>>>>> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>>>>  
>>>>>  	/* WA 1408330847 */
>>>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
>>>>> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>>>> +	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>>>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>>>>>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>>>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>>>>> index cf3589fd0ddb..4ce32df3855f 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>>>> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>>>>>  {
>>>>>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>>>>>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>>>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
>>>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
>>>>>  		return false;
>>>>>  
>>>>>  	return plane_id < PLANE_SPRITE4;
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> index c21a9726326a..111d01e2f81e 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
>>>>>  	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
>>>>>  };
>>>>>  
>>>>> -const struct i915_rev_steppings tgl_uy_revids[] = {
>>>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
>>>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
>>>>> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
>>>>> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
>>>>> +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
>>>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
>>>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
>>>>> +	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
>>>>> +	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
>>>>>  };
>>>>>  
>>>>>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>>>>> -const struct i915_rev_steppings tgl_revids[] = {
>>>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
>>>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
>>>>> +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
>>>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
>>>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>>>>>  };
>>>>>  
>>>>>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>>>>> @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>>>>  	gen12_gt_workarounds_init(i915, wal);
>>>>>  
>>>>>  	/* Wa_1409420604:tgl */
>>>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>>>  		wa_write_or(wal,
>>>>>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>>>>>  			    CPSSUNIT_CLKGATE_DIS);
>>>>>  
>>>>>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
>>>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>>>  		wa_write_or(wal,
>>>>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>>>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>>>>>  
>>>>>  	/* Wa_1408615072:tgl[a0] */
>>>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>>>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>>>>>  			    VSUNIT_CLKGATE_DIS_TGL);
>>>>>  }
>>>>> @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>>>  	struct drm_i915_private *i915 = engine->i915;
>>>>>  
>>>>>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>>>>> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>>>> +	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>>>  		/*
>>>>>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>>>>>  		 * Wa_1607063988:tgl[a0],dg1[a0]
>>>>> @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>>>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>>>>>  	}
>>>>>  
>>>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>>>  		/*
>>>>>  		 * Wa_1606679103:tgl
>>>>>  		 * (see also Wa_1606682166:icl)
>>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>>> index 5e5bcef20e33..11d6e8abde46 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>>> @@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
>>>>>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
>>>>>  
>>>>>  enum {
>>>>> -	TGL_REVID_A0,
>>>>> -	TGL_REVID_B0,
>>>>> -	TGL_REVID_B1,
>>>>> -	TGL_REVID_C0,
>>>>> -	TGL_REVID_D0,
>>>>> +	STEP_A0,
>>>>> +	STEP_B0,
>>>>> +	STEP_B1,
>>>>> +	STEP_C0,
>>>>> +	STEP_D0,
>>>>>  };
>>>>>  
>>>>> -#define TGL_UY_REVIDS_SIZE	4
>>>>> -#define TGL_REVIDS_SIZE		2
>>>>> +#define TGL_UY_REVID_STEP_TBL_SIZE	4
>>>>> +#define TGL_REVID_STEP_TBL_SIZE		2
>>>>>  
>>>>> -extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
>>>>> -extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
>>>>> +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
>>>>> +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
>>>>>  
>>>>>  static inline const struct i915_rev_steppings *
>>>>> -tgl_revids_get(struct drm_i915_private *dev_priv)
>>>>> +tgl_stepping_get(struct drm_i915_private *dev_priv)
>>>>>  {
>>>>>  	u8 revid = INTEL_REVID(dev_priv);
>>>>>  	u8 size;
>>>>> -	const struct i915_rev_steppings *tgl_revid_tbl;
>>>>> +	const struct i915_rev_steppings *revid_step_tbl;
>>>>>  
>>>>>  	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>>>>> -		tgl_revid_tbl = tgl_uy_revids;
>>>>> -		size = ARRAY_SIZE(tgl_uy_revids);
>>>>> +		revid_step_tbl = tgl_uy_revid_step_tbl;
>>>>> +		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>>>>>  	} else {
>>>>> -		tgl_revid_tbl = tgl_revids;
>>>>> -		size = ARRAY_SIZE(tgl_revids);
>>>>> +		revid_step_tbl = tgl_revid_step_tbl;
>>>>> +		size = ARRAY_SIZE(tgl_revid_step_tbl);
>>>>>  	}
>>>>>  
>>>>>  	revid = min_t(u8, revid, size - 1);
>>>>>  
>>>>> -	return &tgl_revid_tbl[revid];
>>>>> +	return &revid_step_tbl[revid];
>>>>>  }
>>>>>  
>>>>> -#define IS_TGL_DISP_REVID(p, since, until) \
>>>>> +#define IS_TGL_DISP_STEPPING(p, since, until) \
>>>>>  	(IS_TIGERLAKE(p) && \
>>>>> -	 tgl_revids_get(p)->disp_stepping >= (since) && \
>>>>> -	 tgl_revids_get(p)->disp_stepping <= (until))
>>>>> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
>>>>> +	 tgl_stepping_get(p)->disp_stepping <= (until))
>>>>>  
>>>>> -#define IS_TGL_UY_GT_REVID(p, since, until) \
>>>>> +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
>>>>>  	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>>>  
>>>>> -#define IS_TGL_GT_REVID(p, since, until) \
>>>>> +#define IS_TGL_GT_STEPPING(p, since, until) \
>>>>>  	(IS_TIGERLAKE(p) && \
>>>>>  	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>>>  
>>>>>  #define RKL_REVID_A0		0x0
>>>>>  #define RKL_REVID_B0		0x1
>>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>>> index bbc73df7f753..319acca2630b 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>>> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>>>>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>>>>  
>>>>>  	/* Wa_1409825376:tgl (pre-prod)*/
>>>>> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>>>>> +	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
>>>>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>>>>  			   TGL_VRH_GATING_DIS);
>>>>>  
>>>>> -- 
>>>>> 2.27.0
>>>>>
>>
>> -- 
>> Jani Nikula, Intel Open Source Graphics Center
> 

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^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 20:13     ` Jani Nikula
  2021-01-11 20:18       ` Jani Nikula
  2021-01-11 20:20       ` Aditya Swarup
@ 2021-01-12  2:04       ` Lucas De Marchi
  2021-01-12 16:18         ` Jani Nikula
  2 siblings, 1 reply; 24+ messages in thread
From: Lucas De Marchi @ 2021-01-12  2:04 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Mon, Jan 11, 2021 at 10:13:15PM +0200, Jani Nikula wrote:
>On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
>>> TGL adds another level of indirection for applying WA based on stepping
>>> information rather than PCI REVID. So change TGL_REVID enum into
>>> stepping enum and use PCI REVID as index into revid to stepping table to
>>> fetch correct display and GT stepping for application of WAs as
>>> suggested by Matt Roper.
>>
>> So to clarify the goal is to rename "revid" -> "stepping" because the
>> values like "A1," "C0," etc. are't the actual PCI revision ID, but
>> rather descriptions of the stepping of a given IP block; the enum values
>> we use to represent those are arbitrary and don't matter as long as
>> they're monotonically increasing for comparisons.  The PCI revision ID
>> is just the input we use today to deduce what the IP steppings are, and
>> there's talk that we could determine the IP steppings in a different way
>> at some point in the future.
>>
>> Furthermore, since the same scheme will be used at least for ADL-S, we
>> should drop the "TGL" prefix since there's no need to name these general
>> enum values in a platform-specific manner.
>>
>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>
>> We should probably make the same kind of change to KBL (and use the same
>> stepping enum) too since it has the same kind of extra indirection as
>> TGL/ADL-S, but we can do that as a followup patch.
>
>FWIW I have a wip series changing the whole thing to abstract steppings
>enums that are shared between platforms, but it's in a bit of limbo
>because the previous revid changes were applied to drm-intel-gt-next,
>and it's fallen pretty far out of sync with drm-intel-next. All of this
>really belongs to drm-intel-next, but can't do that until the branches
>sync up again.

in the end both sides will need that (even if it was a mistake to merge
it in drm-intel-gt-next).  I got an ack from Rodrigo to actually
cherry-pick the single patch we are missing so this can unblock both
merging this patch (after rebasing) and you can continue your series.

>
>My series also completely hides the arrays into a separate .c file,
>because the externs with direct array access are turning into
>nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
>the actual array definition to have the sizes in sync, but the compiler
>does not check that. Really.

not following what the ARRAY_SIZE is not checking. It actually is, since
the declaration is explicitly telling the size of the array. If the
definition had more items, you'd get a compilation error.

>
>IDK, feels like this merging this series is going to be extra churn.

I'm not against the refactor you're talking about, but this seems an
improvement to unblock the ADL-S patches that are pending. The patches
could also be split to remove this dependency, but I'm not sure it's
worth it.

Lucas De Marchi

>
>
>BR,
>Jani.
>
>
>>
>>
>> Matt
>>
>>>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>>> ---
>>>  .../drm/i915/display/intel_display_power.c    |  2 +-
>>>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
>>>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
>>>  drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
>>>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>>>  6 files changed, 43 insertions(+), 43 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> index d52374f01316..bb04b502a442 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>>>  	int config, i;
>>>
>>>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
>>>  		/* Wa_1409767108:tgl,dg1 */
>>>  		table = wa_1409767108_buddy_page_masks;
>>>  	else
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index c24ae69426cf..a93717178957 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>>
>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
>>>  		/* WA 1408330847 */
>>> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>> +		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>>>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>>> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>>
>>>  	/* WA 1408330847 */
>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
>>> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>> +	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>>>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> index cf3589fd0ddb..4ce32df3855f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>>>  {
>>>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>>>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
>>>  		return false;
>>>
>>>  	return plane_id < PLANE_SPRITE4;
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index c21a9726326a..111d01e2f81e 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
>>>  	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
>>>  };
>>>
>>> -const struct i915_rev_steppings tgl_uy_revids[] = {
>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
>>> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
>>> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
>>> +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
>>> +	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
>>> +	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
>>>  };
>>>
>>>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>>> -const struct i915_rev_steppings tgl_revids[] = {
>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
>>> +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>>>  };
>>>
>>>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>>> @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>>  	gen12_gt_workarounds_init(i915, wal);
>>>
>>>  	/* Wa_1409420604:tgl */
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>  		wa_write_or(wal,
>>>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>>>  			    CPSSUNIT_CLKGATE_DIS);
>>>
>>>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>  		wa_write_or(wal,
>>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>>>
>>>  	/* Wa_1408615072:tgl[a0] */
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>>>  			    VSUNIT_CLKGATE_DIS_TGL);
>>>  }
>>> @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>  	struct drm_i915_private *i915 = engine->i915;
>>>
>>>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>>> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>> +	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>  		/*
>>>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>>>  		 * Wa_1607063988:tgl[a0],dg1[a0]
>>> @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>>>  	}
>>>
>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>  		/*
>>>  		 * Wa_1606679103:tgl
>>>  		 * (see also Wa_1606682166:icl)
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 5e5bcef20e33..11d6e8abde46 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
>>>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
>>>
>>>  enum {
>>> -	TGL_REVID_A0,
>>> -	TGL_REVID_B0,
>>> -	TGL_REVID_B1,
>>> -	TGL_REVID_C0,
>>> -	TGL_REVID_D0,
>>> +	STEP_A0,
>>> +	STEP_B0,
>>> +	STEP_B1,
>>> +	STEP_C0,
>>> +	STEP_D0,
>>>  };
>>>
>>> -#define TGL_UY_REVIDS_SIZE	4
>>> -#define TGL_REVIDS_SIZE		2
>>> +#define TGL_UY_REVID_STEP_TBL_SIZE	4
>>> +#define TGL_REVID_STEP_TBL_SIZE		2
>>>
>>> -extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
>>> -extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
>>> +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
>>> +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
>>>
>>>  static inline const struct i915_rev_steppings *
>>> -tgl_revids_get(struct drm_i915_private *dev_priv)
>>> +tgl_stepping_get(struct drm_i915_private *dev_priv)
>>>  {
>>>  	u8 revid = INTEL_REVID(dev_priv);
>>>  	u8 size;
>>> -	const struct i915_rev_steppings *tgl_revid_tbl;
>>> +	const struct i915_rev_steppings *revid_step_tbl;
>>>
>>>  	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>>> -		tgl_revid_tbl = tgl_uy_revids;
>>> -		size = ARRAY_SIZE(tgl_uy_revids);
>>> +		revid_step_tbl = tgl_uy_revid_step_tbl;
>>> +		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>>>  	} else {
>>> -		tgl_revid_tbl = tgl_revids;
>>> -		size = ARRAY_SIZE(tgl_revids);
>>> +		revid_step_tbl = tgl_revid_step_tbl;
>>> +		size = ARRAY_SIZE(tgl_revid_step_tbl);
>>>  	}
>>>
>>>  	revid = min_t(u8, revid, size - 1);
>>>
>>> -	return &tgl_revid_tbl[revid];
>>> +	return &revid_step_tbl[revid];
>>>  }
>>>
>>> -#define IS_TGL_DISP_REVID(p, since, until) \
>>> +#define IS_TGL_DISP_STEPPING(p, since, until) \
>>>  	(IS_TIGERLAKE(p) && \
>>> -	 tgl_revids_get(p)->disp_stepping >= (since) && \
>>> -	 tgl_revids_get(p)->disp_stepping <= (until))
>>> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
>>> +	 tgl_stepping_get(p)->disp_stepping <= (until))
>>>
>>> -#define IS_TGL_UY_GT_REVID(p, since, until) \
>>> +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
>>>  	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>
>>> -#define IS_TGL_GT_REVID(p, since, until) \
>>> +#define IS_TGL_GT_STEPPING(p, since, until) \
>>>  	(IS_TIGERLAKE(p) && \
>>>  	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>
>>>  #define RKL_REVID_A0		0x0
>>>  #define RKL_REVID_B0		0x1
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index bbc73df7f753..319acca2630b 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>>
>>>  	/* Wa_1409825376:tgl (pre-prod)*/
>>> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>>> +	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
>>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>>  			   TGL_VRH_GATING_DIS);
>>>
>>> --
>>> 2.27.0
>>>
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 20:20       ` Aditya Swarup
@ 2021-01-12 16:11         ` Jani Nikula
  0 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2021-01-12 16:11 UTC (permalink / raw)
  To: Aditya Swarup, Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On Mon, 11 Jan 2021, Aditya Swarup <aditya.swarup@intel.com> wrote:
> On 1/11/21 12:13 PM, Jani Nikula wrote:
>> On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>> FWIW I have a wip series changing the whole thing to abstract steppings
>> enums that are shared between platforms, but it's in a bit of limbo
>> because the previous revid changes were applied to drm-intel-gt-next,
>> and it's fallen pretty far out of sync with drm-intel-next. All of this
>> really belongs to drm-intel-next, but can't do that until the branches
>> sync up again.
>> 
>> My series also completely hides the arrays into a separate .c file,
>> because the externs with direct array access are turning into
>> nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
>> the actual array definition to have the sizes in sync, but the compiler
>> does not check that. Really.
>> 
>> IDK, feels like this merging this series is going to be extra churn.
>
> We need ADLS support on drm-tip by WW05 and I don't think this should change anything
> as far as rebase is concerned as it will be just deletion of this entire section to move 
> into the separate stepping/revid file in your implementation. 

Fine, let's take the churn, no big deal.

However, I think you'll find drm-intel-next and drm-intel-gt-next are
currently too far from each other to even have a sensible topic branch
baseline:

$ git merge-base drm-intel/drm-intel-next drm-intel/drm-intel-gt-next
31b05212360cbf3af3c2e1b7f42e176e0eebedb5

Even if you do the minimal cherry-pick to drm-intel-next to be able to
apply this series, you'll still end up with really bad merge trouble to
get the platform support back to drm-intel-gt-next, and I presume that's
what you'll need.

And that means a topic branch.

And that means:

1) New drm-intel-gt-next pull request

2) Have that merged to drm-next

3) Have drm-next backmerged to drm-intel-next

to have a sensible baseline.

> I think as a stop gap and to achieve the goal of ADLS patches being pushed in, these patches
> look good enough. If extern/array declaration was a concern, why were the KBL/TGL pathces accepted
> in the first place?

Really, they should not have been. It's just poor design, and difficult
to maintain long term. Data is not an interface. The driver is too big
to bypass abstractions for this.

See this:

$ git grep -w extern -- drivers/gpu/drm/i915

> I will be happy to help with the rebase but the process of pushing
> ADLS patches is stuck because of this.

It's stuck because our -next branches are too far apart.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-12  2:04       ` Lucas De Marchi
@ 2021-01-12 16:18         ` Jani Nikula
  0 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2021-01-12 16:18 UTC (permalink / raw)
  To: Lucas De Marchi; +Cc: intel-gfx

On Mon, 11 Jan 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Mon, Jan 11, 2021 at 10:13:15PM +0200, Jani Nikula wrote:
>>On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> in the end both sides will need that (even if it was a mistake to merge
> it in drm-intel-gt-next).  I got an ack from Rodrigo to actually
> cherry-pick the single patch we are missing so this can unblock both
> merging this patch (after rebasing) and you can continue your series.

cherry-picking the one patch is not enough. The -next branches are too
far apart to start applying ADL-S patches in either branch. Doing so
will lead to way too bad merge conflicts.

Which just means the cherry-pick won't help, as you'll need a topic
branch with a sensible baseline to merge the ADL-S support to both
branches. Now the merge-base is too far away.

>>My series also completely hides the arrays into a separate .c file,
>>because the externs with direct array access are turning into
>>nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
>>the actual array definition to have the sizes in sync, but the compiler
>>does not check that. Really.
>
> not following what the ARRAY_SIZE is not checking. It actually is, since
> the declaration is explicitly telling the size of the array. If the
> definition had more items, you'd get a compilation error.

Mmmh, I tested this, but can't reproduce now. Never mind. *shrug*.

>>IDK, feels like this merging this series is going to be extra churn.
>
> I'm not against the refactor you're talking about, but this seems an
> improvement to unblock the ADL-S patches that are pending. The patches
> could also be split to remove this dependency, but I'm not sure it's
> worth it.

Please let's first get the branches back in sync, and then create a
topic branch for ADL-S, and merge it to both. Everything else will lead
to tears.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 21:25           ` Lucas De Marchi
@ 2021-01-12 16:24             ` Jani Nikula
  2021-01-12 17:16               ` Matt Roper
  2021-01-12 17:33             ` Vivi, Rodrigo
  1 sibling, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-01-12 16:24 UTC (permalink / raw)
  To: Lucas De Marchi, Matt Roper; +Cc: intel-gfx

On Mon, 11 Jan 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Mon, Jan 11, 2021 at 12:57:43PM -0800, Matt Roper wrote:
>>On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
>>So to clarify, it looks like we have a bunch of revid changes to the
>>display code that got merged to the gt-next tree but not to the
>>intel-next tree?  Should we be going back and also merging /
>>cherry-picking those over to intel-next since that's where the display
>>changes are supposed to go, or is it too late to do that cleanly at this
>>point?
>
> it was my mistake to merge them to drm-intel-gt-next. They should have
> been in drm-intel-next.

That's not the problem though. The branches generally being too far
apart atm is. The single cherry-pick won't solve that. Applying these
patches to one tree just adds a dependency that will not be around in
the topic branch baseline, creating a new problem for merging the topic
branch.

>>Going forward, what should the general strategy be for stuff like
>>platform definitions and such?  Merge such enablement patches to both
>
> last time we talked about this was regarding dg1 AFAIR and the consensus
> was to create a topic branch and that topic branch to be merged in both
> branches. That would avoid having 2 commits in different branches.

Agreed.

> Not sure if it would work out nicely for getting test on CI though.
> Since the changes are spread through the codebase, we could very easily
> hit a situation that this topic branch creates conflicts for other
> patches getting merged on either drm-intel-next or drm-intel-gt-next.

The cycle in review -> apply to topic branch -> merge topic branch just
needs to be short enough. We can't have the topic branch laying around
for more than maybe a few days, or we'll have problems.


BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 22:58           ` Aditya Swarup
@ 2021-01-12 16:32             ` Jani Nikula
  0 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2021-01-12 16:32 UTC (permalink / raw)
  To: Aditya Swarup, Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On Mon, 11 Jan 2021, Aditya Swarup <aditya.swarup@intel.com> wrote:
> On 1/11/21 12:57 PM, Matt Roper wrote:
>> On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
>>> On Mon, 11 Jan 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>> On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>>>>> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
>>>>>> TGL adds another level of indirection for applying WA based on stepping
>>>>>> information rather than PCI REVID. So change TGL_REVID enum into
>>>>>> stepping enum and use PCI REVID as index into revid to stepping table to
>>>>>> fetch correct display and GT stepping for application of WAs as
>>>>>> suggested by Matt Roper.
>>>>>
>>>>> So to clarify the goal is to rename "revid" -> "stepping" because the
>>>>> values like "A1," "C0," etc. are't the actual PCI revision ID, but
>>>>> rather descriptions of the stepping of a given IP block; the enum values
>>>>> we use to represent those are arbitrary and don't matter as long as
>>>>> they're monotonically increasing for comparisons.  The PCI revision ID
>>>>> is just the input we use today to deduce what the IP steppings are, and
>>>>> there's talk that we could determine the IP steppings in a different way
>>>>> at some point in the future.
>>>>>
>>>>> Furthermore, since the same scheme will be used at least for ADL-S, we
>>>>> should drop the "TGL" prefix since there's no need to name these general
>>>>> enum values in a platform-specific manner.
>>>>>
>>>>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>>>>
>>>>> We should probably make the same kind of change to KBL (and use the same
>>>>> stepping enum) too since it has the same kind of extra indirection as
>>>>> TGL/ADL-S, but we can do that as a followup patch.
>>>>
>>>> FWIW I have a wip series changing the whole thing to abstract steppings
>>>> enums that are shared between platforms, but it's in a bit of limbo
>>>> because the previous revid changes were applied to drm-intel-gt-next,
>>>> and it's fallen pretty far out of sync with drm-intel-next. All of this
>>>> really belongs to drm-intel-next, but can't do that until the branches
>>>> sync up again.
>>>
>>> Btw this series doesn't apply to drm-intel-next either, for the same
>>> reason, and the ADL-S platform definition and PCI IDs must *not* be
>>> applied to drm-intel-gt-next.
>
> The reason behind this patch not cleanly applying on drm-intel-next is because
> drm/i915/tgl: Add bound checks and simplify TGL REVID macros
> isn't present on that branch but present on gt-next. 
>
> The patch doesn't apply on gt-next because of a conflict in the following hunk:
>         /* Wa_1409825376:tgl (pre-prod)*/
> -       if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
> +       if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
>
> which can be easily fixed during backmerge process as I was able apply the patch
> cleanly on gt-next. 
> I don't understand the "must *not*" reasoning behind not applying this patch on gt-next.

I think I've explained this in several replies in this thread now.

> It was common consesus during initial review that separating
> stepping/revid parsing in a separate .c file will be pushed in after
> ADLS changes and adding this patch won't add any extra churn, just a
> minor rebase for your approach.

Misunderstanding I guess. I thought the required changes had already
been pushed, and we weren't waiting for further changes on this.

I certainly wasn't expecting the generic revid -> stepping rename at
this point, as I don't think they are required for ADL-S at all. I
thought the consensus was that I'll do the refactoring.

Anyway, I can deal with the churn and the rebases, no problem.


BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-12 16:24             ` Jani Nikula
@ 2021-01-12 17:16               ` Matt Roper
  0 siblings, 0 replies; 24+ messages in thread
From: Matt Roper @ 2021-01-12 17:16 UTC (permalink / raw)
  To: Jani Nikula; +Cc: Lucas De Marchi, intel-gfx

On Tue, Jan 12, 2021 at 06:24:50PM +0200, Jani Nikula wrote:
> On Mon, 11 Jan 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> > On Mon, Jan 11, 2021 at 12:57:43PM -0800, Matt Roper wrote:
> >>On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
> >>So to clarify, it looks like we have a bunch of revid changes to the
> >>display code that got merged to the gt-next tree but not to the
> >>intel-next tree?  Should we be going back and also merging /
> >>cherry-picking those over to intel-next since that's where the display
> >>changes are supposed to go, or is it too late to do that cleanly at this
> >>point?
> >
> > it was my mistake to merge them to drm-intel-gt-next. They should have
> > been in drm-intel-next.
> 
> That's not the problem though. The branches generally being too far
> apart atm is. The single cherry-pick won't solve that. Applying these
> patches to one tree just adds a dependency that will not be around in
> the topic branch baseline, creating a new problem for merging the topic
> branch.

I still don't understand what the original goal of splitting the driver
into two different trees was.  It's clear that this approach is going to
cause extra mistakes and bugs if we continue down this path and it's not
clear to me what the expected benefit was to justify the additional
complexity?

When are the two branches supposed to be brought back in sync?  Is it
just a single backmerge to each branch immediately after new mainline
kernel releases or is there some other strategy to handle this?


Matt

> 
> >>Going forward, what should the general strategy be for stuff like
> >>platform definitions and such?  Merge such enablement patches to both
> >
> > last time we talked about this was regarding dg1 AFAIR and the consensus
> > was to create a topic branch and that topic branch to be merged in both
> > branches. That would avoid having 2 commits in different branches.
> 
> Agreed.
> 
> > Not sure if it would work out nicely for getting test on CI though.
> > Since the changes are spread through the codebase, we could very easily
> > hit a situation that this topic branch creates conflicts for other
> > patches getting merged on either drm-intel-next or drm-intel-gt-next.
> 
> The cycle in review -> apply to topic branch -> merge topic branch just
> needs to be short enough. We can't have the topic branch laying around
> for more than maybe a few days, or we'll have problems.
> 
> 
> BR,
> Jani.
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 21:25           ` Lucas De Marchi
  2021-01-12 16:24             ` Jani Nikula
@ 2021-01-12 17:33             ` Vivi, Rodrigo
  2021-01-12 17:39               ` Jani Nikula
  1 sibling, 1 reply; 24+ messages in thread
From: Vivi, Rodrigo @ 2021-01-12 17:33 UTC (permalink / raw)
  To: Roper, Matthew D, De Marchi, Lucas; +Cc: intel-gfx

On Mon, 2021-01-11 at 13:25 -0800, Lucas De Marchi wrote:
> On Mon, Jan 11, 2021 at 12:57:43PM -0800, Matt Roper wrote:
> > On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
> > > On Mon, 11 Jan 2021, Jani Nikula <jani.nikula@linux.intel.com>
> > > wrote:
> > > > On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com>
> > > > wrote:
> > > > > On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup
> > > > > wrote:
> > > > > > TGL adds another level of indirection for applying WA based
> > > > > > on stepping
> > > > > > information rather than PCI REVID. So change TGL_REVID enum
> > > > > > into
> > > > > > stepping enum and use PCI REVID as index into revid to
> > > > > > stepping table to
> > > > > > fetch correct display and GT stepping for application of
> > > > > > WAs as
> > > > > > suggested by Matt Roper.
> > > > > 
> > > > > So to clarify the goal is to rename "revid" -> "stepping"
> > > > > because the
> > > > > values like "A1," "C0," etc. are't the actual PCI revision
> > > > > ID, but
> > > > > rather descriptions of the stepping of a given IP block; the
> > > > > enum values
> > > > > we use to represent those are arbitrary and don't matter as
> > > > > long as
> > > > > they're monotonically increasing for comparisons.  The PCI
> > > > > revision ID
> > > > > is just the input we use today to deduce what the IP
> > > > > steppings are, and
> > > > > there's talk that we could determine the IP steppings in a
> > > > > different way
> > > > > at some point in the future.
> > > > > 
> > > > > Furthermore, since the same scheme will be used at least for
> > > > > ADL-S, we
> > > > > should drop the "TGL" prefix since there's no need to name
> > > > > these general
> > > > > enum values in a platform-specific manner.
> > > > > 
> > > > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > 
> > > > > We should probably make the same kind of change to KBL (and
> > > > > use the same
> > > > > stepping enum) too since it has the same kind of extra
> > > > > indirection as
> > > > > TGL/ADL-S, but we can do that as a followup patch.
> > > > 
> > > > FWIW I have a wip series changing the whole thing to abstract
> > > > steppings
> > > > enums that are shared between platforms, but it's in a bit of
> > > > limbo
> > > > because the previous revid changes were applied to drm-intel-
> > > > gt-next,
> > > > and it's fallen pretty far out of sync with drm-intel-next. All
> > > > of this
> > > > really belongs to drm-intel-next, but can't do that until the
> > > > branches
> > > > sync up again.
> > > 
> > > Btw this series doesn't apply to drm-intel-next either, for the
> > > same
> > > reason, and the ADL-S platform definition and PCI IDs must *not*
> > > be
> > > applied to drm-intel-gt-next.
> > 
> > So to clarify, it looks like we have a bunch of revid changes to
> > the
> > display code that got merged to the gt-next tree but not to the
> > intel-next tree?  Should we be going back and also merging /
> > cherry-picking those over to intel-next since that's where the
> > display
> > changes are supposed to go, or is it too late to do that cleanly at
> > this
> > point?
> 
> it was my mistake to merge them to drm-intel-gt-next. They should
> have
> been in drm-intel-next.
> 
> > 
> > Going forward, what should the general strategy be for stuff like
> > platform definitions and such?  Merge such enablement patches to
> > both
> 
> last time we talked about this was regarding dg1 AFAIR and the
> consensus
> was to create a topic branch and that topic branch to be merged in
> both
> branches. That would avoid having 2 commits in different branches.

Yeap, I believe this is the way to go.

> 
> Not sure if it would work out nicely for getting test on CI though.

create an empty topic branch using dim.

Pre-merge CI with drm-tip. Only if passing and if everything is realy
ready. Push to the topic branch using dim.

Then it will be part of drm-tip already for any subsequential pre-merge
CI...

Then do the pull requests to bot drm-intel-next and drm-intel-gt-next.

After everything is pulled to both places, then delete the topic
branch.

> Since the changes are spread through the codebase, we could very
> easily
> hit a situation that this topic branch creates conflicts for other
> patches getting merged on either drm-intel-next or drm-intel-gt-next.
> 
> +Joonas, +Rodrigo
> 
> Lucas De Marchi
> 
> > intel-next and gt-next at the same time so that the basic
> > definitions
> > are available to both trees?  It seems like the whole split into
> > two
> > trees really isn't working well and is just leading to more
> > mistakes and
> > bottlenecks.  What benefit are we supposed to be getting from this
> > split?
> > 
> > 
> > Matt
> > 
> > 
> > > 
> > > BR,
> > > Jani.
> > > 
> > > > 
> > > > My series also completely hides the arrays into a separate .c
> > > > file,
> > > > because the externs with direct array access are turning into
> > > > nightmare. The ARRAY_SIZE() checks rely on the extern
> > > > declaration and
> > > > the actual array definition to have the sizes in sync, but the
> > > > compiler
> > > > does not check that. Really.
> > > > 
> > > > IDK, feels like this merging this series is going to be extra
> > > > churn.
> > > > 
> > > > 
> > > > BR,
> > > > Jani.
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > Matt
> > > > > 
> > > > > > 
> > > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > > > > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> > > > > > ---
> > > > > >  .../drm/i915/display/intel_display_power.c    |  2 +-
> > > > > >  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
> > > > > >  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
> > > > > >  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++--
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/i915_drv.h               | 50
> > > > > > +++++++++----------
> > > > > >  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
> > > > > >  6 files changed, 43 insertions(+), 43 deletions(-)
> > > > > > 
> > > > > > diff --git
> > > > > > a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > index d52374f01316..bb04b502a442 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct
> > > > > > drm_i915_private *dev_priv)
> > > > > >         int config, i;
> > > > > > 
> > > > > >         if (IS_DG1_REVID(dev_priv, DG1_REVID_A0,
> > > > > > DG1_REVID_A0) ||
> > > > > > -           IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0,
> > > > > > TGL_REVID_B0))
> > > > > > +           IS_TGL_DISP_STEPPING(dev_priv, STEP_A0,
> > > > > > STEP_B0))
> > > > > >                 /* Wa_1409767108:tgl,dg1 */
> > > > > >                 table = wa_1409767108_buddy_page_masks;
> > > > > >         else
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index c24ae69426cf..a93717178957 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct
> > > > > > intel_dp *intel_dp)
> > > > > > 
> > > > > >         if (dev_priv->psr.psr2_sel_fetch_enabled) {
> > > > > >                 /* WA 1408330847 */
> > > > > > -               if (IS_TGL_DISP_REVID(dev_priv,
> > > > > > TGL_REVID_A0, TGL_REVID_A0) ||
> > > > > > +               if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0,
> > > > > > STEP_A0) ||
> > > > > >                     IS_RKL_REVID(dev_priv, RKL_REVID_A0,
> > > > > > RKL_REVID_A0))
> > > > > >                         intel_de_rmw(dev_priv,
> > > > > > CHICKEN_PAR1_1,
> > > > > >                                     
> > > > > > DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > > > > > @@ -1102,7 +1102,7 @@ static void
> > > > > > intel_psr_disable_locked(struct intel_dp *intel_dp)
> > > > > > 
> > > > > >         /* WA 1408330847 */
> > > > > >         if (dev_priv->psr.psr2_sel_fetch_enabled &&
> > > > > > -           (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0,
> > > > > > TGL_REVID_A0) ||
> > > > > > +           (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0,
> > > > > > STEP_A0) ||
> > > > > >              IS_RKL_REVID(dev_priv, RKL_REVID_A0,
> > > > > > RKL_REVID_A0)))
> > > > > >                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > > > >                              DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > > > > > 0);
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > > > index cf3589fd0ddb..4ce32df3855f 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > > > @@ -3033,7 +3033,7 @@ static bool
> > > > > > gen12_plane_supports_mc_ccs(struct drm_i915_private
> > > > > > *dev_priv,
> > > > > >  {
> > > > > >         /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> > > > > >         if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> > > > > > -           IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0,
> > > > > > TGL_REVID_C0))
> > > > > > +           IS_TGL_DISP_STEPPING(dev_priv, STEP_A0,
> > > > > > STEP_C0))
> > > > > >                 return false;
> > > > > > 
> > > > > >         return plane_id < PLANE_SPRITE4;
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > > index c21a9726326a..111d01e2f81e 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > > @@ -71,17 +71,17 @@ const struct i915_rev_steppings
> > > > > > kbl_revids[] = {
> > > > > >         [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping
> > > > > > = KBL_REVID_C0 },
> > > > > >  };
> > > > > > 
> > > > > > -const struct i915_rev_steppings tgl_uy_revids[] = {
> > > > > > -       [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping
> > > > > > = TGL_REVID_A0 },
> > > > > > -       [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping
> > > > > > = TGL_REVID_C0 },
> > > > > > -       [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping
> > > > > > = TGL_REVID_C0 },
> > > > > > -       [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping
> > > > > > = TGL_REVID_D0 },
> > > > > > +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] =
> > > > > > {
> > > > > > +       [0] = { .gt_stepping = STEP_A0, .disp_stepping =
> > > > > > STEP_A0 },
> > > > > > +       [1] = { .gt_stepping = STEP_B0, .disp_stepping =
> > > > > > STEP_C0 },
> > > > > > +       [2] = { .gt_stepping = STEP_B1, .disp_stepping =
> > > > > > STEP_C0 },
> > > > > > +       [3] = { .gt_stepping = STEP_C0, .disp_stepping =
> > > > > > STEP_D0 },
> > > > > >  };
> > > > > > 
> > > > > >  /* Same GT stepping between tgl_uy_revids and tgl_revids
> > > > > > don't mean the same HW */
> > > > > > -const struct i915_rev_steppings tgl_revids[] = {
> > > > > > -       [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping
> > > > > > = TGL_REVID_B0 },
> > > > > > -       [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping
> > > > > > = TGL_REVID_D0 },
> > > > > > +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
> > > > > > +       [0] = { .gt_stepping = STEP_A0, .disp_stepping =
> > > > > > STEP_B0 },
> > > > > > +       [1] = { .gt_stepping = STEP_B0, .disp_stepping =
> > > > > > STEP_D0 },
> > > > > >  };
> > > > > > 
> > > > > >  static void wa_init_start(struct i915_wa_list *wal, const
> > > > > > char *name, const char *engine_name)
> > > > > > @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct
> > > > > > drm_i915_private *i915, struct i915_wa_list *wal)
> > > > > >         gen12_gt_workarounds_init(i915, wal);
> > > > > > 
> > > > > >         /* Wa_1409420604:tgl */
> > > > > > -       if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0,
> > > > > > TGL_REVID_A0))
> > > > > > +       if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
> > > > > >                 wa_write_or(wal,
> > > > > >                             SUBSLICE_UNIT_LEVEL_CLKGATE2,
> > > > > >                             CPSSUNIT_CLKGATE_DIS);
> > > > > > 
> > > > > >         /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > > > > > -       if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0,
> > > > > > TGL_REVID_A0))
> > > > > > +       if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
> > > > > >                 wa_write_or(wal,
> > > > > >                             SLICE_UNIT_LEVEL_CLKGATE,
> > > > > >                             L3_CLKGATE_DIS |
> > > > > > L3_CR2X_CLKGATE_DIS);
> > > > > > 
> > > > > >         /* Wa_1408615072:tgl[a0] */
> > > > > > -       if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0,
> > > > > > TGL_REVID_A0))
> > > > > > +       if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
> > > > > >                 wa_write_or(wal,
> > > > > > UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > > > >                             VSUNIT_CLKGATE_DIS_TGL);
> > > > > >  }
> > > > > > @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct
> > > > > > intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > >         struct drm_i915_private *i915 = engine->i915;
> > > > > > 
> > > > > >         if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0)
> > > > > > ||
> > > > > > -           IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0,
> > > > > > TGL_REVID_A0)) {
> > > > > > +           IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
> > > > > > {
> > > > > >                 /*
> > > > > >                  * Wa_1607138336:tgl[a0],dg1[a0]
> > > > > >                  * Wa_1607063988:tgl[a0],dg1[a0]
> > > > > > @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct
> > > > > > intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > >                            
> > > > > > GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > > > > >         }
> > > > > > 
> > > > > > -       if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0,
> > > > > > TGL_REVID_A0)) {
> > > > > > +       if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
> > > > > > {
> > > > > >                 /*
> > > > > >                  * Wa_1606679103:tgl
> > > > > >                  * (see also Wa_1606682166:icl)
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > index 5e5bcef20e33..11d6e8abde46 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > @@ -1559,54 +1559,54 @@ extern const struct
> > > > > > i915_rev_steppings kbl_revids[];
> > > > > >         (IS_JSL_EHL(p) && IS_REVID(p, since, until))
> > > > > > 
> > > > > >  enum {
> > > > > > -       TGL_REVID_A0,
> > > > > > -       TGL_REVID_B0,
> > > > > > -       TGL_REVID_B1,
> > > > > > -       TGL_REVID_C0,
> > > > > > -       TGL_REVID_D0,
> > > > > > +       STEP_A0,
> > > > > > +       STEP_B0,
> > > > > > +       STEP_B1,
> > > > > > +       STEP_C0,
> > > > > > +       STEP_D0,
> > > > > >  };
> > > > > > 
> > > > > > -#define TGL_UY_REVIDS_SIZE     4
> > > > > > -#define TGL_REVIDS_SIZE                2
> > > > > > +#define TGL_UY_REVID_STEP_TBL_SIZE     4
> > > > > > +#define TGL_REVID_STEP_TBL_SIZE                2
> > > > > > 
> > > > > > -extern const struct i915_rev_steppings
> > > > > > tgl_uy_revids[TGL_UY_REVIDS_SIZE];
> > > > > > -extern const struct i915_rev_steppings
> > > > > > tgl_revids[TGL_REVIDS_SIZE];
> > > > > > +extern const struct i915_rev_steppings
> > > > > > tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
> > > > > > +extern const struct i915_rev_steppings
> > > > > > tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
> > > > > > 
> > > > > >  static inline const struct i915_rev_steppings *
> > > > > > -tgl_revids_get(struct drm_i915_private *dev_priv)
> > > > > > +tgl_stepping_get(struct drm_i915_private *dev_priv)
> > > > > >  {
> > > > > >         u8 revid = INTEL_REVID(dev_priv);
> > > > > >         u8 size;
> > > > > > -       const struct i915_rev_steppings *tgl_revid_tbl;
> > > > > > +       const struct i915_rev_steppings *revid_step_tbl;
> > > > > > 
> > > > > >         if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> > > > > > -               tgl_revid_tbl = tgl_uy_revids;
> > > > > > -               size = ARRAY_SIZE(tgl_uy_revids);
> > > > > > +               revid_step_tbl = tgl_uy_revid_step_tbl;
> > > > > > +               size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
> > > > > >         } else {
> > > > > > -               tgl_revid_tbl = tgl_revids;
> > > > > > -               size = ARRAY_SIZE(tgl_revids);
> > > > > > +               revid_step_tbl = tgl_revid_step_tbl;
> > > > > > +               size = ARRAY_SIZE(tgl_revid_step_tbl);
> > > > > >         }
> > > > > > 
> > > > > >         revid = min_t(u8, revid, size - 1);
> > > > > > 
> > > > > > -       return &tgl_revid_tbl[revid];
> > > > > > +       return &revid_step_tbl[revid];
> > > > > >  }
> > > > > > 
> > > > > > -#define IS_TGL_DISP_REVID(p, since, until) \
> > > > > > +#define IS_TGL_DISP_STEPPING(p, since, until) \
> > > > > >         (IS_TIGERLAKE(p) && \
> > > > > > -        tgl_revids_get(p)->disp_stepping >= (since) && \
> > > > > > -        tgl_revids_get(p)->disp_stepping <= (until))
> > > > > > +        tgl_stepping_get(p)->disp_stepping >= (since) && \
> > > > > > +        tgl_stepping_get(p)->disp_stepping <= (until))
> > > > > > 
> > > > > > -#define IS_TGL_UY_GT_REVID(p, since, until) \
> > > > > > +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
> > > > > >         ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
> > > > > > -        tgl_revids_get(p)->gt_stepping >= (since) && \
> > > > > > -        tgl_revids_get(p)->gt_stepping <= (until))
> > > > > > +        tgl_stepping_get(p)->gt_stepping >= (since) && \
> > > > > > +        tgl_stepping_get(p)->gt_stepping <= (until))
> > > > > > 
> > > > > > -#define IS_TGL_GT_REVID(p, since, until) \
> > > > > > +#define IS_TGL_GT_STEPPING(p, since, until) \
> > > > > >         (IS_TIGERLAKE(p) && \
> > > > > >          !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
> > > > > > -        tgl_revids_get(p)->gt_stepping >= (since) && \
> > > > > > -        tgl_revids_get(p)->gt_stepping <= (until))
> > > > > > +        tgl_stepping_get(p)->gt_stepping >= (since) && \
> > > > > > +        tgl_stepping_get(p)->gt_stepping <= (until))
> > > > > > 
> > > > > >  #define RKL_REVID_A0           0x0
> > > > > >  #define RKL_REVID_B0           0x1
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index bbc73df7f753..319acca2630b 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -7110,7 +7110,7 @@ static void
> > > > > > tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> > > > > >                    ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> > > > > > 
> > > > > >         /* Wa_1409825376:tgl (pre-prod)*/
> > > > > > -       if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0,
> > > > > > TGL_REVID_B1))
> > > > > > +       if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0,
> > > > > > STEP_B1))
> > > > > >                 intel_uncore_write(&dev_priv->uncore,
> > > > > > GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore,
> > > > > > GEN9_CLKGATE_DIS_3) |
> > > > > >                            TGL_VRH_GATING_DIS);
> > > > > > 
> > > > > > --
> > > > > > 2.27.0
> > > > > > 
> > > 
> > > --
> > > Jani Nikula, Intel Open Source Graphics Center
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-12 17:33             ` Vivi, Rodrigo
@ 2021-01-12 17:39               ` Jani Nikula
  0 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2021-01-12 17:39 UTC (permalink / raw)
  To: Vivi, Rodrigo, Roper, Matthew D, De Marchi, Lucas; +Cc: intel-gfx

On Tue, 12 Jan 2021, "Vivi, Rodrigo" <rodrigo.vivi@intel.com> wrote:
> On Mon, 2021-01-11 at 13:25 -0800, Lucas De Marchi wrote:
>> last time we talked about this was regarding dg1 AFAIR and the
>> consensus was to create a topic branch and that topic branch to be
>> merged in both branches. That would avoid having 2 commits in
>> different branches.
>
> Yeap, I believe this is the way to go.
>
>> 
>> Not sure if it would work out nicely for getting test on CI though.
>
> create an empty topic branch using dim.
>
> Pre-merge CI with drm-tip. Only if passing and if everything is realy
> ready. Push to the topic branch using dim.
>
> Then it will be part of drm-tip already for any subsequential pre-merge
> CI...
>
> Then do the pull requests to bot drm-intel-next and drm-intel-gt-next.
>
> After everything is pulled to both places, then delete the topic
> branch.

Atm the problem is this:

$ git merge-base drm-intel/drm-intel-next drm-intel/drm-intel-gt-next

That would be the baseline for the topic branch.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
  2021-01-11 19:29 [Intel-gfx] [PATCH 0/2] " Aditya Swarup
@ 2021-01-11 19:29 ` Aditya Swarup
  0 siblings, 0 replies; 24+ messages in thread
From: Aditya Swarup @ 2021-01-11 19:29 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

TGL adds another level of indirection for applying WA based on stepping
information rather than PCI REVID. So change TGL_REVID enum into
stepping enum and use PCI REVID as index into revid to stepping table to
fetch correct display and GT stepping for application of WAs as
suggested by Matt Roper.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 .../drm/i915/display/intel_display_power.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
 drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
 drivers/gpu/drm/i915/intel_pm.c               |  2 +-
 6 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d52374f01316..bb04b502a442 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	int config, i;
 
 	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
-	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
 		/* Wa_1409767108:tgl,dg1 */
 		table = wa_1409767108_buddy_page_masks;
 	else
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c24ae69426cf..a93717178957 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	if (dev_priv->psr.psr2_sel_fetch_enabled) {
 		/* WA 1408330847 */
-		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
 		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
 			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	/* WA 1408330847 */
 	if (dev_priv->psr.psr2_sel_fetch_enabled &&
-	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
 	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index cf3589fd0ddb..4ce32df3855f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 {
 	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
 	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
 		return false;
 
 	return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c21a9726326a..111d01e2f81e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
 	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
 };
 
-const struct i915_rev_steppings tgl_uy_revids[] = {
-	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
-	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
-	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
-	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
+const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
+	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
+	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
+	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
+	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
 };
 
 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
-const struct i915_rev_steppings tgl_revids[] = {
-	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
-	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
+const struct i915_rev_steppings tgl_revid_step_tbl[] = {
+	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
+	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
 };
 
 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
@@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	gen12_gt_workarounds_init(i915, wal);
 
 	/* Wa_1409420604:tgl */
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
 			    CPSSUNIT_CLKGATE_DIS);
 
 	/* Wa_1607087056:tgl also know as BUG:1409180338 */
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 
 	/* Wa_1408615072:tgl[a0] */
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
 			    VSUNIT_CLKGATE_DIS_TGL);
 }
@@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	struct drm_i915_private *i915 = engine->i915;
 
 	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
-	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
 		/*
 		 * Wa_1607138336:tgl[a0],dg1[a0]
 		 * Wa_1607063988:tgl[a0],dg1[a0]
@@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
 	}
 
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
 		/*
 		 * Wa_1606679103:tgl
 		 * (see also Wa_1606682166:icl)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5e5bcef20e33..11d6e8abde46 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
 	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
 
 enum {
-	TGL_REVID_A0,
-	TGL_REVID_B0,
-	TGL_REVID_B1,
-	TGL_REVID_C0,
-	TGL_REVID_D0,
+	STEP_A0,
+	STEP_B0,
+	STEP_B1,
+	STEP_C0,
+	STEP_D0,
 };
 
-#define TGL_UY_REVIDS_SIZE	4
-#define TGL_REVIDS_SIZE		2
+#define TGL_UY_REVID_STEP_TBL_SIZE	4
+#define TGL_REVID_STEP_TBL_SIZE		2
 
-extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
-extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
+extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
+extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
 
 static inline const struct i915_rev_steppings *
-tgl_revids_get(struct drm_i915_private *dev_priv)
+tgl_stepping_get(struct drm_i915_private *dev_priv)
 {
 	u8 revid = INTEL_REVID(dev_priv);
 	u8 size;
-	const struct i915_rev_steppings *tgl_revid_tbl;
+	const struct i915_rev_steppings *revid_step_tbl;
 
 	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
-		tgl_revid_tbl = tgl_uy_revids;
-		size = ARRAY_SIZE(tgl_uy_revids);
+		revid_step_tbl = tgl_uy_revid_step_tbl;
+		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
 	} else {
-		tgl_revid_tbl = tgl_revids;
-		size = ARRAY_SIZE(tgl_revids);
+		revid_step_tbl = tgl_revid_step_tbl;
+		size = ARRAY_SIZE(tgl_revid_step_tbl);
 	}
 
 	revid = min_t(u8, revid, size - 1);
 
-	return &tgl_revid_tbl[revid];
+	return &revid_step_tbl[revid];
 }
 
-#define IS_TGL_DISP_REVID(p, since, until) \
+#define IS_TGL_DISP_STEPPING(p, since, until) \
 	(IS_TIGERLAKE(p) && \
-	 tgl_revids_get(p)->disp_stepping >= (since) && \
-	 tgl_revids_get(p)->disp_stepping <= (until))
+	 tgl_stepping_get(p)->disp_stepping >= (since) && \
+	 tgl_stepping_get(p)->disp_stepping <= (until))
 
-#define IS_TGL_UY_GT_REVID(p, since, until) \
+#define IS_TGL_UY_GT_STEPPING(p, since, until) \
 	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
-	 tgl_revids_get(p)->gt_stepping >= (since) && \
-	 tgl_revids_get(p)->gt_stepping <= (until))
+	 tgl_stepping_get(p)->gt_stepping >= (since) && \
+	 tgl_stepping_get(p)->gt_stepping <= (until))
 
-#define IS_TGL_GT_REVID(p, since, until) \
+#define IS_TGL_GT_STEPPING(p, since, until) \
 	(IS_TIGERLAKE(p) && \
 	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
-	 tgl_revids_get(p)->gt_stepping >= (since) && \
-	 tgl_revids_get(p)->gt_stepping <= (until))
+	 tgl_stepping_get(p)->gt_stepping >= (since) && \
+	 tgl_stepping_get(p)->gt_stepping <= (until))
 
 #define RKL_REVID_A0		0x0
 #define RKL_REVID_B0		0x1
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bbc73df7f753..319acca2630b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
 	/* Wa_1409825376:tgl (pre-prod)*/
-	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
+	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
 		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   TGL_VRH_GATING_DIS);
 
-- 
2.27.0

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^ permalink raw reply related	[flat|nested] 24+ messages in thread

end of thread, other threads:[~2021-01-12 17:40 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-08 23:18 [Intel-gfx] [PATCH 0/2] Use TGL stepping info and add ADLS platform changes Aditya Swarup
2021-01-08 23:18 ` [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs Aditya Swarup
2021-01-08 23:44   ` Matt Roper
2021-01-11 20:13     ` Jani Nikula
2021-01-11 20:18       ` Jani Nikula
2021-01-11 20:57         ` Matt Roper
2021-01-11 21:25           ` Lucas De Marchi
2021-01-12 16:24             ` Jani Nikula
2021-01-12 17:16               ` Matt Roper
2021-01-12 17:33             ` Vivi, Rodrigo
2021-01-12 17:39               ` Jani Nikula
2021-01-11 22:58           ` Aditya Swarup
2021-01-12 16:32             ` Jani Nikula
2021-01-11 20:20       ` Aditya Swarup
2021-01-12 16:11         ` Jani Nikula
2021-01-12  2:04       ` Lucas De Marchi
2021-01-12 16:18         ` Jani Nikula
2021-01-08 23:18 ` [Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
2021-01-09  0:20   ` Matt Roper
2021-01-11 19:37     ` Aditya Swarup
2021-01-09  2:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use TGL stepping info and add ADLS platform changes Patchwork
2021-01-09  2:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-09 10:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-11 19:29 [Intel-gfx] [PATCH 0/2] " Aditya Swarup
2021-01-11 19:29 ` [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs Aditya Swarup

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