From mboxrd@z Thu Jan 1 00:00:00 1970 From: Patrick DELAUNAY Date: Mon, 11 Feb 2019 11:56:27 +0000 Subject: [U-Boot] [PATCH 1/2] fdt: Allow indicating a node is for U-Boot proper only References: <1549275292-3134-1-git-send-email-patrick.delaunay@st.com> <53f1641f-7c55-9a34-8655-7bc41bc01d26@denx.de> <0e9b24dbc05f49308306a4bf9db948a7@SFHDAG6NODE3.st.com> <13efb4ac-ef65-ea70-d2a1-47a804091efa@denx.de> Message-ID: <0f3d9121c5e946fb9758681a0a3ce3e3@SFHDAG6NODE3.st.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de Hi Marek and Simon > From: Patrick DELAUNAY > Sent: vendredi 8 février 2019 13:47 > > Hi Marek, > > > From: Marek Vasut > > Sent: jeudi 7 février 2019 18:48 > > > > On 2/7/19 6:40 PM, Patrick DELAUNAY wrote: > > > Hi Marek, > > > > > >> From: Marek Vasut > > >> Sent: mardi 5 février 2019 09:55 > > >> > > >> On 2/4/19 3:40 PM, Simon Glass wrote: > > >>> On Mon, 4 Feb 2019 at 03:15, Patrick Delaunay > > >>> > > >> wrote: > > >>>> > > >>>> This add missing parts for previous commit 06f94461a9f4 > > >>>> ("fdt: Allow indicating a node is for U-Boot proper only") > > >>>> > > >>>> At present it is not possible to specify that a node should be > > >>>> used before relocation (in U-Boot proper) without it also ending > > >>>> up in SPL and TPL device trees. Add a new "u-boot,dm-pre-proper" > > >>>> boolean property > > >> for this. > > >>>> > > >>>> > > >>>> Signed-off-by: Patrick Delaunay > > >>> ... > > > NB: we could also remove the tags u-boot,dm-pre-reloc/u-boot,dm-spl > > > : we > > can gain place in spl dtb > > > These tags are not needed as binding is mandatory in SPL > > > build for ALL > > node present in SPL device tree > > > others node are cleaned by fdtgrep (but impact in SPL code) > > Finally I will sent a patch for this proposal (today I hope) => On my board > stm32mp1-ev1, the SPL device tree is reduced by 790 bytes FYI: patch sent with http://patchwork.ozlabs.org/patch/1039756/ > NB: side effect on the patch, we only need to TAG the children (all node are > bounded in SPL) > That improve the next point. After test, the phandle of the parent node is remove when the tag preloc or spl is not present.... So the need to tag all the DT tree is not solved. Regards Patrick