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Mon, 30 Mar 2020 13:11:34 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D926F100038; Mon, 30 Mar 2020 13:11:33 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CCED62AD2AB; Mon, 30 Mar 2020 13:11:33 +0200 (CEST) Received: from SFHDAG6NODE3.st.com (10.75.127.18) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 30 Mar 2020 13:11:33 +0200 Received: from SFHDAG6NODE3.st.com ([fe80::d04:5337:ab17:b6f6]) by SFHDAG6NODE3.st.com ([fe80::d04:5337:ab17:b6f6%20]) with mapi id 15.00.1473.003; Mon, 30 Mar 2020 13:11:33 +0200 From: Patrice CHOTARD To: Marek Vasut , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH 07/22] ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7 Thread-Topic: [PATCH 07/22] ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7 Thread-Index: AQHWBSQA4U8QbAdEAEu5txLKBHyoDKhg3CGA Date: Mon, 30 Mar 2020 11:11:33 +0000 Message-ID: <0fb89d25-feb0-2eb0-9e83-d7f8c76f8b9e@st.com> References: <20200328171144.51888-1-marex@denx.de> <20200328171144.51888-8-marex@denx.de> In-Reply-To: <20200328171144.51888-8-marex@denx.de> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.47] Content-ID: <0560D2E8DFAA6E4BB0C9993495FF72A8@st.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.645 definitions=2020-03-30_01:2020-03-27, 2020-03-30 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200330_041141_243743_3A995FD7 X-CRM114-Status: GOOD ( 19.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Patrick DELAUNAY , Alexandre TORGUE , Maxime Coquelin , "linux-stm32@st-md-mailman.stormreply.com" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marek On 3/28/20 6:11 PM, Marek Vasut wrote: > Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board. > > Signed-off-by: Marek Vasut > Cc: Alexandre Torgue > Cc: Maxime Coquelin > Cc: Patrice Chotard > Cc: Patrick Delaunay > Cc: linux-stm32@st-md-mailman.stormreply.com > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > index bfd255dfe81f..6a37af213eb6 100644 > --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > @@ -1062,6 +1062,27 @@ pins { > }; > }; > > + sdmmc2_d47_pins_b: sdmmc2-d47-1 { > + pins { > + pinmux = , /* SDMMC2_D4 */ > + , /* SDMMC2_D5 */ > + , /* SDMMC2_D6 */ > + ; /* SDMMC2_D7 */ > + slew-rate = <1>; > + drive-push-pull; > + bias-pull-up; > + }; > + }; > + > + sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { > + pins { > + pinmux = , /* SDMMC2_D4 */ > + , /* SDMMC2_D5 */ > + , /* SDMMC2_D6 */ > + ; /* SDMMC2_D7 */ > + }; > + }; > + > sdmmc3_b4_pins_a: sdmmc3-b4-0 { > pins1 { > pinmux = , /* SDMMC3_D0 */ For your information, another submitted patch uses the same pinctrl sdmmc2_d47_pins_b node with different muxing (SDMMC2_D5) see https://lore.kernel.org/patchwork/patch/1216452/ I haven't checked other muxing if there are other conflict. Patrice _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel