From mboxrd@z Thu Jan 1 00:00:00 1970 From: Segher Boessenkool Subject: Re: [PATCH 10/13] kvm/powerpc: Add support for Book3S processors in hypervisor mode Date: Sat, 28 May 2011 03:07:04 +0200 Message-ID: <10cc079a31947ec4b6d39f30f2ac50f2@kernel.crashing.org> References: <20110511103443.GA2837@brick.ozlabs.ibm.com> <20110511104456.GK2837@brick.ozlabs.ibm.com> <20110516055809.GA3590@drongo> <20110527103334.GA4236@brick.ozlabs.ibm.com> <6A1CA2C8-8032-4D67-9C14-4ABD81ABCDD7@suse.de> Mime-Version: 1.0 (Apple Message framework v624) Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Cc: Linuxppc-dev , Paul Mackerras , KVM list , kvm-ppc@vger.kernel.org To: Alexander Graf Return-path: Received: from gate.crashing.org ([63.228.1.57]:56154 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757658Ab1E1BFf (ORCPT ); Fri, 27 May 2011 21:05:35 -0400 In-Reply-To: <6A1CA2C8-8032-4D67-9C14-4ABD81ABCDD7@suse.de> Sender: kvm-owner@vger.kernel.org List-ID: >>> If HDEC expires when interrupts are off, the HDEC interrupt stays >>> pending until interrupts get re-enabled. I'm not sure exactly what >>> the conditions are that cause an HDEC interrupt to get lost, but they >>> seem to involve at least a partition switch. >> >> On some CPUs, if the top bit of the decrementer is 0 again when you >> re-enable >> the interrupt, the interrupt is lost (so it is actually >> level-triggered). >> The arch books talk a bit about this AFAIR. > > Sure, but that shouldn't happen with HDEC during the odd 50 > instructions that it takes to enter the guest :) It's more like 500 insns, including some ptesync, so lots of cycles too. Can another hardware thread be running at the same time? Segher From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7F19FB6F8F for ; Sat, 28 May 2011 11:05:27 +1000 (EST) In-Reply-To: <6A1CA2C8-8032-4D67-9C14-4ABD81ABCDD7@suse.de> References: <20110511103443.GA2837@brick.ozlabs.ibm.com> <20110511104456.GK2837@brick.ozlabs.ibm.com> <20110516055809.GA3590@drongo> <20110527103334.GA4236@brick.ozlabs.ibm.com> <6A1CA2C8-8032-4D67-9C14-4ABD81ABCDD7@suse.de> Mime-Version: 1.0 (Apple Message framework v624) Content-Type: text/plain; charset=US-ASCII; format=flowed Message-Id: <10cc079a31947ec4b6d39f30f2ac50f2@kernel.crashing.org> From: Segher Boessenkool Subject: Re: [PATCH 10/13] kvm/powerpc: Add support for Book3S processors in hypervisor mode Date: Sat, 28 May 2011 03:07:04 +0200 To: Alexander Graf Cc: Linuxppc-dev , Paul Mackerras , kvm-ppc@vger.kernel.org, KVM list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , >>> If HDEC expires when interrupts are off, the HDEC interrupt stays >>> pending until interrupts get re-enabled. I'm not sure exactly what >>> the conditions are that cause an HDEC interrupt to get lost, but they >>> seem to involve at least a partition switch. >> >> On some CPUs, if the top bit of the decrementer is 0 again when you >> re-enable >> the interrupt, the interrupt is lost (so it is actually >> level-triggered). >> The arch books talk a bit about this AFAIR. > > Sure, but that shouldn't happen with HDEC during the odd 50 > instructions that it takes to enter the guest :) It's more like 500 insns, including some ptesync, so lots of cycles too. Can another hardware thread be running at the same time? Segher From mboxrd@z Thu Jan 1 00:00:00 1970 From: Segher Boessenkool Date: Sat, 28 May 2011 01:07:04 +0000 Subject: Re: [PATCH 10/13] kvm/powerpc: Add support for Book3S processors in hypervisor mode Message-Id: <10cc079a31947ec4b6d39f30f2ac50f2@kernel.crashing.org> List-Id: References: <20110511103443.GA2837@brick.ozlabs.ibm.com> <20110511104456.GK2837@brick.ozlabs.ibm.com> <20110516055809.GA3590@drongo> <20110527103334.GA4236@brick.ozlabs.ibm.com> <6A1CA2C8-8032-4D67-9C14-4ABD81ABCDD7@suse.de> In-Reply-To: <6A1CA2C8-8032-4D67-9C14-4ABD81ABCDD7@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Alexander Graf Cc: Linuxppc-dev , Paul Mackerras , KVM list , kvm-ppc@vger.kernel.org >>> If HDEC expires when interrupts are off, the HDEC interrupt stays >>> pending until interrupts get re-enabled. I'm not sure exactly what >>> the conditions are that cause an HDEC interrupt to get lost, but they >>> seem to involve at least a partition switch. >> >> On some CPUs, if the top bit of the decrementer is 0 again when you >> re-enable >> the interrupt, the interrupt is lost (so it is actually >> level-triggered). >> The arch books talk a bit about this AFAIR. > > Sure, but that shouldn't happen with HDEC during the odd 50 > instructions that it takes to enter the guest :) It's more like 500 insns, including some ptesync, so lots of cycles too. Can another hardware thread be running at the same time? Segher