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Sun, 07 Mar 2021 19:18:57 +0000 To: Laurent Vivier , qemu-devel@nongnu.org References: <20210307182210.473111-1-laurent@vivier.eu> From: Mark Cave-Ayland Message-ID: <10e2920f-cbd9-947f-c116-54bb2fe551aa@ilande.co.uk> Date: Sun, 7 Mar 2021 19:18:52 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.0 MIME-Version: 1.0 In-Reply-To: <20210307182210.473111-1-laurent@vivier.eu> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: Re: [PATCH v2] target/m68k: implement rtr instruction X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 07/03/2021 18:22, Laurent Vivier wrote: > This is needed to boot MacOS ROM. > > Pull the condition code and the program counter from the stack. > > Operation: > > (SP) -> CCR > SP + 2 -> SP > (SP) -> PC > SP + 4 - > SP > > This operation is not privileged. > > Reported-by: Mark Cave-Ayland > Signed-off-by: Laurent Vivier > --- > > Notes: > v2: update comment > SP + 4 -> SP > > target/m68k/translate.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/target/m68k/translate.c b/target/m68k/translate.c > index ac936ebe8f14..e6942955713c 100644 > --- a/target/m68k/translate.c > +++ b/target/m68k/translate.c > @@ -2969,6 +2969,20 @@ DISAS_INSN(rtd) > gen_jmp(s, tmp); > } > > +DISAS_INSN(rtr) > +{ > + TCGv tmp; > + TCGv ccr; > + > + ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s)); > + gen_set_sr(s, ccr, true); > + tcg_temp_free(ccr); > + tcg_gen_addi_i32(QREG_SP, QREG_SP, 2); > + tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s)); > + tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); > + gen_jmp(s, tmp); > +} > + > DISAS_INSN(rts) > { > TCGv tmp; > @@ -6015,6 +6029,7 @@ void register_m68k_insns (CPUM68KState *env) > BASE(nop, 4e71, ffff); > INSN(rtd, 4e74, ffff, RTD); > BASE(rts, 4e75, ffff); > + INSN(rtr, 4e77, ffff, M68000); > BASE(jump, 4e80, ffc0); > BASE(jump, 4ec0, ffc0); > INSN(addsubq, 5000, f080, M68000); Solves the issue for me, so: Tested-by: Mark Cave-Ayland I also have a couple of other target/m68k patches from my experimental branch which are probably worth adding to an m68k PR. Let me go dig them out... ATB, Mark.