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Date: Wed, 10 Nov 2004 15:15:07 +0100
From: olivier cozette <olivier.cozette@u-picardie.fr>
Subject: Re:Another related question Re: [Qemu-devel] Question about softmmu
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To: qemu-devel@nongnu.org

  Hello Ye,


>So EIP is just the offset of current instruction.

Yes

>When address mapping changes,
>the CS segment register also changes.

No.
The virtual adress is CS+EIP (CS.Base+EIP), this virtual address is trans=
lated
to the physical address with the page mapping. In pseudo code, the real a=
ddress
is PAGE_MAPPING(CS+EIP). So, if the page mapping change the CS stay the s=
ame.

>That's why QEMU does not need to flush
>the code. Am I right?


>The reason I'm thinking about this is because I'm implementing QEMU's
>translation method in my ARM simulator which needs to simulate the whole=
 system
>running Linux. In ARM, since PC is just r15, you can access it as a norm=
al
>register and it is the absolute virtual address. So I wonder if I have t=
o flush
>code cache every time page table changes.

I don't know well ARM processor, but i know Alpha, and it's different fro=
m the
x86.

With x86, the data stored in the data/code cache are stored with the phys=
ical
address (page mapping is done between processor and cache), and so the ca=
che
don't need to be flushed when page mapping change (CR3 change).

With alpha (and probably arm), the address stored in cache are the virtua=
l
address (page mapping is done between cache and memory).

But, i presume this difference have no impact with Qemu cache, and it wil=
l be
better to don't flush qemu cache.



   Olivier


Thanks,
Ye