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Wed, 8 Jul 2020 10:32:20 -0400 (EDT) Received: from mail03.efficios.com (mail03.efficios.com [167.114.26.124]) by mail.efficios.com (Postfix) with ESMTP id BCA381B5E9A; Wed, 8 Jul 2020 10:32:20 -0400 (EDT) Date: Wed, 8 Jul 2020 10:32:20 -0400 (EDT) From: Mathieu Desnoyers To: Christophe Leroy Message-ID: <1137155888.2676.1594218740683.JavaMail.zimbra@efficios.com> In-Reply-To: <96994487-ae4a-3bfb-b0f1-34228e51bea2@csgroup.eu> References: <972420887.755.1594149430308.JavaMail.zimbra@efficios.com> <20200708005922.GW3598@gate.crashing.org> <841816533.1735.1594211583710.JavaMail.zimbra@efficios.com> <1623833219.1877.1594216801865.JavaMail.zimbra@efficios.com> <96994487-ae4a-3bfb-b0f1-34228e51bea2@csgroup.eu> Subject: Re: Failure to build librseq on ppc MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [167.114.26.124] X-Mailer: Zimbra 8.8.15_GA_3955 (ZimbraWebClient - FF78 (Linux)/8.8.15_GA_3953) Thread-Topic: Failure to build librseq on ppc Thread-Index: 06yJtaljCBbbI+2aEUpB/bOBXHcqEA== X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Boqun Feng , linuxppc-dev , Michael Jeanson Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" ----- On Jul 8, 2020, at 10:21 AM, Christophe Leroy christophe.leroy@csgrou= p.eu wrote: > Le 08/07/2020 =C3=A0 16:00, Mathieu Desnoyers a =C3=A9crit=C2=A0: >> ----- On Jul 8, 2020, at 8:33 AM, Mathieu Desnoyers >> mathieu.desnoyers@efficios.com wrote: >>=20 >>> ----- On Jul 7, 2020, at 8:59 PM, Segher Boessenkool segher@kernel.cras= hing.org >>> wrote: >> [...] >>>> >>>> So perhaps you have code like >>>> >>>> int *p; >>>> int x; >>>> ... >>>> asm ("lwz %0,%1" : "=3Dr"(x) : "m"(*p)); >>> >>> We indeed have explicit "lwz" and "stw" instructions in there. >>> >>>> >>>> where that last line should actually read >>>> >>>> asm ("lwz%X1 %0,%1" : "=3Dr"(x) : "m"(*p)); >>> >>> Indeed, turning those into "lwzx" and "stwx" seems to fix the issue. >>> >>> There has been some level of extra CPP macro coating around those instr= uctions >>> to >>> support both ppc32 and ppc64 with the same assembly. So adding %X[arg] = is not >>> trivial. >>> Let me see what can be done here. >>=20 >> I did the following changes which appear to generate valid asm. >> See attached corresponding .S output. >>=20 >> I grepped for uses of "m" asm operand in Linux powerpc code and noticed = it's >> pretty much >> always used with e.g. "lwz%U1%X1". I could find one blog post discussing= that %U >> is about >> update flag, and nothing about %X. Are those documented ? >=20 > As far as I can see, %U is mentioned in > https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html in the > powerpc subpart, at the "m" constraint. Yep, I did notice it, but mistakenly thought it was only needed for "m<>" o= perand, not "m". Thanks, Mathieu >=20 > For the %X I don't know. >=20 > Christophe >=20 >>=20 >> Although it appears to generate valid asm, I have the feeling I'm relyin= g on >> undocumented >> features here. :-/ --=20 Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com