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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Markus Armbruster <armbru@redhat.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Joel Stanley" <joel@jms.id.au>,
	"Havard Skinnemoen" <hskinnemoen@google.com>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"CS20 KFTing" <kfting@nuvoton.com>,
	qemu-arm <qemu-arm@nongnu.org>,
	"IS20 Avi Fishman" <Avi.Fishman@nuvoton.com>,
	"Cédric Le Goater" <clg@kaod.org>
Subject: Re: [PATCH v5 04/11] hw/arm: Add NPCM730 and NPCM750 SoC models
Date: Tue, 14 Jul 2020 19:11:04 +0200	[thread overview]
Message-ID: <11c410d4-b310-faf1-5116-2ab62270c3cb@amsat.org> (raw)
In-Reply-To: <877dv63x2e.fsf@dusky.pond.sub.org>

On 7/14/20 6:01 PM, Markus Armbruster wrote:
> Philippe Mathieu-Daudé <f4bug@amsat.org> writes:
> 
>> +Markus
>>
>> On 7/14/20 2:44 AM, Havard Skinnemoen wrote:
>>> On Mon, Jul 13, 2020 at 8:02 AM Cédric Le Goater <clg@kaod.org> wrote:
>>>>
>>>> On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
>>>>> The Nuvoton NPCM7xx SoC family are used to implement Baseboard
>>>>> Management Controllers in servers. While the family includes four SoCs,
>>>>> this patch implements limited support for two of them: NPCM730 (targeted
>>>>> for Data Center applications) and NPCM750 (targeted for Enterprise
>>>>> applications).
>>>>>
>>>>> This patch includes little more than the bare minimum needed to boot a
>>>>> Linux kernel built with NPCM7xx support in direct-kernel mode:
>>>>>
>>>>>   - Two Cortex-A9 CPU cores with built-in periperhals.
>>>>>   - Global Configuration Registers.
>>>>>   - Clock Management.
>>>>>   - 3 Timer Modules with 5 timers each.
>>>>>   - 4 serial ports.
>>>>>
>>>>> The chips themselves have a lot more features, some of which will be
>>>>> added to the model at a later stage.
>>>>>
>>>>> Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
>>>>> Reviewed-by: Joel Stanley <joel@jms.id.au>
>>>>> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
>>>>> ---
>> ...
>>
>>>>> +static void npcm7xx_realize(DeviceState *dev, Error **errp)
>>>>> +{
>>>>> +    NPCM7xxState *s = NPCM7XX(dev);
>>>>> +    NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
>>>>> +    int i;
>>>>> +
>>>>> +    /* CPUs */
>>>>> +    for (i = 0; i < nc->num_cpus; i++) {
>>>>> +        object_property_set_int(OBJECT(&s->cpu[i]),
>>>>> +                                arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
>>>>> +                                "mp-affinity", &error_abort);
>>>>> +        object_property_set_int(OBJECT(&s->cpu[i]), NPCM7XX_GIC_CPU_IF_ADDR,
>>>>> +                                "reset-cbar", &error_abort);
>>>>> +        object_property_set_bool(OBJECT(&s->cpu[i]), true,
>>>>> +                                 "reset-hivecs", &error_abort);
>>>>> +
>>>>> +        /* Disable security extensions. */
>>>>> +        object_property_set_bool(OBJECT(&s->cpu[i]), false, "has_el3",
>>>>> +                                 &error_abort);
>>>>> +
>>>>> +        qdev_realize(DEVICE(&s->cpu[i]), NULL, &error_abort);
>>>>
>>>> I would check the error:
>>>>
>>>>         if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
>>>>             return;
>>>>         }
>>>>
>>>> same for the sysbus_realize() below.
>>>
>>> Hmm, I used to propagate these errors until Philippe told me not to
>>> (or at least that's how I understood it).
>>
>> It was before Markus simplification API were merged, you had to
>> propagate after each call, since this is a non hot-pluggable SoC
>> I suggested to use &error_abort to simplify.
>>
>>> I'll be happy to do it
>>> either way (and the new API makes it really easy to propagate errors),
>>> but I worry that I don't fully understand when to propagate errors and
>>> when not to.
>>
>> Markus explained it on the mailing list recently (as I found the doc
>> not obvious). I can't find the thread. I suppose once the work result
>> after the "Questionable aspects of QEMU Error's design" discussion is
>> merged, the documentation will be clarified.
> 
> The Error API evolved recently.  Please peruse the big comment in
> include/qapi/error.h.  If still unsure, don't hesitate to ask here.
> 
>> My rule of thumb so far is:
>> - programming error (can't happen) -> &error_abort
> 
> Correct.  Quote the big comment:
> 
>  * Call a function aborting on errors:
>  *     foo(arg, &error_abort);
>  * This is more concise and fails more nicely than
>  *     Error *err = NULL;
>  *     foo(arg, &err);
>  *     assert(!err); // don't do this
> 
>> - everything triggerable by user or management layer (via QMP command)
>>   -> &error_fatal, as we can't risk loose the user data, we need to
>>   shutdown gracefully.
> 
> Quote the big comment:
> 
>  * Call a function treating errors as fatal:
>  *     foo(arg, &error_fatal);
>  * This is more concise than
>  *     Error *err = NULL;
>  *     foo(arg, &err);
>  *     if (err) { // don't do this
>  *         error_report_err(err);
>  *         exit(1);
>  *     }
> 
> Terminating the process is generally fine during initial startup,
> i.e. before the guest runs.
> 
> It's generally not fine once the guest runs.  Errors need to be handled
> more gracefully then.  A QMP command, for instance, should fail cleanly,
> propagating the error to the monitor core, which then sends it to the
> QMP client, and loops to process the next command.
> 
>>> It makes sense to me to propagate errors from *_realize() and
>>> error_abort on failure to set simple properties, but I'd like to know
>>> if Philippe is on board with that.
> 
> Realize methods must not use &error_fatal.  Instead, they should clean
> up and fail.
> 
> "Clean up" is the part we often neglect.  The big advantage of
> &error_fatal is that you don't have to bother :)
> 
> Questions?

One on my side. So in this realize(), all &error_abort uses has
to be replaced by local_err + propagate ...:

static void npcm7xx_realize(DeviceState *dev, Error **errp)
{
    NPCM7xxState *s = NPCM7XX(dev);
    NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
    int i;

    /* CPUs */
    for (i = 0; i < nc->num_cpus; i++) {
        object_property_set_int(OBJECT(&s->cpu[i]),
                                arm_cpu_mp_affinity(i,
NPCM7XX_MAX_NUM_CPUS),
                                "mp-affinity", &error_abort);
        object_property_set_int(OBJECT(&s->cpu[i]), NPCM7XX_GIC_CPU_IF_ADDR,
                                "reset-cbar", &error_abort);
        object_property_set_bool(OBJECT(&s->cpu[i]), true,
                                 "reset-hivecs", &error_abort);

        /* Disable security extensions. */
        object_property_set_bool(OBJECT(&s->cpu[i]), false, "has_el3",
                                 &error_abort);

        qdev_realize(DEVICE(&s->cpu[i]), NULL, &error_abort);
    }
    [...]

... but the caller does:

static void quanta_gsj_init(MachineState *machine)
{
    NPCM7xxState *soc;

    soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
    npcm7xx_connect_dram(soc, machine->ram);
    qdev_realize(DEVICE(soc), NULL, &error_abort);
                                    ^^^^^^^^^^^^
    npcm7xx_load_kernel(machine, soc);
}

So we overload the code...

My question: Do you confirm this is worth it to propagate?


  reply	other threads:[~2020-07-14 17:12 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-09  0:35 [PATCH v5 00/11] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
2020-07-09  0:35 ` [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model Havard Skinnemoen
2020-07-09  6:04   ` Philippe Mathieu-Daudé
2020-07-09  6:43     ` Havard Skinnemoen
2020-07-09 16:23       ` Philippe Mathieu-Daudé
2020-07-09 17:09         ` Havard Skinnemoen
2020-07-09 17:24           ` Philippe Mathieu-Daudé
2020-07-09 17:42             ` Havard Skinnemoen
2020-07-10  9:31               ` Philippe Mathieu-Daudé
2020-07-11  6:46                 ` Havard Skinnemoen
2020-07-12  5:49                   ` Havard Skinnemoen
2020-07-09  0:35 ` [PATCH v5 02/11] hw/misc: Add NPCM7xx Clock Controller " Havard Skinnemoen
2020-07-15  7:18   ` Philippe Mathieu-Daudé
2020-07-09  0:36 ` [PATCH v5 03/11] hw/timer: Add NPCM7xx Timer " Havard Skinnemoen
2020-07-15  7:25   ` Philippe Mathieu-Daudé
2020-07-15 23:04     ` Havard Skinnemoen
2020-07-16  8:04       ` Philippe Mathieu-Daudé
2020-07-09  0:36 ` [PATCH v5 04/11] hw/arm: Add NPCM730 and NPCM750 SoC models Havard Skinnemoen
2020-07-09  6:11   ` Philippe Mathieu-Daudé
2020-07-13 15:02   ` Cédric Le Goater
2020-07-14  0:44     ` Havard Skinnemoen
2020-07-14 11:37       ` Philippe Mathieu-Daudé
2020-07-14 16:01         ` Markus Armbruster
2020-07-14 17:11           ` Philippe Mathieu-Daudé [this message]
2020-07-15  1:03             ` Havard Skinnemoen
2020-07-15  9:35               ` Markus Armbruster
2020-07-09  0:36 ` [PATCH v5 05/11] hw/arm: Add two NPCM7xx-based machines Havard Skinnemoen
2020-07-09  5:57   ` Philippe Mathieu-Daudé
2020-07-09  6:09     ` Philippe Mathieu-Daudé
2020-07-09  0:36 ` [PATCH v5 06/11] hw/arm: Load -bios image as a boot ROM for npcm7xx Havard Skinnemoen
2020-07-13 17:50   ` Philippe Mathieu-Daudé
2020-07-09  0:36 ` [PATCH v5 07/11] hw/nvram: NPCM7xx OTP device model Havard Skinnemoen
2020-07-09  0:36 ` [PATCH v5 08/11] hw/mem: Stubbed out NPCM7xx Memory Controller model Havard Skinnemoen
2020-07-09 16:29   ` Philippe Mathieu-Daudé
2020-07-09  0:36 ` [PATCH v5 09/11] hw/ssi: NPCM7xx Flash Interface Unit device model Havard Skinnemoen
2020-07-09 17:00   ` Philippe Mathieu-Daudé
2020-07-12  5:42     ` Havard Skinnemoen
2020-07-13 17:38       ` Philippe Mathieu-Daudé
2020-07-14  2:39         ` Havard Skinnemoen
2020-07-09  0:36 ` [PATCH v5 10/11] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj Havard Skinnemoen
2020-07-13 14:57   ` Cédric Le Goater
2020-07-13 17:59     ` Philippe Mathieu-Daudé
2020-07-13 18:02       ` Philippe Mathieu-Daudé
2020-07-14  2:56     ` Havard Skinnemoen
2020-07-14  9:16       ` Markus Armbruster
2020-07-14 11:29         ` Philippe Mathieu-Daudé
2020-07-14 16:21           ` Markus Armbruster
2020-07-14 17:16             ` Philippe Mathieu-Daudé
2020-07-15  9:00               ` Markus Armbruster
2020-07-15 10:57                 ` Philippe Mathieu-Daudé
2020-07-15 20:54                   ` Havard Skinnemoen
2020-07-16 20:56                     ` Havard Skinnemoen
2020-07-17  7:48                       ` Philippe Mathieu-Daudé
2020-07-17  8:03                         ` Thomas Huth
2020-07-17  8:27                           ` Philippe Mathieu-Daudé
2020-07-17  9:00                             ` Philippe Mathieu-Daudé
2020-07-17 19:18                               ` Havard Skinnemoen
2020-07-17 20:21                                 ` Cédric Le Goater
2020-07-17 20:52                                 ` Philippe Mathieu-Daudé
2020-07-17 20:57                                   ` Havard Skinnemoen
2020-07-20  7:58                               ` Markus Armbruster
2020-07-15  7:42       ` Cédric Le Goater
2020-07-15 21:19         ` Havard Skinnemoen
2020-07-09  0:36 ` [PATCH v5 11/11] docs/system: Add Nuvoton machine documentation Havard Skinnemoen

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