[PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Joerg Roedel]

Hi,                                                                                                                              

here is the first release of patches for KVM to support the Nested Paging (NPT)
feature of AMD QuadCore CPUs for comments and public testing. This feature
improves the guest performance significantly. I measured an improvement of
around 17% using kernbench in my first tests.

This patch series is basically tested with Linux guests (32 bit legacy
paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with Windows Vista
32 bit and 64 bit. All these guests ran successfully with these patches. The
patch series only enables NPT for 64 bit Linux hosts at the moment.

Please give these patches a good and deep testing. I hope we have this patchset
ready for merging soon.

Joerg

Here is the diffstat:

 arch/x86/kvm/mmu.c         |   81 +++++++++++++++++++++++++++++++++++---
 arch/x86/kvm/mmu.h         |    6 +++
 arch/x86/kvm/svm.c         |   94 +++++++++++++++++++++++++++++++++++++++++--
 arch/x86/kvm/vmx.c         |    7 +++
 arch/x86/kvm/x86.c         |    1 +
 include/asm-x86/kvm_host.h |    4 ++
 6 files changed, 182 insertions(+), 11 deletions(-)

[PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Joerg Roedel]

Hi,                                                                                                                              

here is the first release of patches for KVM to support the Nested Paging (NPT)
feature of AMD QuadCore CPUs for comments and public testing. This feature
improves the guest performance significantly. I measured an improvement of
around 17% using kernbench in my first tests.

This patch series is basically tested with Linux guests (32 bit legacy
paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with Windows Vista
32 bit and 64 bit. All these guests ran successfully with these patches. The
patch series only enables NPT for 64 bit Linux hosts at the moment.

Please give these patches a good and deep testing. I hope we have this patchset
ready for merging soon.

Joerg

Here is the diffstat:

 arch/x86/kvm/mmu.c         |   81 +++++++++++++++++++++++++++++++++++---
 arch/x86/kvm/mmu.h         |    6 +++
 arch/x86/kvm/svm.c         |   94 +++++++++++++++++++++++++++++++++++++++++--
 arch/x86/kvm/vmx.c         |    7 +++
 arch/x86/kvm/x86.c         |    1 +
 include/asm-x86/kvm_host.h |    4 ++
 6 files changed, 182 insertions(+), 11 deletions(-)





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[PATCH 1/8] SVM: move feature detection to hardware setup code

[Joerg Roedel]

By moving the SVM feature detection from the each_cpu code to the hardware
setup code it runs only once. As an additional advance the feature check is now
available earlier in the module setup process.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kvm/svm.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 7bdbe16..0c58527 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -302,7 +302,6 @@ static void svm_hardware_enable(void *garbage)
 	svm_data->asid_generation = 1;
 	svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 	svm_data->next_asid = svm_data->max_asid + 1;
-	svm_features = cpuid_edx(SVM_CPUID_FUNC);
 
 	asm volatile ("sgdt %0" : "=m"(gdt_descr));
 	gdt = (struct desc_struct *)gdt_descr.address;
@@ -408,6 +407,9 @@ static __init int svm_hardware_setup(void)
 		if (r)
 			goto err_2;
 	}
+
+	svm_features = cpuid_edx(SVM_CPUID_FUNC);
+
 	return 0;
 
 err_2:
-- 
1.5.3.7

[PATCH 1/8] SVM: move feature detection to hardware setup code

[Joerg Roedel]

By moving the SVM feature detection from the each_cpu code to the hardware
setup code it runs only once. As an additional advance the feature check is now
available earlier in the module setup process.

Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
---
 arch/x86/kvm/svm.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 7bdbe16..0c58527 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -302,7 +302,6 @@ static void svm_hardware_enable(void *garbage)
 	svm_data->asid_generation = 1;
 	svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 	svm_data->next_asid = svm_data->max_asid + 1;
-	svm_features = cpuid_edx(SVM_CPUID_FUNC);
 
 	asm volatile ("sgdt %0" : "=m"(gdt_descr));
 	gdt = (struct desc_struct *)gdt_descr.address;
@@ -408,6 +407,9 @@ static __init int svm_hardware_setup(void)
 		if (r)
 			goto err_2;
 	}
+
+	svm_features = cpuid_edx(SVM_CPUID_FUNC);
+
 	return 0;
 
 err_2:
-- 
1.5.3.7




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[PATCH 2/8] SVM: add detection of Nested Paging feature

[Joerg Roedel]

Let SVM detect if the Nested Paging feature is available on the hardware.
Disable it to keep this patch series bisectable.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kvm/svm.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 0c58527..49bb57a 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -47,6 +47,8 @@ MODULE_LICENSE("GPL");
 #define SVM_FEATURE_LBRV (1 << 1)
 #define SVM_DEATURE_SVML (1 << 2)
 
+static bool npt_enabled = false;
+
 static void kvm_reput_irq(struct vcpu_svm *svm);
 
 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
@@ -410,6 +412,12 @@ static __init int svm_hardware_setup(void)
 
 	svm_features = cpuid_edx(SVM_CPUID_FUNC);
 
+	if (!svm_has(SVM_FEATURE_NPT))
+		npt_enabled = false;
+
+	if (npt_enabled)
+		printk(KERN_INFO "kvm: Nested Paging enabled\n");
+
 	return 0;
 
 err_2:
-- 
1.5.3.7

[PATCH 2/8] SVM: add detection of Nested Paging feature

[Joerg Roedel]

Let SVM detect if the Nested Paging feature is available on the hardware.
Disable it to keep this patch series bisectable.

Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
---
 arch/x86/kvm/svm.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 0c58527..49bb57a 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -47,6 +47,8 @@ MODULE_LICENSE("GPL");
 #define SVM_FEATURE_LBRV (1 << 1)
 #define SVM_DEATURE_SVML (1 << 2)
 
+static bool npt_enabled = false;
+
 static void kvm_reput_irq(struct vcpu_svm *svm);
 
 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
@@ -410,6 +412,12 @@ static __init int svm_hardware_setup(void)
 
 	svm_features = cpuid_edx(SVM_CPUID_FUNC);
 
+	if (!svm_has(SVM_FEATURE_NPT))
+		npt_enabled = false;
+
+	if (npt_enabled)
+		printk(KERN_INFO "kvm: Nested Paging enabled\n");
+
 	return 0;
 
 err_2:
-- 
1.5.3.7




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[PATCH 3/8] SVM: add module parameter to disable Nested Paging

[Joerg Roedel]

To disable the use of the Nested Paging feature even if it is available in
hardware this patch adds a module parameter. Nested Paging can be disabled by
passing npt=off to the kvm_amd module.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kvm/svm.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 49bb57a..2e718ff 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -48,6 +48,9 @@ MODULE_LICENSE("GPL");
 #define SVM_DEATURE_SVML (1 << 2)
 
 static bool npt_enabled = false;
+static char *npt = "on";
+
+module_param(npt, charp, S_IRUGO);
 
 static void kvm_reput_irq(struct vcpu_svm *svm);
 
@@ -415,6 +418,11 @@ static __init int svm_hardware_setup(void)
 	if (!svm_has(SVM_FEATURE_NPT))
 		npt_enabled = false;
 
+	if (npt_enabled && strncmp(npt, "off", 3) == 0) {
+		printk(KERN_INFO "kvm: Nested Paging disabled\n");
+		npt_enabled = false;
+	}
+
 	if (npt_enabled)
 		printk(KERN_INFO "kvm: Nested Paging enabled\n");
 
-- 
1.5.3.7

Re: [kvm-devel] [PATCH 3/8] SVM: add module parameter to disable Nested Paging

[Anthony Liguori]

Joerg Roedel wrote:
> To disable the use of the Nested Paging feature even if it is available in
> hardware this patch adds a module parameter. Nested Paging can be disabled by
> passing npt=off to the kvm_amd module.
>
> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
> ---
>  arch/x86/kvm/svm.c |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index 49bb57a..2e718ff 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -48,6 +48,9 @@ MODULE_LICENSE("GPL");
>  #define SVM_DEATURE_SVML (1 << 2)
>  
>  static bool npt_enabled = false;
> +static char *npt = "on";
> +
> +module_param(npt, charp, S_IRUGO);
>   

This would probably be better as an integer.  Then we don't have to do 
nasty things like implicitly cast a literal to a char *.

Regards,

Anthony Liguori

>  static void kvm_reput_irq(struct vcpu_svm *svm);
>  
> @@ -415,6 +418,11 @@ static __init int svm_hardware_setup(void)
>  	if (!svm_has(SVM_FEATURE_NPT))
>  		npt_enabled = false;
>  
> +	if (npt_enabled && strncmp(npt, "off", 3) == 0) {
> +		printk(KERN_INFO "kvm: Nested Paging disabled\n");
> +		npt_enabled = false;
> +	}
> +
>  	if (npt_enabled)
>  		printk(KERN_INFO "kvm: Nested Paging enabled\n");
>  
>   

Re: [PATCH 3/8] SVM: add module parameter to disable Nested Paging

[Anthony Liguori]

Joerg Roedel wrote:
> To disable the use of the Nested Paging feature even if it is available in
> hardware this patch adds a module parameter. Nested Paging can be disabled by
> passing npt=off to the kvm_amd module.
>
> Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
> ---
>  arch/x86/kvm/svm.c |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index 49bb57a..2e718ff 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -48,6 +48,9 @@ MODULE_LICENSE("GPL");
>  #define SVM_DEATURE_SVML (1 << 2)
>  
>  static bool npt_enabled = false;
> +static char *npt = "on";
> +
> +module_param(npt, charp, S_IRUGO);
>   

This would probably be better as an integer.  Then we don't have to do 
nasty things like implicitly cast a literal to a char *.

Regards,

Anthony Liguori

>  static void kvm_reput_irq(struct vcpu_svm *svm);
>  
> @@ -415,6 +418,11 @@ static __init int svm_hardware_setup(void)
>  	if (!svm_has(SVM_FEATURE_NPT))
>  		npt_enabled = false;
>  
> +	if (npt_enabled && strncmp(npt, "off", 3) == 0) {
> +		printk(KERN_INFO "kvm: Nested Paging disabled\n");
> +		npt_enabled = false;
> +	}
> +
>  	if (npt_enabled)
>  		printk(KERN_INFO "kvm: Nested Paging enabled\n");
>  
>   


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Re: [kvm-devel] [PATCH 3/8] SVM: add module parameter to disable Nested Paging

[Joerg Roedel]

On Fri, Jan 25, 2008 at 03:35:23PM -0600, Anthony Liguori wrote:
> Joerg Roedel wrote:
> >To disable the use of the Nested Paging feature even if it is available in
> >hardware this patch adds a module parameter. Nested Paging can be disabled by
> >passing npt=off to the kvm_amd module.
> >
> >Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
> >---
> > arch/x86/kvm/svm.c |    8 ++++++++
> > 1 files changed, 8 insertions(+), 0 deletions(-)
> >
> >diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> >index 49bb57a..2e718ff 100644
> >--- a/arch/x86/kvm/svm.c
> >+++ b/arch/x86/kvm/svm.c
> >@@ -48,6 +48,9 @@ MODULE_LICENSE("GPL");
> > #define SVM_DEATURE_SVML (1 << 2)
> >  static bool npt_enabled = false;
> >+static char *npt = "on";
> >+
> >+module_param(npt, charp, S_IRUGO);
> >  
> 
> This would probably be better as an integer.  Then we don't have to do nasty things like 
> implicitly cast a literal to a char *.

Hmm, I used int for that first but typing npt=off seemed more
userfriendly to me than npt=0. So I used char* for it.

Joerg

-- 
           |           AMD Saxony Limited Liability Company & Co. KG
 Operating |         Wilschdorfer Landstr. 101, 01109 Dresden, Germany
 System    |                  Register Court Dresden: HRA 4896
 Research  |              General Partner authorized to represent:
 Center    |             AMD Saxony LLC (Wilmington, Delaware, US)
           | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy

Re: [PATCH 3/8] SVM: add module parameter to disable Nested Paging

[Joerg Roedel]

On Fri, Jan 25, 2008 at 03:35:23PM -0600, Anthony Liguori wrote:
> Joerg Roedel wrote:
> >To disable the use of the Nested Paging feature even if it is available in
> >hardware this patch adds a module parameter. Nested Paging can be disabled by
> >passing npt=off to the kvm_amd module.
> >
> >Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
> >---
> > arch/x86/kvm/svm.c |    8 ++++++++
> > 1 files changed, 8 insertions(+), 0 deletions(-)
> >
> >diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> >index 49bb57a..2e718ff 100644
> >--- a/arch/x86/kvm/svm.c
> >+++ b/arch/x86/kvm/svm.c
> >@@ -48,6 +48,9 @@ MODULE_LICENSE("GPL");
> > #define SVM_DEATURE_SVML (1 << 2)
> >  static bool npt_enabled = false;
> >+static char *npt = "on";
> >+
> >+module_param(npt, charp, S_IRUGO);
> >  
> 
> This would probably be better as an integer.  Then we don't have to do nasty things like 
> implicitly cast a literal to a char *.

Hmm, I used int for that first but typing npt=off seemed more
userfriendly to me than npt=0. So I used char* for it.

Joerg

-- 
           |           AMD Saxony Limited Liability Company & Co. KG
 Operating |         Wilschdorfer Landstr. 101, 01109 Dresden, Germany
 System    |                  Register Court Dresden: HRA 4896
 Research  |              General Partner authorized to represent:
 Center    |             AMD Saxony LLC (Wilmington, Delaware, US)
           | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy



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Re: [kvm-devel] [PATCH 3/8] SVM: add module parameter to disable Nested Paging

[Avi Kivity]

Joerg Roedel wrote:
>>> +static char *npt = "on";
>>> +
>>> +module_param(npt, charp, S_IRUGO);
>>>  
>>>       
>> This would probably be better as an integer.  Then we don't have to do nasty things like 
>> implicitly cast a literal to a char *.
>>     
>
> Hmm, I used int for that first but typing npt=off seemed more
> userfriendly to me than npt=0. So I used char* for it.
>   

I expect this to be rarely used by users, so the simpler int is 
preferable (and also consistent with vmx's bypass_guest_pf and enable_vpid).

-- 
Any sufficiently difficult bug is indistinguishable from a feature.

Re: [PATCH 3/8] SVM: add module parameter to disable Nested Paging

[Avi Kivity]

Joerg Roedel wrote:
>>> +static char *npt = "on";
>>> +
>>> +module_param(npt, charp, S_IRUGO);
>>>  
>>>       
>> This would probably be better as an integer.  Then we don't have to do nasty things like 
>> implicitly cast a literal to a char *.
>>     
>
> Hmm, I used int for that first but typing npt=off seemed more
> userfriendly to me than npt=0. So I used char* for it.
>   

I expect this to be rarely used by users, so the simpler int is 
preferable (and also consistent with vmx's bypass_guest_pf and enable_vpid).

-- 
Any sufficiently difficult bug is indistinguishable from a feature.


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RE: [kvm-devel] [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Nakajima, Jun]

Joerg Roedel wrote:
> To disable the use of the Nested Paging feature even if it is
available in
> hardware this patch adds a module parameter. Nested Paging can be
disabled by
> passing npt=off to the kvm_amd module.

I think it's better to use a (common) parameter to qemu. That way you
can control on/off for each VM.

Jun
---
Intel Open Source Technology Center

Re: [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Nakajima, Jun]

Joerg Roedel wrote:
> To disable the use of the Nested Paging feature even if it is
available in
> hardware this patch adds a module parameter. Nested Paging can be
disabled by
> passing npt=off to the kvm_amd module.

I think it's better to use a (common) parameter to qemu. That way you
can control on/off for each VM.

Jun
---
Intel Open Source Technology Center

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Re: [kvm-devel] [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Joerg Roedel]

On Fri, Jan 25, 2008 at 05:47:11PM -0800, Nakajima, Jun wrote:
> Joerg Roedel wrote:
> > To disable the use of the Nested Paging feature even if it is
> available in
> > hardware this patch adds a module parameter. Nested Paging can be
> disabled by
> > passing npt=off to the kvm_amd module.
> 
> I think it's better to use a (common) parameter to qemu. That way you
> can control on/off for each VM.

Generally I see no problem with it. But at least for NPT I don't see a
reason why someone should want to disable it on a VM basis (as far as it
works stable). Avi, what do you think?

Joerg

Re: [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Joerg Roedel]

On Fri, Jan 25, 2008 at 05:47:11PM -0800, Nakajima, Jun wrote:
> Joerg Roedel wrote:
> > To disable the use of the Nested Paging feature even if it is
> available in
> > hardware this patch adds a module parameter. Nested Paging can be
> disabled by
> > passing npt=off to the kvm_amd module.
> 
> I think it's better to use a (common) parameter to qemu. That way you
> can control on/off for each VM.

Generally I see no problem with it. But at least for NPT I don't see a
reason why someone should want to disable it on a VM basis (as far as it
works stable). Avi, what do you think?

Joerg

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Re: [kvm-devel] [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Alexey Eremenko]

> Generally I see no problem with it. But at least for NPT I don't see a
> reason why someone should want to disable it on a VM basis (as far as it
> works stable). Avi, what do you think?
>

1. This is more user-friendly and easier-to-find

2. A lot of people would like to view (and Demo) it side-by-side.

3. Useful for BETA-testing of KVM.

-- 
-Alexey Eremenko "Technologov"

Re: [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Alexey Eremenko]

> Generally I see no problem with it. But at least for NPT I don't see a
> reason why someone should want to disable it on a VM basis (as far as it
> works stable). Avi, what do you think?
>

1. This is more user-friendly and easier-to-find

2. A lot of people would like to view (and Demo) it side-by-side.

3. Useful for BETA-testing of KVM.

-- 
-Alexey Eremenko "Technologov"

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Re: [kvm-devel] [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Joerg Roedel]

On Sat, Jan 26, 2008 at 11:49:17AM +0200, Alexey Eremenko wrote:
> > Generally I see no problem with it. But at least for NPT I don't see a
> > reason why someone should want to disable it on a VM basis (as far as it
> > works stable). Avi, what do you think?
> >
> 
> 1. This is more user-friendly and easier-to-find
> 
> 2. A lot of people would like to view (and Demo) it side-by-side.
> 
> 3. Useful for BETA-testing of KVM.

Ok, agreed. I will add this feature.

Joerg

Re: [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Joerg Roedel]

On Sat, Jan 26, 2008 at 11:49:17AM +0200, Alexey Eremenko wrote:
> > Generally I see no problem with it. But at least for NPT I don't see a
> > reason why someone should want to disable it on a VM basis (as far as it
> > works stable). Avi, what do you think?
> >
> 
> 1. This is more user-friendly and easier-to-find
> 
> 2. A lot of people would like to view (and Demo) it side-by-side.
> 
> 3. Useful for BETA-testing of KVM.

Ok, agreed. I will add this feature.

Joerg

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Re: [kvm-devel] [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Anthony Liguori]

Alexey Eremenko wrote:
>> Generally I see no problem with it. But at least for NPT I don't see a
>> reason why someone should want to disable it on a VM basis (as far as it
>> works stable). Avi, what do you think?
>>
>>     
>
> 1. This is more user-friendly and easier-to-find
>   

I'm inclined to disagree.  Why add an additional thing for people to 
tune if they really shouldn't need to.  Once NPT/EPT support are stable, 
is there any reason to want to disable it?

Regards,

Anthony Liguori

> 2. A lot of people would like to view (and Demo) it side-by-side.
>
> 3. Useful for BETA-testing of KVM.
>
>   

Re: [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Anthony Liguori]

Alexey Eremenko wrote:
>> Generally I see no problem with it. But at least for NPT I don't see a
>> reason why someone should want to disable it on a VM basis (as far as it
>> works stable). Avi, what do you think?
>>
>>     
>
> 1. This is more user-friendly and easier-to-find
>   

I'm inclined to disagree.  Why add an additional thing for people to 
tune if they really shouldn't need to.  Once NPT/EPT support are stable, 
is there any reason to want to disable it?

Regards,

Anthony Liguori

> 2. A lot of people would like to view (and Demo) it side-by-side.
>
> 3. Useful for BETA-testing of KVM.
>
>   


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Re: [kvm-devel] [PATCH 3/8] SVM: add module parameter to disable NestedPaging

[Avi Kivity]

Joerg Roedel wrote:
> Generally I see no problem with it. But at least for NPT I don't see a
> reason why someone should want to disable it on a VM basis (as far as it
> works stable). Avi, what do you think?
>   

Unless there is a real-life workload that benefits from npt=0, I see no 
reason to have per-vm npt control.  The module parameter is helpful, for 
to isolate npt problems and for development, but I don't see a need for 
users to fiddle with it.

-- 
Any sufficiently difficult bug is indistinguishable from a feature.

[PATCH 4/8] X86: export information about NPT to generic x86 code

[Joerg Roedel]

The generic x86 code has to know if the specific implementation uses Nested
Paging. In the generic code Nested Paging is called Hardware Assisted Paging
(HAP) to avoid confusion with (future) HAP implementations of other vendors.
This patch exports the availability of HAP to the generic x86 code.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kvm/svm.c         |    7 +++++++
 arch/x86/kvm/vmx.c         |    7 +++++++
 include/asm-x86/kvm_host.h |    2 ++
 3 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 2e718ff..d0bfdd8 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1678,6 +1678,11 @@ static bool svm_cpu_has_accelerated_tpr(void)
 	return false;
 }
 
+static bool svm_hap_enabled(void)
+{
+	return npt_enabled;
+}
+
 static struct kvm_x86_ops svm_x86_ops = {
 	.cpu_has_kvm_support = has_svm,
 	.disabled_by_bios = is_disabled,
@@ -1734,6 +1739,8 @@ static struct kvm_x86_ops svm_x86_ops = {
 	.inject_pending_vectors = do_interrupt_requests,
 
 	.set_tss_addr = svm_set_tss_addr,
+
+	.hap_enabled = svm_hap_enabled,
 };
 
 static int __init svm_init(void)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 00a00e4..8feb775 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2631,6 +2631,11 @@ static void __init vmx_check_processor_compat(void *rtn)
 	}
 }
 
+static bool vmx_hap_enabled(void)
+{
+	return false;
+}
+
 static struct kvm_x86_ops vmx_x86_ops = {
 	.cpu_has_kvm_support = cpu_has_kvm_support,
 	.disabled_by_bios = vmx_disabled_by_bios,
@@ -2688,6 +2693,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
 	.inject_pending_vectors = do_interrupt_requests,
 
 	.set_tss_addr = vmx_set_tss_addr,
+
+	.hap_enabled = vmx_hap_enabled,
 };
 
 static int __init vmx_init(void)
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 67ae307..45a9d05 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -392,6 +392,8 @@ struct kvm_x86_ops {
 				       struct kvm_run *run);
 
 	int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
+
+	bool (*hap_enabled)(void);
 };
 
 extern struct kvm_x86_ops *kvm_x86_ops;
-- 
1.5.3.7

[PATCH 4/8] X86: export information about NPT to generic x86 code

[Joerg Roedel]

The generic x86 code has to know if the specific implementation uses Nested
Paging. In the generic code Nested Paging is called Hardware Assisted Paging
(HAP) to avoid confusion with (future) HAP implementations of other vendors.
This patch exports the availability of HAP to the generic x86 code.

Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
---
 arch/x86/kvm/svm.c         |    7 +++++++
 arch/x86/kvm/vmx.c         |    7 +++++++
 include/asm-x86/kvm_host.h |    2 ++
 3 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 2e718ff..d0bfdd8 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1678,6 +1678,11 @@ static bool svm_cpu_has_accelerated_tpr(void)
 	return false;
 }
 
+static bool svm_hap_enabled(void)
+{
+	return npt_enabled;
+}
+
 static struct kvm_x86_ops svm_x86_ops = {
 	.cpu_has_kvm_support = has_svm,
 	.disabled_by_bios = is_disabled,
@@ -1734,6 +1739,8 @@ static struct kvm_x86_ops svm_x86_ops = {
 	.inject_pending_vectors = do_interrupt_requests,
 
 	.set_tss_addr = svm_set_tss_addr,
+
+	.hap_enabled = svm_hap_enabled,
 };
 
 static int __init svm_init(void)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 00a00e4..8feb775 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2631,6 +2631,11 @@ static void __init vmx_check_processor_compat(void *rtn)
 	}
 }
 
+static bool vmx_hap_enabled(void)
+{
+	return false;
+}
+
 static struct kvm_x86_ops vmx_x86_ops = {
 	.cpu_has_kvm_support = cpu_has_kvm_support,
 	.disabled_by_bios = vmx_disabled_by_bios,
@@ -2688,6 +2693,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
 	.inject_pending_vectors = do_interrupt_requests,
 
 	.set_tss_addr = vmx_set_tss_addr,
+
+	.hap_enabled = vmx_hap_enabled,
 };
 
 static int __init vmx_init(void)
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 67ae307..45a9d05 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -392,6 +392,8 @@ struct kvm_x86_ops {
 				       struct kvm_run *run);
 
 	int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
+
+	bool (*hap_enabled)(void);
 };
 
 extern struct kvm_x86_ops *kvm_x86_ops;
-- 
1.5.3.7




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Re: [kvm-devel] [PATCH 4/8] X86: export information about NPT to generic x86 code

[Anthony Liguori]

Joerg Roedel wrote:
> The generic x86 code has to know if the specific implementation uses Nested
> Paging. In the generic code Nested Paging is called Hardware Assisted Paging
> (HAP) to avoid confusion with (future) HAP implementations of other vendors.
> This patch exports the availability of HAP to the generic x86 code.
>
> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
> ---
>  arch/x86/kvm/svm.c         |    7 +++++++
>  arch/x86/kvm/vmx.c         |    7 +++++++
>  include/asm-x86/kvm_host.h |    2 ++
>  3 files changed, 16 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index 2e718ff..d0bfdd8 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -1678,6 +1678,11 @@ static bool svm_cpu_has_accelerated_tpr(void)
>  	return false;
>  }
>  
> +static bool svm_hap_enabled(void)
> +{
> +	return npt_enabled;
> +}
> +
>   

To help with bisecting, you should probably return false here until the 
patch that actually implements NPT support.  Otherwise, the 7th patch in 
this series breaks KVM for SVM.

Regards,

Anthony Liguori

>  static struct kvm_x86_ops svm_x86_ops = {
>  	.cpu_has_kvm_support = has_svm,
>  	.disabled_by_bios = is_disabled,
> @@ -1734,6 +1739,8 @@ static struct kvm_x86_ops svm_x86_ops = {
>  	.inject_pending_vectors = do_interrupt_requests,
>  
>  	.set_tss_addr = svm_set_tss_addr,
> +
> +	.hap_enabled = svm_hap_enabled,
>  };
>  
>  static int __init svm_init(void)
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 00a00e4..8feb775 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -2631,6 +2631,11 @@ static void __init vmx_check_processor_compat(void *rtn)
>  	}
>  }
>  
> +static bool vmx_hap_enabled(void)
> +{
> +	return false;
> +}
> +
>  static struct kvm_x86_ops vmx_x86_ops = {
>  	.cpu_has_kvm_support = cpu_has_kvm_support,
>  	.disabled_by_bios = vmx_disabled_by_bios,
> @@ -2688,6 +2693,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
>  	.inject_pending_vectors = do_interrupt_requests,
>  
>  	.set_tss_addr = vmx_set_tss_addr,
> +
> +	.hap_enabled = vmx_hap_enabled,
>  };
>  
>  static int __init vmx_init(void)
> diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
> index 67ae307..45a9d05 100644
> --- a/include/asm-x86/kvm_host.h
> +++ b/include/asm-x86/kvm_host.h
> @@ -392,6 +392,8 @@ struct kvm_x86_ops {
>  				       struct kvm_run *run);
>  
>  	int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
> +
> +	bool (*hap_enabled)(void);
>  };
>  
>  extern struct kvm_x86_ops *kvm_x86_ops;
>   

Re: [PATCH 4/8] X86: export information about NPT to generic x86 code

[Anthony Liguori]

Joerg Roedel wrote:
> The generic x86 code has to know if the specific implementation uses Nested
> Paging. In the generic code Nested Paging is called Hardware Assisted Paging
> (HAP) to avoid confusion with (future) HAP implementations of other vendors.
> This patch exports the availability of HAP to the generic x86 code.
>
> Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
> ---
>  arch/x86/kvm/svm.c         |    7 +++++++
>  arch/x86/kvm/vmx.c         |    7 +++++++
>  include/asm-x86/kvm_host.h |    2 ++
>  3 files changed, 16 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index 2e718ff..d0bfdd8 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -1678,6 +1678,11 @@ static bool svm_cpu_has_accelerated_tpr(void)
>  	return false;
>  }
>  
> +static bool svm_hap_enabled(void)
> +{
> +	return npt_enabled;
> +}
> +
>   

To help with bisecting, you should probably return false here until the 
patch that actually implements NPT support.  Otherwise, the 7th patch in 
this series breaks KVM for SVM.

Regards,

Anthony Liguori

>  static struct kvm_x86_ops svm_x86_ops = {
>  	.cpu_has_kvm_support = has_svm,
>  	.disabled_by_bios = is_disabled,
> @@ -1734,6 +1739,8 @@ static struct kvm_x86_ops svm_x86_ops = {
>  	.inject_pending_vectors = do_interrupt_requests,
>  
>  	.set_tss_addr = svm_set_tss_addr,
> +
> +	.hap_enabled = svm_hap_enabled,
>  };
>  
>  static int __init svm_init(void)
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 00a00e4..8feb775 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -2631,6 +2631,11 @@ static void __init vmx_check_processor_compat(void *rtn)
>  	}
>  }
>  
> +static bool vmx_hap_enabled(void)
> +{
> +	return false;
> +}
> +
>  static struct kvm_x86_ops vmx_x86_ops = {
>  	.cpu_has_kvm_support = cpu_has_kvm_support,
>  	.disabled_by_bios = vmx_disabled_by_bios,
> @@ -2688,6 +2693,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
>  	.inject_pending_vectors = do_interrupt_requests,
>  
>  	.set_tss_addr = vmx_set_tss_addr,
> +
> +	.hap_enabled = vmx_hap_enabled,
>  };
>  
>  static int __init vmx_init(void)
> diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
> index 67ae307..45a9d05 100644
> --- a/include/asm-x86/kvm_host.h
> +++ b/include/asm-x86/kvm_host.h
> @@ -392,6 +392,8 @@ struct kvm_x86_ops {
>  				       struct kvm_run *run);
>  
>  	int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
> +
> +	bool (*hap_enabled)(void);
>  };
>  
>  extern struct kvm_x86_ops *kvm_x86_ops;
>   


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Re: [kvm-devel] [PATCH 4/8] X86: export information about NPT to generic x86 code

[Anthony Liguori]

Anthony Liguori wrote:
> Joerg Roedel wrote:
>> The generic x86 code has to know if the specific implementation uses 
>> Nested
>> Paging. In the generic code Nested Paging is called Hardware Assisted 
>> Paging
>> (HAP) to avoid confusion with (future) HAP implementations of other 
>> vendors.
>> This patch exports the availability of HAP to the generic x86 code.
>>
>> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
>> ---
>>  arch/x86/kvm/svm.c         |    7 +++++++
>>  arch/x86/kvm/vmx.c         |    7 +++++++
>>  include/asm-x86/kvm_host.h |    2 ++
>>  3 files changed, 16 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
>> index 2e718ff..d0bfdd8 100644
>> --- a/arch/x86/kvm/svm.c
>> +++ b/arch/x86/kvm/svm.c
>> @@ -1678,6 +1678,11 @@ static bool svm_cpu_has_accelerated_tpr(void)
>>      return false;
>>  }
>>  
>> +static bool svm_hap_enabled(void)
>> +{
>> +    return npt_enabled;
>> +}
>> +
>>   
>
> To help with bisecting, you should probably return false here until 
> the patch that actually implements NPT support.  Otherwise, the 7th 
> patch in this series breaks KVM for SVM.

Ignore this, you're already doing the right thing :-)

Regards,

Anthony Liguori

> Regards,
>
> Anthony Liguori
>
>>  static struct kvm_x86_ops svm_x86_ops = {
>>      .cpu_has_kvm_support = has_svm,
>>      .disabled_by_bios = is_disabled,
>> @@ -1734,6 +1739,8 @@ static struct kvm_x86_ops svm_x86_ops = {
>>      .inject_pending_vectors = do_interrupt_requests,
>>  
>>      .set_tss_addr = svm_set_tss_addr,
>> +
>> +    .hap_enabled = svm_hap_enabled,
>>  };
>>  
>>  static int __init svm_init(void)
>> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>> index 00a00e4..8feb775 100644
>> --- a/arch/x86/kvm/vmx.c
>> +++ b/arch/x86/kvm/vmx.c
>> @@ -2631,6 +2631,11 @@ static void __init 
>> vmx_check_processor_compat(void *rtn)
>>      }
>>  }
>>  
>> +static bool vmx_hap_enabled(void)
>> +{
>> +    return false;
>> +}
>> +
>>  static struct kvm_x86_ops vmx_x86_ops = {
>>      .cpu_has_kvm_support = cpu_has_kvm_support,
>>      .disabled_by_bios = vmx_disabled_by_bios,
>> @@ -2688,6 +2693,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
>>      .inject_pending_vectors = do_interrupt_requests,
>>  
>>      .set_tss_addr = vmx_set_tss_addr,
>> +
>> +    .hap_enabled = vmx_hap_enabled,
>>  };
>>  
>>  static int __init vmx_init(void)
>> diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
>> index 67ae307..45a9d05 100644
>> --- a/include/asm-x86/kvm_host.h
>> +++ b/include/asm-x86/kvm_host.h
>> @@ -392,6 +392,8 @@ struct kvm_x86_ops {
>>                         struct kvm_run *run);
>>  
>>      int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
>> +
>> +    bool (*hap_enabled)(void);
>>  };
>>  
>>  extern struct kvm_x86_ops *kvm_x86_ops;
>>   
>

Re: [PATCH 4/8] X86: export information about NPT to generic x86 code

[Anthony Liguori]

Anthony Liguori wrote:
> Joerg Roedel wrote:
>> The generic x86 code has to know if the specific implementation uses 
>> Nested
>> Paging. In the generic code Nested Paging is called Hardware Assisted 
>> Paging
>> (HAP) to avoid confusion with (future) HAP implementations of other 
>> vendors.
>> This patch exports the availability of HAP to the generic x86 code.
>>
>> Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
>> ---
>>  arch/x86/kvm/svm.c         |    7 +++++++
>>  arch/x86/kvm/vmx.c         |    7 +++++++
>>  include/asm-x86/kvm_host.h |    2 ++
>>  3 files changed, 16 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
>> index 2e718ff..d0bfdd8 100644
>> --- a/arch/x86/kvm/svm.c
>> +++ b/arch/x86/kvm/svm.c
>> @@ -1678,6 +1678,11 @@ static bool svm_cpu_has_accelerated_tpr(void)
>>      return false;
>>  }
>>  
>> +static bool svm_hap_enabled(void)
>> +{
>> +    return npt_enabled;
>> +}
>> +
>>   
>
> To help with bisecting, you should probably return false here until 
> the patch that actually implements NPT support.  Otherwise, the 7th 
> patch in this series breaks KVM for SVM.

Ignore this, you're already doing the right thing :-)

Regards,

Anthony Liguori

> Regards,
>
> Anthony Liguori
>
>>  static struct kvm_x86_ops svm_x86_ops = {
>>      .cpu_has_kvm_support = has_svm,
>>      .disabled_by_bios = is_disabled,
>> @@ -1734,6 +1739,8 @@ static struct kvm_x86_ops svm_x86_ops = {
>>      .inject_pending_vectors = do_interrupt_requests,
>>  
>>      .set_tss_addr = svm_set_tss_addr,
>> +
>> +    .hap_enabled = svm_hap_enabled,
>>  };
>>  
>>  static int __init svm_init(void)
>> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>> index 00a00e4..8feb775 100644
>> --- a/arch/x86/kvm/vmx.c
>> +++ b/arch/x86/kvm/vmx.c
>> @@ -2631,6 +2631,11 @@ static void __init 
>> vmx_check_processor_compat(void *rtn)
>>      }
>>  }
>>  
>> +static bool vmx_hap_enabled(void)
>> +{
>> +    return false;
>> +}
>> +
>>  static struct kvm_x86_ops vmx_x86_ops = {
>>      .cpu_has_kvm_support = cpu_has_kvm_support,
>>      .disabled_by_bios = vmx_disabled_by_bios,
>> @@ -2688,6 +2693,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
>>      .inject_pending_vectors = do_interrupt_requests,
>>  
>>      .set_tss_addr = vmx_set_tss_addr,
>> +
>> +    .hap_enabled = vmx_hap_enabled,
>>  };
>>  
>>  static int __init vmx_init(void)
>> diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
>> index 67ae307..45a9d05 100644
>> --- a/include/asm-x86/kvm_host.h
>> +++ b/include/asm-x86/kvm_host.h
>> @@ -392,6 +392,8 @@ struct kvm_x86_ops {
>>                         struct kvm_run *run);
>>  
>>      int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
>> +
>> +    bool (*hap_enabled)(void);
>>  };
>>  
>>  extern struct kvm_x86_ops *kvm_x86_ops;
>>   
>


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Re: [kvm-devel] [PATCH 4/8] X86: export information about NPT to generic x86 code

[Avi Kivity]

Joerg Roedel wrote:
> The generic x86 code has to know if the specific implementation uses Nested
> Paging. In the generic code Nested Paging is called Hardware Assisted Paging
> (HAP) to avoid confusion with (future) HAP implementations of other vendors.
> This patch exports the availability of HAP to the generic x86 code.
>
>  	int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
> +
> +	bool (*hap_enabled)(void);
>  };
>  
>   

Since the value doesn't change during the lifetime of the VM, it can be 
a data field instead of a function.  Or, if we find that npt/ept is 
always a win, a static field in mmu.c.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 4/8] X86: export information about NPT to generic x86 code

[Avi Kivity]

Joerg Roedel wrote:
> The generic x86 code has to know if the specific implementation uses Nested
> Paging. In the generic code Nested Paging is called Hardware Assisted Paging
> (HAP) to avoid confusion with (future) HAP implementations of other vendors.
> This patch exports the availability of HAP to the generic x86 code.
>
>  	int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
> +
> +	bool (*hap_enabled)(void);
>  };
>  
>   

Since the value doesn't change during the lifetime of the VM, it can be 
a data field instead of a function.  Or, if we find that npt/ept is 
always a win, a static field in mmu.c.

-- 
error compiling committee.c: too many arguments to function


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[PATCH 5/8] MMU: make the __nonpaging_map function generic

[Joerg Roedel]

The mapping function for the nonpaging case in the softmmu does basically the
same as required for Nested Paging. Make this function generic so it can be
used for both.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kvm/mmu.c |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 635e70c..dfbcf5e 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -956,10 +956,9 @@ static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
 {
 }
 
-static int __nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write,
-			   gfn_t gfn, struct page *page)
+static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
+			   gfn_t gfn, struct page *page, int level)
 {
-	int level = PT32E_ROOT_LEVEL;
 	hpa_t table_addr = vcpu->arch.mmu.root_hpa;
 	int pt_write = 0;
 
@@ -1017,7 +1016,7 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
 
 	spin_lock(&vcpu->kvm->mmu_lock);
 	kvm_mmu_free_some_pages(vcpu);
-	r = __nonpaging_map(vcpu, v, write, gfn, page);
+	r = __direct_map(vcpu, v, write, gfn, page, PT32E_ROOT_LEVEL);
 	spin_unlock(&vcpu->kvm->mmu_lock);
 
 	up_read(&current->mm->mmap_sem);
-- 
1.5.3.7

[PATCH 5/8] MMU: make the __nonpaging_map function generic

[Joerg Roedel]

The mapping function for the nonpaging case in the softmmu does basically the
same as required for Nested Paging. Make this function generic so it can be
used for both.

Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
---
 arch/x86/kvm/mmu.c |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 635e70c..dfbcf5e 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -956,10 +956,9 @@ static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
 {
 }
 
-static int __nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write,
-			   gfn_t gfn, struct page *page)
+static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
+			   gfn_t gfn, struct page *page, int level)
 {
-	int level = PT32E_ROOT_LEVEL;
 	hpa_t table_addr = vcpu->arch.mmu.root_hpa;
 	int pt_write = 0;
 
@@ -1017,7 +1016,7 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
 
 	spin_lock(&vcpu->kvm->mmu_lock);
 	kvm_mmu_free_some_pages(vcpu);
-	r = __nonpaging_map(vcpu, v, write, gfn, page);
+	r = __direct_map(vcpu, v, write, gfn, page, PT32E_ROOT_LEVEL);
 	spin_unlock(&vcpu->kvm->mmu_lock);
 
 	up_read(&current->mm->mmap_sem);
-- 
1.5.3.7




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[PATCH 6/8] X86: export the load_pdptrs() function to modules

[Joerg Roedel]

The load_pdptrs() function is required in the SVM module for NPT support.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kvm/x86.c         |    1 +
 include/asm-x86/kvm_host.h |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 8f94a0b..31cdf09 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -202,6 +202,7 @@ out:
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(load_pdptrs);
 
 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
 {
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 45a9d05..b55a7a6 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -412,6 +412,8 @@ void kvm_mmu_zap_all(struct kvm *kvm);
 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
 
+int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3);
+
 enum emulation_result {
 	EMULATE_DONE,       /* no further processing */
 	EMULATE_DO_MMIO,      /* kvm_run filled with mmio request */
-- 
1.5.3.7

[PATCH 6/8] X86: export the load_pdptrs() function to modules

[Joerg Roedel]

The load_pdptrs() function is required in the SVM module for NPT support.

Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
---
 arch/x86/kvm/x86.c         |    1 +
 include/asm-x86/kvm_host.h |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 8f94a0b..31cdf09 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -202,6 +202,7 @@ out:
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(load_pdptrs);
 
 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
 {
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 45a9d05..b55a7a6 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -412,6 +412,8 @@ void kvm_mmu_zap_all(struct kvm *kvm);
 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
 
+int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3);
+
 enum emulation_result {
 	EMULATE_DONE,       /* no further processing */
 	EMULATE_DO_MMIO,      /* kvm_run filled with mmio request */
-- 
1.5.3.7




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[PATCH 7/8] MMU: add HAP support to the KVM MMU

[Joerg Roedel]

This patch contains the changes to the KVM MMU necessary for support of the
Nested Paging feature in AMD Barcelona and Phenom Processors.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kvm/mmu.c |   74 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 arch/x86/kvm/mmu.h |    6 ++++
 2 files changed, 78 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index dfbcf5e..bce27ca 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -1072,6 +1072,7 @@ static void mmu_alloc_roots(struct kvm_vcpu *vcpu)
 	int i;
 	gfn_t root_gfn;
 	struct kvm_mmu_page *sp;
+	int metaphysical = 0;
 
 	root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
 
@@ -1080,8 +1081,11 @@ static void mmu_alloc_roots(struct kvm_vcpu *vcpu)
 		hpa_t root = vcpu->arch.mmu.root_hpa;
 
 		ASSERT(!VALID_PAGE(root));
+		if (kvm_x86_ops->hap_enabled())
+			metaphysical = 1;
 		sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
-				      PT64_ROOT_LEVEL, 0, ACC_ALL, NULL, NULL);
+				      PT64_ROOT_LEVEL, metaphysical,
+				      ACC_ALL, NULL, NULL);
 		root = __pa(sp->spt);
 		++sp->root_count;
 		vcpu->arch.mmu.root_hpa = root;
@@ -1135,6 +1139,36 @@ static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
 			     error_code & PFERR_WRITE_MASK, gfn);
 }
 
+static int hap_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
+				u32 error_code)
+{
+	struct page *page;
+	int r;
+
+	ASSERT(vcpu);
+	ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
+
+	r = mmu_topup_memory_caches(vcpu);
+	if (r)
+		return r;
+
+	down_read(&current->mm->mmap_sem);
+	page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
+	if (is_error_page(page)) {
+		kvm_release_page_clean(page);
+		up_read(&current->mm->mmap_sem);
+		return 1;
+	}
+	spin_lock(&vcpu->kvm->mmu_lock);
+	kvm_mmu_free_some_pages(vcpu);
+	r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
+			 gpa >> PAGE_SHIFT, page, HAP_ROOT_LEVEL);
+	spin_unlock(&vcpu->kvm->mmu_lock);
+	up_read(&current->mm->mmap_sem);
+
+	return r;
+}
+
 static void nonpaging_free(struct kvm_vcpu *vcpu)
 {
 	mmu_free_roots(vcpu);
@@ -1228,7 +1262,35 @@ static int paging32E_init_context(struct kvm_vcpu *vcpu)
 	return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
 }
 
-static int init_kvm_mmu(struct kvm_vcpu *vcpu)
+static int init_kvm_hap_mmu(struct kvm_vcpu *vcpu)
+{
+	struct kvm_mmu *context = &vcpu->arch.mmu;
+
+	context->new_cr3 = nonpaging_new_cr3;
+	context->page_fault = hap_page_fault;
+	context->free = nonpaging_free;
+	context->prefetch_page = nonpaging_prefetch_page;
+	context->shadow_root_level = HAP_ROOT_LEVEL;
+	context->root_hpa = INVALID_PAGE;
+
+	if (!is_paging(vcpu)) {
+		context->gva_to_gpa = nonpaging_gva_to_gpa;
+		context->root_level = 0;
+	} else if (is_long_mode(vcpu)) {
+		context->gva_to_gpa = paging64_gva_to_gpa;
+		context->root_level = PT64_ROOT_LEVEL;
+	} else if (is_pae(vcpu)) {
+		context->gva_to_gpa = paging64_gva_to_gpa;
+		context->root_level = PT32E_ROOT_LEVEL;
+	} else {
+		context->gva_to_gpa = paging32_gva_to_gpa;
+		context->root_level = PT32_ROOT_LEVEL;
+	}
+
+	return 0;
+}
+
+static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
 {
 	ASSERT(vcpu);
 	ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
@@ -1243,6 +1305,14 @@ static int init_kvm_mmu(struct kvm_vcpu *vcpu)
 		return paging32_init_context(vcpu);
 }
 
+static int init_kvm_mmu(struct kvm_vcpu *vcpu)
+{
+	if (kvm_x86_ops->hap_enabled())
+		return init_kvm_hap_mmu(vcpu);
+	else
+		return init_kvm_softmmu(vcpu);
+}
+
 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
 {
 	ASSERT(vcpu);
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 1fce19e..ef880a5 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -3,6 +3,12 @@
 
 #include <linux/kvm_host.h>
 
+#ifdef CONFIG_X86_64
+#define HAP_ROOT_LEVEL PT64_ROOT_LEVEL
+#else
+#define HAP_ROOT_LEVEL PT32E_ROOT_LEVEL
+#endif
+
 static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
 {
 	if (unlikely(vcpu->kvm->arch.n_free_mmu_pages < KVM_MIN_FREE_MMU_PAGES))
-- 
1.5.3.7

[PATCH 7/8] MMU: add HAP support to the KVM MMU

[Joerg Roedel]

This patch contains the changes to the KVM MMU necessary for support of the
Nested Paging feature in AMD Barcelona and Phenom Processors.

Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
---
 arch/x86/kvm/mmu.c |   74 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 arch/x86/kvm/mmu.h |    6 ++++
 2 files changed, 78 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index dfbcf5e..bce27ca 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -1072,6 +1072,7 @@ static void mmu_alloc_roots(struct kvm_vcpu *vcpu)
 	int i;
 	gfn_t root_gfn;
 	struct kvm_mmu_page *sp;
+	int metaphysical = 0;
 
 	root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
 
@@ -1080,8 +1081,11 @@ static void mmu_alloc_roots(struct kvm_vcpu *vcpu)
 		hpa_t root = vcpu->arch.mmu.root_hpa;
 
 		ASSERT(!VALID_PAGE(root));
+		if (kvm_x86_ops->hap_enabled())
+			metaphysical = 1;
 		sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
-				      PT64_ROOT_LEVEL, 0, ACC_ALL, NULL, NULL);
+				      PT64_ROOT_LEVEL, metaphysical,
+				      ACC_ALL, NULL, NULL);
 		root = __pa(sp->spt);
 		++sp->root_count;
 		vcpu->arch.mmu.root_hpa = root;
@@ -1135,6 +1139,36 @@ static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
 			     error_code & PFERR_WRITE_MASK, gfn);
 }
 
+static int hap_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
+				u32 error_code)
+{
+	struct page *page;
+	int r;
+
+	ASSERT(vcpu);
+	ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
+
+	r = mmu_topup_memory_caches(vcpu);
+	if (r)
+		return r;
+
+	down_read(&current->mm->mmap_sem);
+	page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
+	if (is_error_page(page)) {
+		kvm_release_page_clean(page);
+		up_read(&current->mm->mmap_sem);
+		return 1;
+	}
+	spin_lock(&vcpu->kvm->mmu_lock);
+	kvm_mmu_free_some_pages(vcpu);
+	r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
+			 gpa >> PAGE_SHIFT, page, HAP_ROOT_LEVEL);
+	spin_unlock(&vcpu->kvm->mmu_lock);
+	up_read(&current->mm->mmap_sem);
+
+	return r;
+}
+
 static void nonpaging_free(struct kvm_vcpu *vcpu)
 {
 	mmu_free_roots(vcpu);
@@ -1228,7 +1262,35 @@ static int paging32E_init_context(struct kvm_vcpu *vcpu)
 	return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
 }
 
-static int init_kvm_mmu(struct kvm_vcpu *vcpu)
+static int init_kvm_hap_mmu(struct kvm_vcpu *vcpu)
+{
+	struct kvm_mmu *context = &vcpu->arch.mmu;
+
+	context->new_cr3 = nonpaging_new_cr3;
+	context->page_fault = hap_page_fault;
+	context->free = nonpaging_free;
+	context->prefetch_page = nonpaging_prefetch_page;
+	context->shadow_root_level = HAP_ROOT_LEVEL;
+	context->root_hpa = INVALID_PAGE;
+
+	if (!is_paging(vcpu)) {
+		context->gva_to_gpa = nonpaging_gva_to_gpa;
+		context->root_level = 0;
+	} else if (is_long_mode(vcpu)) {
+		context->gva_to_gpa = paging64_gva_to_gpa;
+		context->root_level = PT64_ROOT_LEVEL;
+	} else if (is_pae(vcpu)) {
+		context->gva_to_gpa = paging64_gva_to_gpa;
+		context->root_level = PT32E_ROOT_LEVEL;
+	} else {
+		context->gva_to_gpa = paging32_gva_to_gpa;
+		context->root_level = PT32_ROOT_LEVEL;
+	}
+
+	return 0;
+}
+
+static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
 {
 	ASSERT(vcpu);
 	ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
@@ -1243,6 +1305,14 @@ static int init_kvm_mmu(struct kvm_vcpu *vcpu)
 		return paging32_init_context(vcpu);
 }
 
+static int init_kvm_mmu(struct kvm_vcpu *vcpu)
+{
+	if (kvm_x86_ops->hap_enabled())
+		return init_kvm_hap_mmu(vcpu);
+	else
+		return init_kvm_softmmu(vcpu);
+}
+
 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
 {
 	ASSERT(vcpu);
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 1fce19e..ef880a5 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -3,6 +3,12 @@
 
 #include <linux/kvm_host.h>
 
+#ifdef CONFIG_X86_64
+#define HAP_ROOT_LEVEL PT64_ROOT_LEVEL
+#else
+#define HAP_ROOT_LEVEL PT32E_ROOT_LEVEL
+#endif
+
 static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
 {
 	if (unlikely(vcpu->kvm->arch.n_free_mmu_pages < KVM_MIN_FREE_MMU_PAGES))
-- 
1.5.3.7




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[PATCH 8/8] SVM: add support for Nested Paging

[Joerg Roedel]

This patch contains the SVM architecture dependent changes for KVM to enable
support for the Nested Paging feature of AMD Barcelona and Phenom processors.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kvm/svm.c |   67 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 63 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index d0bfdd8..578d8ec 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -47,7 +47,12 @@ MODULE_LICENSE("GPL");
 #define SVM_FEATURE_LBRV (1 << 1)
 #define SVM_DEATURE_SVML (1 << 2)
 
+#ifdef CONFIG_X86_64
+static bool npt_enabled = true;
+#else
 static bool npt_enabled = false;
+#endif
+
 static char *npt = "on";
 
 module_param(npt, charp, S_IRUGO);
@@ -187,7 +192,7 @@ static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 
 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 {
-	if (!(efer & EFER_LMA))
+	if (!npt_enabled && !(efer & EFER_LMA))
 		efer &= ~EFER_LME;
 
 	to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
@@ -568,6 +573,24 @@ static void init_vmcb(struct vmcb *vmcb)
 	save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 	save->cr4 = X86_CR4_PAE;
 	/* rdx = ?? */
+
+	if (npt_enabled) {
+		/* Setup VMCB for Nested Paging */
+		control->nested_ctl = 1;
+		control->intercept_exceptions &= ~(1 << PF_VECTOR);
+		control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
+						INTERCEPT_CR3_MASK|
+						INTERCEPT_CR4_MASK);
+		control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
+						 INTERCEPT_CR3_MASK|
+						 INTERCEPT_CR4_MASK);
+		save->g_pat = 0x0007040600070406ULL;
+		/* enable caching because the QEMU Bios doesn't enable it */
+		save->cr0 = X86_CR0_ET;
+		save->cr3 = 0;
+		save->cr4 = 0;
+	}
+
 }
 
 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
@@ -789,6 +812,15 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
 
+	if (npt_enabled) {
+		/*
+		 * re-enable caching here because the QEMU bios
+		 * does not do it - this results in some delay at
+		 * reboot
+		 */
+		cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
+		goto set;
+	}
 #ifdef CONFIG_X86_64
 	if (vcpu->arch.shadow_efer & EFER_LME) {
 		if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
@@ -812,13 +844,16 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 	cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 	if (!vcpu->fpu_active)
 		cr0 |= X86_CR0_TS;
+set:
 	svm->vmcb->save.cr0 = cr0;
 }
 
 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 {
        vcpu->arch.cr4 = cr4;
-       to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
+       if (!npt_enabled)
+	       cr4 |= X86_CR4_PAE;
+       to_svm(vcpu)->vmcb->save.cr4 = cr4;
 }
 
 static void svm_set_segment(struct kvm_vcpu *vcpu,
@@ -1284,14 +1319,31 @@ static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
 	[SVM_EXIT_WBINVD]                       = emulate_on_interception,
 	[SVM_EXIT_MONITOR]			= invalid_op_interception,
 	[SVM_EXIT_MWAIT]			= invalid_op_interception,
+	[SVM_EXIT_NPF]				= pf_interception,
 };
 
-
 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
 	u32 exit_code = svm->vmcb->control.exit_code;
 
+	if (npt_enabled) {
+		int mmu_reload = 0;
+		if (((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG)
+		    || ((vcpu->arch.cr4 ^ svm->vmcb->save.cr4) &
+			(X86_CR4_PGE|X86_CR4_PAE)))
+			mmu_reload = 1;
+		vcpu->arch.cr0 = svm->vmcb->save.cr0;
+		vcpu->arch.cr4 = svm->vmcb->save.cr4;
+		vcpu->arch.cr3 = svm->vmcb->save.cr3;
+		if (mmu_reload) {
+			kvm_mmu_reset_context(vcpu);
+			kvm_mmu_load(vcpu);
+		}
+		if (is_pae(vcpu) && !is_long_mode(vcpu))
+			load_pdptrs(vcpu, vcpu->arch.cr3);
+	}
+
 	kvm_reput_irq(svm);
 
 	if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
@@ -1302,7 +1354,8 @@ static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 	}
 
 	if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
-	    exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
+	    exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
+	    exit_code != SVM_EXIT_NPF)
 		printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
 		       "exit_code 0x%x\n",
 		       __FUNCTION__, svm->vmcb->control.exit_int_info,
@@ -1636,6 +1689,12 @@ static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
 
+	if (npt_enabled) {
+		svm->vmcb->control.nested_cr3 = root;
+		force_new_asid(vcpu);
+		return;
+	}
+
 	svm->vmcb->save.cr3 = root;
 	force_new_asid(vcpu);
 
-- 
1.5.3.7

[PATCH 8/8] SVM: add support for Nested Paging

[Joerg Roedel]

This patch contains the SVM architecture dependent changes for KVM to enable
support for the Nested Paging feature of AMD Barcelona and Phenom processors.

Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
---
 arch/x86/kvm/svm.c |   67 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 63 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index d0bfdd8..578d8ec 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -47,7 +47,12 @@ MODULE_LICENSE("GPL");
 #define SVM_FEATURE_LBRV (1 << 1)
 #define SVM_DEATURE_SVML (1 << 2)
 
+#ifdef CONFIG_X86_64
+static bool npt_enabled = true;
+#else
 static bool npt_enabled = false;
+#endif
+
 static char *npt = "on";
 
 module_param(npt, charp, S_IRUGO);
@@ -187,7 +192,7 @@ static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 
 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 {
-	if (!(efer & EFER_LMA))
+	if (!npt_enabled && !(efer & EFER_LMA))
 		efer &= ~EFER_LME;
 
 	to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
@@ -568,6 +573,24 @@ static void init_vmcb(struct vmcb *vmcb)
 	save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 	save->cr4 = X86_CR4_PAE;
 	/* rdx = ?? */
+
+	if (npt_enabled) {
+		/* Setup VMCB for Nested Paging */
+		control->nested_ctl = 1;
+		control->intercept_exceptions &= ~(1 << PF_VECTOR);
+		control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
+						INTERCEPT_CR3_MASK|
+						INTERCEPT_CR4_MASK);
+		control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
+						 INTERCEPT_CR3_MASK|
+						 INTERCEPT_CR4_MASK);
+		save->g_pat = 0x0007040600070406ULL;
+		/* enable caching because the QEMU Bios doesn't enable it */
+		save->cr0 = X86_CR0_ET;
+		save->cr3 = 0;
+		save->cr4 = 0;
+	}
+
 }
 
 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
@@ -789,6 +812,15 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
 
+	if (npt_enabled) {
+		/*
+		 * re-enable caching here because the QEMU bios
+		 * does not do it - this results in some delay at
+		 * reboot
+		 */
+		cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
+		goto set;
+	}
 #ifdef CONFIG_X86_64
 	if (vcpu->arch.shadow_efer & EFER_LME) {
 		if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
@@ -812,13 +844,16 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 	cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 	if (!vcpu->fpu_active)
 		cr0 |= X86_CR0_TS;
+set:
 	svm->vmcb->save.cr0 = cr0;
 }
 
 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 {
        vcpu->arch.cr4 = cr4;
-       to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
+       if (!npt_enabled)
+	       cr4 |= X86_CR4_PAE;
+       to_svm(vcpu)->vmcb->save.cr4 = cr4;
 }
 
 static void svm_set_segment(struct kvm_vcpu *vcpu,
@@ -1284,14 +1319,31 @@ static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
 	[SVM_EXIT_WBINVD]                       = emulate_on_interception,
 	[SVM_EXIT_MONITOR]			= invalid_op_interception,
 	[SVM_EXIT_MWAIT]			= invalid_op_interception,
+	[SVM_EXIT_NPF]				= pf_interception,
 };
 
-
 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
 	u32 exit_code = svm->vmcb->control.exit_code;
 
+	if (npt_enabled) {
+		int mmu_reload = 0;
+		if (((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG)
+		    || ((vcpu->arch.cr4 ^ svm->vmcb->save.cr4) &
+			(X86_CR4_PGE|X86_CR4_PAE)))
+			mmu_reload = 1;
+		vcpu->arch.cr0 = svm->vmcb->save.cr0;
+		vcpu->arch.cr4 = svm->vmcb->save.cr4;
+		vcpu->arch.cr3 = svm->vmcb->save.cr3;
+		if (mmu_reload) {
+			kvm_mmu_reset_context(vcpu);
+			kvm_mmu_load(vcpu);
+		}
+		if (is_pae(vcpu) && !is_long_mode(vcpu))
+			load_pdptrs(vcpu, vcpu->arch.cr3);
+	}
+
 	kvm_reput_irq(svm);
 
 	if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
@@ -1302,7 +1354,8 @@ static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 	}
 
 	if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
-	    exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
+	    exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
+	    exit_code != SVM_EXIT_NPF)
 		printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
 		       "exit_code 0x%x\n",
 		       __FUNCTION__, svm->vmcb->control.exit_int_info,
@@ -1636,6 +1689,12 @@ static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
 
+	if (npt_enabled) {
+		svm->vmcb->control.nested_cr3 = root;
+		force_new_asid(vcpu);
+		return;
+	}
+
 	svm->vmcb->save.cr3 = root;
 	force_new_asid(vcpu);
 
-- 
1.5.3.7




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Re: [kvm-devel] [PATCH 8/8] SVM: add support for Nested Paging

[Avi Kivity]

Joerg Roedel wrote:
> This patch contains the SVM architecture dependent changes for KVM to enable
> support for the Nested Paging feature of AMD Barcelona and Phenom processors.
>  
> +#ifdef CONFIG_X86_64
> +static bool npt_enabled = true;
> +#else
>  static bool npt_enabled = false;
> +#endif
>   

I think that i386 + pae can also support npt, with no changes, no?

So we should check CONFIG_X86_PAE, not X86_64.

> +
> +	if (npt_enabled) {
> +		/* Setup VMCB for Nested Paging */
> +		control->nested_ctl = 1;
> +		control->intercept_exceptions &= ~(1 << PF_VECTOR);
> +		control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
> +						INTERCEPT_CR3_MASK|
> +						INTERCEPT_CR4_MASK);
> +		control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
> +						 INTERCEPT_CR3_MASK|
> +						 INTERCEPT_CR4_MASK);
>   

What happens to lazy fpu if we don't trap cr0 changes?

Perhaps it's worth disabling lazy fpu with npt.

>  static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
> @@ -789,6 +812,15 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
>  {
>  	struct vcpu_svm *svm = to_svm(vcpu);
>  
> +	if (npt_enabled) {
> +		/*
> +		 * re-enable caching here because the QEMU bios
> +		 * does not do it - this results in some delay at
> +		 * reboot
> +		 */
> +		cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
> +		goto set;
> +	}
>  #ifdef CONFIG_X86_64
>  	if (vcpu->arch.shadow_efer & EFER_LME) {
>  		if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
> @@ -812,13 +844,16 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
>  	cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
>  	if (!vcpu->fpu_active)
>  		cr0 |= X86_CR0_TS;
> +set:
>  	svm->vmcb->save.cr0 = cr0;
>  }
>   

You could move 'cr0 &= ~(X86_CR0_CD | X86_CR0_NW);' from three lines 
above the 'set' label downwards, and avoid it in the if () above.
>  static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
>  {
>  	struct vcpu_svm *svm = to_svm(vcpu);
>  	u32 exit_code = svm->vmcb->control.exit_code;
>  
> +	if (npt_enabled) {
> +		int mmu_reload = 0;
>   

blank line

> +		if (((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG)
> +		    || ((vcpu->arch.cr4 ^ svm->vmcb->save.cr4) &
> +			(X86_CR4_PGE|X86_CR4_PAE)))
> +			mmu_reload = 1;
> +		vcpu->arch.cr0 = svm->vmcb->save.cr0;
> +		vcpu->arch.cr4 = svm->vmcb->save.cr4;
> +		vcpu->arch.cr3 = svm->vmcb->save.cr3;
> +		if (mmu_reload) {
> +			kvm_mmu_reset_context(vcpu);
> +			kvm_mmu_load(vcpu);
> +		}
> +		if (is_pae(vcpu) && !is_long_mode(vcpu))
> +			load_pdptrs(vcpu, vcpu->arch.cr3);
>   

load_pdptrs() may fail; you need to check that.


-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 8/8] SVM: add support for Nested Paging

[Avi Kivity]

Joerg Roedel wrote:
> This patch contains the SVM architecture dependent changes for KVM to enable
> support for the Nested Paging feature of AMD Barcelona and Phenom processors.
>  
> +#ifdef CONFIG_X86_64
> +static bool npt_enabled = true;
> +#else
>  static bool npt_enabled = false;
> +#endif
>   

I think that i386 + pae can also support npt, with no changes, no?

So we should check CONFIG_X86_PAE, not X86_64.

> +
> +	if (npt_enabled) {
> +		/* Setup VMCB for Nested Paging */
> +		control->nested_ctl = 1;
> +		control->intercept_exceptions &= ~(1 << PF_VECTOR);
> +		control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
> +						INTERCEPT_CR3_MASK|
> +						INTERCEPT_CR4_MASK);
> +		control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
> +						 INTERCEPT_CR3_MASK|
> +						 INTERCEPT_CR4_MASK);
>   

What happens to lazy fpu if we don't trap cr0 changes?

Perhaps it's worth disabling lazy fpu with npt.

>  static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
> @@ -789,6 +812,15 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
>  {
>  	struct vcpu_svm *svm = to_svm(vcpu);
>  
> +	if (npt_enabled) {
> +		/*
> +		 * re-enable caching here because the QEMU bios
> +		 * does not do it - this results in some delay at
> +		 * reboot
> +		 */
> +		cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
> +		goto set;
> +	}
>  #ifdef CONFIG_X86_64
>  	if (vcpu->arch.shadow_efer & EFER_LME) {
>  		if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
> @@ -812,13 +844,16 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
>  	cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
>  	if (!vcpu->fpu_active)
>  		cr0 |= X86_CR0_TS;
> +set:
>  	svm->vmcb->save.cr0 = cr0;
>  }
>   

You could move 'cr0 &= ~(X86_CR0_CD | X86_CR0_NW);' from three lines 
above the 'set' label downwards, and avoid it in the if () above.
>  static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
>  {
>  	struct vcpu_svm *svm = to_svm(vcpu);
>  	u32 exit_code = svm->vmcb->control.exit_code;
>  
> +	if (npt_enabled) {
> +		int mmu_reload = 0;
>   

blank line

> +		if (((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG)
> +		    || ((vcpu->arch.cr4 ^ svm->vmcb->save.cr4) &
> +			(X86_CR4_PGE|X86_CR4_PAE)))
> +			mmu_reload = 1;
> +		vcpu->arch.cr0 = svm->vmcb->save.cr0;
> +		vcpu->arch.cr4 = svm->vmcb->save.cr4;
> +		vcpu->arch.cr3 = svm->vmcb->save.cr3;
> +		if (mmu_reload) {
> +			kvm_mmu_reset_context(vcpu);
> +			kvm_mmu_load(vcpu);
> +		}
> +		if (is_pae(vcpu) && !is_long_mode(vcpu))
> +			load_pdptrs(vcpu, vcpu->arch.cr3);
>   

load_pdptrs() may fail; you need to check that.


-- 
error compiling committee.c: too many arguments to function


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Re: [kvm-devel] [PATCH 8/8] SVM: add support for Nested Paging

[Joerg Roedel]

On Sun, Jan 27, 2008 at 10:52:30AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> > This patch contains the SVM architecture dependent changes for KVM to enable
> > support for the Nested Paging feature of AMD Barcelona and Phenom processors.
> >  
> > +#ifdef CONFIG_X86_64
> > +static bool npt_enabled = true;
> > +#else
> >  static bool npt_enabled = false;
> > +#endif
> >   
> 
> I think that i386 + pae can also support npt, with no changes, no?
> 
> So we should check CONFIG_X86_PAE, not X86_64.

Yes, I think that too. But its completly untested so I disabled it for
the first post of this patchset.

> > +
> > +	if (npt_enabled) {
> > +		/* Setup VMCB for Nested Paging */
> > +		control->nested_ctl = 1;
> > +		control->intercept_exceptions &= ~(1 << PF_VECTOR);
> > +		control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
> > +						INTERCEPT_CR3_MASK|
> > +						INTERCEPT_CR4_MASK);
> > +		control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
> > +						 INTERCEPT_CR3_MASK|
> > +						 INTERCEPT_CR4_MASK);
> >   
> 
> What happens to lazy fpu if we don't trap cr0 changes?
> 
> Perhaps it's worth disabling lazy fpu with npt.

It should be implicitly disabled with npt because accesses to cr3 are
not intercepted anymore. The svm_set_cr3 function is the only place
which disables fpu switching.

Re: [PATCH 8/8] SVM: add support for Nested Paging

[Joerg Roedel]

On Sun, Jan 27, 2008 at 10:52:30AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> > This patch contains the SVM architecture dependent changes for KVM to enable
> > support for the Nested Paging feature of AMD Barcelona and Phenom processors.
> >  
> > +#ifdef CONFIG_X86_64
> > +static bool npt_enabled = true;
> > +#else
> >  static bool npt_enabled = false;
> > +#endif
> >   
> 
> I think that i386 + pae can also support npt, with no changes, no?
> 
> So we should check CONFIG_X86_PAE, not X86_64.

Yes, I think that too. But its completly untested so I disabled it for
the first post of this patchset.

> > +
> > +	if (npt_enabled) {
> > +		/* Setup VMCB for Nested Paging */
> > +		control->nested_ctl = 1;
> > +		control->intercept_exceptions &= ~(1 << PF_VECTOR);
> > +		control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
> > +						INTERCEPT_CR3_MASK|
> > +						INTERCEPT_CR4_MASK);
> > +		control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
> > +						 INTERCEPT_CR3_MASK|
> > +						 INTERCEPT_CR4_MASK);
> >   
> 
> What happens to lazy fpu if we don't trap cr0 changes?
> 
> Perhaps it's worth disabling lazy fpu with npt.

It should be implicitly disabled with npt because accesses to cr3 are
not intercepted anymore. The svm_set_cr3 function is the only place
which disables fpu switching.


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Re: [kvm-devel] [PATCH 8/8] SVM: add support for Nested Paging

[Avi Kivity]

Joerg Roedel wrote:
>
>> What happens to lazy fpu if we don't trap cr0 changes?
>>
>> Perhaps it's worth disabling lazy fpu with npt.
>>     
>
> It should be implicitly disabled with npt because accesses to cr3 are
> not intercepted anymore. The svm_set_cr3 function is the only place
> which disables fpu switching.
>   

Okay.  We may want to investigate enabling it later, but no hurry now.

On the other hand, we want to trap cr0 so the guest can't control the 
cache disable bits.  Also cr4.pce and cr4.mce.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 8/8] SVM: add support for Nested Paging

[Avi Kivity]

Joerg Roedel wrote:
>
>> What happens to lazy fpu if we don't trap cr0 changes?
>>
>> Perhaps it's worth disabling lazy fpu with npt.
>>     
>
> It should be implicitly disabled with npt because accesses to cr3 are
> not intercepted anymore. The svm_set_cr3 function is the only place
> which disables fpu switching.
>   

Okay.  We may want to investigate enabling it later, but no hurry now.

On the other hand, we want to trap cr0 so the guest can't control the 
cache disable bits.  Also cr4.pce and cr4.mce.

-- 
error compiling committee.c: too many arguments to function


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Re: [kvm-devel] [PATCH 8/8] SVM: add support for Nested Paging

[Joerg Roedel]

On Sun, Jan 27, 2008 at 11:51:06AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> >
> >> What happens to lazy fpu if we don't trap cr0 changes?
> >>
> >> Perhaps it's worth disabling lazy fpu with npt.
> >>     
> >
> > It should be implicitly disabled with npt because accesses to cr3 are
> > not intercepted anymore. The svm_set_cr3 function is the only place
> > which disables fpu switching.
> >   
> 
> Okay.  We may want to investigate enabling it later, but no hurry now.
> 
> On the other hand, we want to trap cr0 so the guest can't control the 
> cache disable bits.  Also cr4.pce and cr4.mce.

Is it a problem when the guest disables caching? It disables it only in
its own context because it has its own copy of cr0. Cr4.pce can be
accessible for the guests because there is no way for them to access the
performance counter MSRs. But I am not sure about MCE, I will check
that.

Re: [PATCH 8/8] SVM: add support for Nested Paging

[Joerg Roedel]

On Sun, Jan 27, 2008 at 11:51:06AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> >
> >> What happens to lazy fpu if we don't trap cr0 changes?
> >>
> >> Perhaps it's worth disabling lazy fpu with npt.
> >>     
> >
> > It should be implicitly disabled with npt because accesses to cr3 are
> > not intercepted anymore. The svm_set_cr3 function is the only place
> > which disables fpu switching.
> >   
> 
> Okay.  We may want to investigate enabling it later, but no hurry now.
> 
> On the other hand, we want to trap cr0 so the guest can't control the 
> cache disable bits.  Also cr4.pce and cr4.mce.

Is it a problem when the guest disables caching? It disables it only in
its own context because it has its own copy of cr0. Cr4.pce can be
accessible for the guests because there is no way for them to access the
performance counter MSRs. But I am not sure about MCE, I will check
that.

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Re: [kvm-devel] [PATCH 8/8] SVM: add support for Nested Paging

[Avi Kivity]

Joerg Roedel wrote:
>> On the other hand, we want to trap cr0 so the guest can't control the 
>> cache disable bits.  Also cr4.pce and cr4.mce.
>>     
>
> Is it a problem when the guest disables caching? It disables it only in
> its own context because it has its own copy of cr0. 

Some Intel processors have a mode where cache coherency is no longer 
preserved, and we need to prevent that.  However from my reading of the 
AMD manuals, cache coherency is preserved even with caching disabled, so 
no real issue with disabling the cache.


> Cr4.pce can be
> accessible for the guests because there is no way for them to access the
> performance counter MSRs. 

Yes.  This was a red herring, cr0.pce only affects userspace rdpmc.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 8/8] SVM: add support for Nested Paging

[Avi Kivity]

Joerg Roedel wrote:
>> On the other hand, we want to trap cr0 so the guest can't control the 
>> cache disable bits.  Also cr4.pce and cr4.mce.
>>     
>
> Is it a problem when the guest disables caching? It disables it only in
> its own context because it has its own copy of cr0. 

Some Intel processors have a mode where cache coherency is no longer 
preserved, and we need to prevent that.  However from my reading of the 
AMD manuals, cache coherency is preserved even with caching disabled, so 
no real issue with disabling the cache.


> Cr4.pce can be
> accessible for the guests because there is no way for them to access the
> performance counter MSRs. 

Yes.  This was a red herring, cr0.pce only affects userspace rdpmc.

-- 
error compiling committee.c: too many arguments to function


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Re: [kvm-devel] [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Anthony Liguori]

Joerg Roedel wrote:
> Hi,                                                                                                                              
>
> here is the first release of patches for KVM to support the Nested Paging (NPT)
> feature of AMD QuadCore CPUs for comments and public testing. This feature
> improves the guest performance significantly. I measured an improvement of
> around 17% using kernbench in my first tests.
>
> This patch series is basically tested with Linux guests (32 bit legacy
> paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with Windows Vista
> 32 bit and 64 bit. All these guests ran successfully with these patches. The
> patch series only enables NPT for 64 bit Linux hosts at the moment.
>
> Please give these patches a good and deep testing. I hope we have this patchset
> ready for merging soon.
>   

A quick sniff test and things look pretty good.  I was able to start 
running the install CDs for 32-bit and 64-bit Ubuntu, 32-bit OpenSuSE, 
64-bit Fedora, and 32-bit Win2k8.  I'll do a more thorough run of 
kvm-test on Monday when I have a better connection to my machine.

Nice work!

Regards,

Anthony Liguori

> Joerg
>
> Here is the diffstat:
>
>  arch/x86/kvm/mmu.c         |   81 +++++++++++++++++++++++++++++++++++---
>  arch/x86/kvm/mmu.h         |    6 +++
>  arch/x86/kvm/svm.c         |   94 +++++++++++++++++++++++++++++++++++++++++--
>  arch/x86/kvm/vmx.c         |    7 +++
>  arch/x86/kvm/x86.c         |    1 +
>  include/asm-x86/kvm_host.h |    4 ++
>  6 files changed, 182 insertions(+), 11 deletions(-)
>
>
>
>
>
> -------------------------------------------------------------------------
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> kvm-devel@lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/kvm-devel
>   

Re: [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Anthony Liguori]

Joerg Roedel wrote:
> Hi,                                                                                                                              
>
> here is the first release of patches for KVM to support the Nested Paging (NPT)
> feature of AMD QuadCore CPUs for comments and public testing. This feature
> improves the guest performance significantly. I measured an improvement of
> around 17% using kernbench in my first tests.
>
> This patch series is basically tested with Linux guests (32 bit legacy
> paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with Windows Vista
> 32 bit and 64 bit. All these guests ran successfully with these patches. The
> patch series only enables NPT for 64 bit Linux hosts at the moment.
>
> Please give these patches a good and deep testing. I hope we have this patchset
> ready for merging soon.
>   

A quick sniff test and things look pretty good.  I was able to start 
running the install CDs for 32-bit and 64-bit Ubuntu, 32-bit OpenSuSE, 
64-bit Fedora, and 32-bit Win2k8.  I'll do a more thorough run of 
kvm-test on Monday when I have a better connection to my machine.

Nice work!

Regards,

Anthony Liguori

> Joerg
>
> Here is the diffstat:
>
>  arch/x86/kvm/mmu.c         |   81 +++++++++++++++++++++++++++++++++++---
>  arch/x86/kvm/mmu.h         |    6 +++
>  arch/x86/kvm/svm.c         |   94 +++++++++++++++++++++++++++++++++++++++++--
>  arch/x86/kvm/vmx.c         |    7 +++
>  arch/x86/kvm/x86.c         |    1 +
>  include/asm-x86/kvm_host.h |    4 ++
>  6 files changed, 182 insertions(+), 11 deletions(-)
>
>
>
>
>
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Re: [kvm-devel] [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Joerg Roedel]

On Fri, Jan 25, 2008 at 03:32:57PM -0600, Anthony Liguori wrote:

> A quick sniff test and things look pretty good.  I was able to start 
> running the install CDs for 32-bit and 64-bit Ubuntu, 32-bit OpenSuSE, 
> 64-bit Fedora, and 32-bit Win2k8.  I'll do a more thorough run of 
> kvm-test on Monday when I have a better connection to my machine.

Great. We will do more tests too next week. Life migration is completly
untested for now. SMP guests worked also fine with this patches.

> Nice work!

Thanks :-)

Joerg

Re: [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Joerg Roedel]

On Fri, Jan 25, 2008 at 03:32:57PM -0600, Anthony Liguori wrote:

> A quick sniff test and things look pretty good.  I was able to start 
> running the install CDs for 32-bit and 64-bit Ubuntu, 32-bit OpenSuSE, 
> 64-bit Fedora, and 32-bit Win2k8.  I'll do a more thorough run of 
> kvm-test on Monday when I have a better connection to my machine.

Great. We will do more tests too next week. Life migration is completly
untested for now. SMP guests worked also fine with this patches.

> Nice work!

Thanks :-)

Joerg

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RE: [kvm-devel] [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Nakajima, Jun]

Joerg Roedel wrote:
> Hi,
> 
> here is the first release of patches for KVM to support the Nested
Paging
> (NPT) feature of AMD QuadCore CPUs for comments and public testing.
This
> feature improves the guest performance significantly. I measured an
> improvement of around 17% using kernbench in my first tests.
> 
> This patch series is basically tested with Linux guests (32 bit legacy
> paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with
Windows
> Vista 32 bit and 64 bit. All these guests ran successfully with these
> patches. The patch series only enables NPT for 64 bit Linux hosts at
the
> moment. 
> 
> Please give these patches a good and deep testing. I hope we have this
> patchset ready for merging soon.

Good. We also ported the EPT patch for Xen to KVM, which we submitted
last year. We've been cleaning up the patch with Avi. We are working on
live migration support now, and we'll submit the patch once it's done.
So please stay tuned.

> 
> Joerg
> 

Jun
---
Intel Open Source Technology Center

Re: [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Nakajima, Jun]

Joerg Roedel wrote:
> Hi,
> 
> here is the first release of patches for KVM to support the Nested
Paging
> (NPT) feature of AMD QuadCore CPUs for comments and public testing.
This
> feature improves the guest performance significantly. I measured an
> improvement of around 17% using kernbench in my first tests.
> 
> This patch series is basically tested with Linux guests (32 bit legacy
> paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with
Windows
> Vista 32 bit and 64 bit. All these guests ran successfully with these
> patches. The patch series only enables NPT for 64 bit Linux hosts at
the
> moment. 
> 
> Please give these patches a good and deep testing. I hope we have this
> patchset ready for merging soon.

Good. We also ported the EPT patch for Xen to KVM, which we submitted
last year. We've been cleaning up the patch with Avi. We are working on
live migration support now, and we'll submit the patch once it's done.
So please stay tuned.

> 
> Joerg
> 

Jun
---
Intel Open Source Technology Center

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Re: [kvm-devel] [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Avi Kivity]

Joerg Roedel wrote:
> Hi,                                                                                                                              
>
> here is the first release of patches for KVM to support the Nested Paging (NPT)
> feature of AMD QuadCore CPUs for comments and public testing. This feature
> improves the guest performance significantly. I measured an improvement of
> around 17% using kernbench in my first tests.
>
> This patch series is basically tested with Linux guests (32 bit legacy
> paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with Windows Vista
> 32 bit and 64 bit. All these guests ran successfully with these patches. The
> patch series only enables NPT for 64 bit Linux hosts at the moment.
>   


Very nice patchset; small, simple, and clean.  Apart from the comments I 
already posted, I'd like to avoid the term 'hap': I find it 
non-descriptive, and it reminds me of another hypervisor.  I suggest 
'tlp' for two-level paging.

Since it re-uses non-npt real-mode paging, live migration and swapping 
will likely work without further changes.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Avi Kivity]

Joerg Roedel wrote:
> Hi,                                                                                                                              
>
> here is the first release of patches for KVM to support the Nested Paging (NPT)
> feature of AMD QuadCore CPUs for comments and public testing. This feature
> improves the guest performance significantly. I measured an improvement of
> around 17% using kernbench in my first tests.
>
> This patch series is basically tested with Linux guests (32 bit legacy
> paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with Windows Vista
> 32 bit and 64 bit. All these guests ran successfully with these patches. The
> patch series only enables NPT for 64 bit Linux hosts at the moment.
>   


Very nice patchset; small, simple, and clean.  Apart from the comments I 
already posted, I'd like to avoid the term 'hap': I find it 
non-descriptive, and it reminds me of another hypervisor.  I suggest 
'tlp' for two-level paging.

Since it re-uses non-npt real-mode paging, live migration and swapping 
will likely work without further changes.

-- 
error compiling committee.c: too many arguments to function


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Re: [kvm-devel] [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Joerg Roedel]

On Sun, Jan 27, 2008 at 10:57:07AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> > Hi,                                                                                                                              
> >
> > here is the first release of patches for KVM to support the Nested Paging (NPT)
> > feature of AMD QuadCore CPUs for comments and public testing. This feature
> > improves the guest performance significantly. I measured an improvement of
> > around 17% using kernbench in my first tests.
> >
> > This patch series is basically tested with Linux guests (32 bit legacy
> > paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with Windows Vista
> > 32 bit and 64 bit. All these guests ran successfully with these patches. The
> > patch series only enables NPT for 64 bit Linux hosts at the moment.
> >   
> 
> 
> Very nice patchset; small, simple, and clean.  Apart from the comments I 
> already posted, I'd like to avoid the term 'hap': I find it 
> non-descriptive, and it reminds me of another hypervisor.  I suggest 
> 'tlp' for two-level paging.
> 
> Since it re-uses non-npt real-mode paging, live migration and swapping 
> will likely work without further changes.

Yes, I think so too. Thank you for your comments. I will work them into
the patchset and run some larger tests on it next week (test with many
kinds of guests and some stress testing) to be sure that there are no
regressions. I would like to enable NPT per default when the patchset
is merged. I will post a new version of the patchset maybe on Thursday
or Friday.

Joerg

Re: [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Joerg Roedel]

On Sun, Jan 27, 2008 at 10:57:07AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> > Hi,                                                                                                                              
> >
> > here is the first release of patches for KVM to support the Nested Paging (NPT)
> > feature of AMD QuadCore CPUs for comments and public testing. This feature
> > improves the guest performance significantly. I measured an improvement of
> > around 17% using kernbench in my first tests.
> >
> > This patch series is basically tested with Linux guests (32 bit legacy
> > paging, 32 bit PAE paging and 64 bit Long Mode). Also tested with Windows Vista
> > 32 bit and 64 bit. All these guests ran successfully with these patches. The
> > patch series only enables NPT for 64 bit Linux hosts at the moment.
> >   
> 
> 
> Very nice patchset; small, simple, and clean.  Apart from the comments I 
> already posted, I'd like to avoid the term 'hap': I find it 
> non-descriptive, and it reminds me of another hypervisor.  I suggest 
> 'tlp' for two-level paging.
> 
> Since it re-uses non-npt real-mode paging, live migration and swapping 
> will likely work without further changes.

Yes, I think so too. Thank you for your comments. I will work them into
the patchset and run some larger tests on it next week (test with many
kinds of guests and some stress testing) to be sure that there are no
regressions. I would like to enable NPT per default when the patchset
is merged. I will post a new version of the patchset maybe on Thursday
or Friday.

Joerg

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Re: [kvm-devel] [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Jeremy Fitzhardinge]

Avi Kivity wrote:
>  I find it non-descriptive, and it reminds me of another hypervisor.  
> I suggest 'tlp' for two-level paging.

That has its own ambiguity; without other context it reads like 
"two-level pagetable".  Anyway, using the same term for the same thing 
is not a bad idea.

    J

Re: [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Jeremy Fitzhardinge]

Avi Kivity wrote:
>  I find it non-descriptive, and it reminds me of another hypervisor.  
> I suggest 'tlp' for two-level paging.

That has its own ambiguity; without other context it reads like 
"two-level pagetable".  Anyway, using the same term for the same thing 
is not a bad idea.

    J

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Re: [kvm-devel] [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Avi Kivity]

Jeremy Fitzhardinge wrote:
> Avi Kivity wrote:
>   
>>  I find it non-descriptive, and it reminds me of another hypervisor.  
>> I suggest 'tlp' for two-level paging.
>>     
>
> That has its own ambiguity; without other context it reads like 
> "two-level pagetable".  Anyway, using the same term for the same thing 
> is not a bad idea.
>
>   

What annoys me about hap and hvm is that it comes from a 
paravirtualization viewpoint, where pv is the default model, and 
hardware extensions are an optional addition.  With kvm it's the other 
way round: the base model is full virtualization, and paravirtualization 
is an optional add-on.  I'd rather call traditional shadow paging 
"software-assisted paging".


-- 
error compiling committee.c: too many arguments to function

Re: [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Avi Kivity]

Jeremy Fitzhardinge wrote:
> Avi Kivity wrote:
>   
>>  I find it non-descriptive, and it reminds me of another hypervisor.  
>> I suggest 'tlp' for two-level paging.
>>     
>
> That has its own ambiguity; without other context it reads like 
> "two-level pagetable".  Anyway, using the same term for the same thing 
> is not a bad idea.
>
>   

What annoys me about hap and hvm is that it comes from a 
paravirtualization viewpoint, where pv is the default model, and 
hardware extensions are an optional addition.  With kvm it's the other 
way round: the base model is full virtualization, and paravirtualization 
is an optional add-on.  I'd rather call traditional shadow paging 
"software-assisted paging".


-- 
error compiling committee.c: too many arguments to function


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Re: [kvm-devel] [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Joerg Roedel]

On Sun, Jan 27, 2008 at 10:57:07AM +0200, Avi Kivity wrote:
> Very nice patchset; small, simple, and clean.  Apart from the comments
> I already posted, I'd like to avoid the term 'hap': I find it
> non-descriptive, and it reminds me of another hypervisor.  I suggest
> 'tlp' for two-level paging.

I renamed HAP to TDP. This stands for Two-Dimensional Paging and is the
term which descibes best what happens in my opinion.

Joerg

-- 
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 Operating |         Wilschdorfer Landstr. 101, 01109 Dresden, Germany
 System    |                  Register Court Dresden: HRA 4896
 Research  |              General Partner authorized to represent:
 Center    |             AMD Saxony LLC (Wilmington, Delaware, US)
           | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy

Re: [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Joerg Roedel]

On Sun, Jan 27, 2008 at 10:57:07AM +0200, Avi Kivity wrote:
> Very nice patchset; small, simple, and clean.  Apart from the comments
> I already posted, I'd like to avoid the term 'hap': I find it
> non-descriptive, and it reminds me of another hypervisor.  I suggest
> 'tlp' for two-level paging.

I renamed HAP to TDP. This stands for Two-Dimensional Paging and is the
term which descibes best what happens in my opinion.

Joerg

-- 
           |           AMD Saxony Limited Liability Company & Co. KG
 Operating |         Wilschdorfer Landstr. 101, 01109 Dresden, Germany
 System    |                  Register Court Dresden: HRA 4896
 Research  |              General Partner authorized to represent:
 Center    |             AMD Saxony LLC (Wilmington, Delaware, US)
           | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy



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Re: [kvm-devel] [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Avi Kivity]

Joerg Roedel wrote:
> On Sun, Jan 27, 2008 at 10:57:07AM +0200, Avi Kivity wrote:
>   
>> Very nice patchset; small, simple, and clean.  Apart from the comments
>> I already posted, I'd like to avoid the term 'hap': I find it
>> non-descriptive, and it reminds me of another hypervisor.  I suggest
>> 'tlp' for two-level paging.
>>     
>
> I renamed HAP to TDP. This stands for Two-Dimensional Paging and is the
> term which descibes best what happens in my opinion.
>
>   

Yes, it actually describes what is going on in there.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH][RFC] SVM: Add Support for Nested Paging in AMD Fam16 CPUs

[Avi Kivity]

Joerg Roedel wrote:
> On Sun, Jan 27, 2008 at 10:57:07AM +0200, Avi Kivity wrote:
>   
>> Very nice patchset; small, simple, and clean.  Apart from the comments
>> I already posted, I'd like to avoid the term 'hap': I find it
>> non-descriptive, and it reminds me of another hypervisor.  I suggest
>> 'tlp' for two-level paging.
>>     
>
> I renamed HAP to TDP. This stands for Two-Dimensional Paging and is the
> term which descibes best what happens in my opinion.
>
>   

Yes, it actually describes what is going on in there.

-- 
error compiling committee.c: too many arguments to function


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