From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6C880DDF73 for ; Tue, 16 Dec 2008 10:31:39 +1100 (EST) Subject: Re: [PATCH 11/16] powerpc/mm: Add SMP support to no-hash TLB handling v3 From: Benjamin Herrenschmidt To: Kumar Gala In-Reply-To: <01FA1F1A-0A98-4553-B27D-CBC627E3EC02@kernel.crashing.org> References: <20081215054554.E883EDDF9D@ozlabs.org> <1229373978.26324.120.camel@pasglop> <1229374984.26324.125.camel@pasglop> <1229375937.26324.128.camel@pasglop> <01FA1F1A-0A98-4553-B27D-CBC627E3EC02@kernel.crashing.org> Content-Type: text/plain Date: Tue, 16 Dec 2008 10:31:32 +1100 Message-Id: <1229383892.26324.132.camel@pasglop> Mime-Version: 1.0 Cc: linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Mon, 2008-12-15 at 16:19 -0600, Kumar Gala wrote: > Ok. Lets use MMU_FTR_LOCK_BCAST_TLB_OPS and have a comment about > locking because bus implementations cant handle multiple ivax and/or > multiple syncs. > Hi used MMU_FTR_LOCK_BCAST_INVAL :-) And I put a comment that says: /* This indicates that the processor cannot handle multiple outstanding * broadcast tlbivax or tlbsync. This makes the code use a spinlock * around such invalidate forms. */ Cheers, Ben.