From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mike Frysinger Date: Wed, 28 Jan 2009 19:03:24 -0500 Subject: [U-Boot] [PATCH 15/27] Blackfin: dma_memcpy(): fix random failures In-Reply-To: <1233187416-22378-1-git-send-email-vapier@gentoo.org> References: <1233187416-22378-1-git-send-email-vapier@gentoo.org> Message-ID: <1233187416-22378-16-git-send-email-vapier@gentoo.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de We have to make sure the DMA channel is actually disabled in hardware before attempting to reprogram it. Otherwise the new settings are ignored and we end up with random hangs/failures. Signed-off-by: Mike Frysinger --- lib_blackfin/string.c | 19 +++++++++++-------- 1 files changed, 11 insertions(+), 8 deletions(-) diff --git a/lib_blackfin/string.c b/lib_blackfin/string.c index 36eecdf..e458718 100644 --- a/lib_blackfin/string.c +++ b/lib_blackfin/string.c @@ -136,6 +136,14 @@ int strncmp(const char *cs, const char *ct, size_t count) */ void dma_memcpy_nocache(void *dst, const void *src, size_t count) { + /* Disable DMA in case it's still running (older u-boot's did not + * always turn them off). Do it before the if statement below so + * we can be cheap and not do a SSYNC() due to the forced abort. + */ + bfin_write_MDMA_D0_CONFIG(0); + bfin_write_MDMA_S0_CONFIG(0); + bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR); + /* Scratchpad cannot be a DMA source or destination */ if (((unsigned long)src >= L1_SRAM_SCRATCH && (unsigned long)src < L1_SRAM_SCRATCH_END) || @@ -143,10 +151,6 @@ void dma_memcpy_nocache(void *dst, const void *src, size_t count) (unsigned long)dst < L1_SRAM_SCRATCH_END)) hang(); - bfin_write_MDMA_S0_CONFIG(0); - bfin_write_MDMA_D0_CONFIG(0); - bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR); - /* Copy sram functions from sdram to sram */ /* Setup destination start address */ bfin_write_MDMA_D0_START_ADDR(dst); @@ -164,14 +168,13 @@ void dma_memcpy_nocache(void *dst, const void *src, size_t count) /* Enable source DMA */ bfin_write_MDMA_S0_CONFIG(DMAEN); - - bfin_write_MDMA_D0_CONFIG(WNR | DMAEN); + bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | DI_EN); SSYNC(); - while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) + while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) continue; - bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_RUN | DMA_DONE | DMA_ERR); + bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR); bfin_write_MDMA_D0_CONFIG(0); bfin_write_MDMA_S0_CONFIG(0); } -- 1.6.1.1