Re: Broken ARM atomic ops wrt memory barriers (was : [PATCH] Add cmpxchg support for ARMv6+ systems)

From: Catalin Marinas <catalin.marinas@arm.com>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>,
	Jamie Lokier <jamie@shareable.org>,
	linux-arm-kernel@lists.arm.linux.org.uk,
	linux-kernel@vger.kernel.org,
	"Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Subject: Re: Broken ARM atomic ops wrt memory barriers (was : [PATCH] Add cmpxchg support for ARMv6+ systems)
Date: Wed, 27 May 2009 10:18:28 +0100	[thread overview]
Message-ID: <1243415908.1947.27.camel@pc1117.cambridge.arm.com> (raw)
In-Reply-To: <20090527085631.GA18768@n2100.arm.linux.org.uk>

On Wed, 2009-05-27 at 09:56 +0100, Russell King - ARM Linux wrote:
> On Tue, May 26, 2009 at 09:22:43PM -0400, Mathieu Desnoyers wrote:
> > My point was not about the wmb() : we _clearly_ need a dmb there. My
> > point is about the hidden
> > 
> > smp_read_barrier_depends() in rcu_dereference() :
> > 
> > cpyptr = ptr;
> > smp_read_barrier_depends();
> > access *cpyptr data
> > 
> > Which is needed to make sure we update our global view of memory between
> > the pointer value read and the moment we read the data pointed to. This
> > makes sure the data read is not garbage.
> 
> There is a dependency between reading 'ptr' and reading 'data'.
> I think there was a paragraph in the ARM ARM about this which says
> that they happen in program order, but I don't have access at the
> moment to the ARM ARM to check right now.

You are right, there is an address dependency here and there is no need
for an explicit barrier (probably another difference from Alpha).

-- 
Catalin