[Qemu-devel] [PATCH 41/61] pci: make bar update function aware of pci bridge.

[Isaku Yamahata <yamahata@valinux.co.jp>]

header type of 01 has differenct BAR to type 00.
It has only BAR0,1 and expantion rom whose offset address
is different from type 00 one.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pci.c |   55 +++++++++++++++++++++++++++++++++++++++++++------------
 hw/pci.h |    3 +++
 2 files changed, 46 insertions(+), 12 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index ec6c7d4..dc93b28 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -483,6 +483,35 @@ int pci_unregister_device(PCIDevice *pci_dev)
     return 0;
 }
 
+#define PCI_BAR_INVALID  UINT32_MAX
+static uint32_t pci_bar_config_offset(PCIDevice *d, int region_num)
+{
+    switch (d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION) {
+    case PCI_HEADER_TYPE_NORMAL:
+        /* BAR 0-5 and Expantion ROM*/
+        if (region_num < PCI_ROM_SLOT) {
+            return PCI_BASE_ADDRESS_0 + region_num * 4;
+        } else if (region_num == PCI_ROM_SLOT) {
+            return PCI_ROM_ADDRESS;
+        }
+        break;
+    case PCI_HEADER_TYPE_BRIDGE:
+        /* BAR 0-1 and Expantion ROM */
+        if (region_num < 2) {
+            return PCI_BASE_ADDRESS_0 + region_num * 4;
+        } else if (region_num == PCI_ROM_SLOT) {
+            return PCI_ROM_ADDRESS1;
+        }
+        break;
+    case PCI_HEADER_TYPE_CARDBUS:
+    default:
+        break;
+    }
+    fprintf(stderr, "ERROR: %s: unknow PCI config header type %d or bar %d\n",
+            __func__, d->config[PCI_HEADER_TYPE], region_num);
+    return PCI_BAR_INVALID;
+}
+
 void pci_register_bar(PCIDevice *pci_dev, int region_num,
                             uint64_t size, int type,
                             PCIMapIORegionFunc *map_func)
@@ -506,13 +535,11 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
     r->type = type;
     r->map_func = map_func;
 
+    addr = pci_bar_config_offset(pci_dev, region_num);
     wmask = ~(size - 1);
     if (region_num == PCI_ROM_SLOT) {
-        addr = 0x30;
         /* ROM enable bit is writeable */
         wmask |= PCI_ROM_ADDRESS_ENABLE;
-    } else {
-        addr = 0x10 + region_num * 4;
     }
 
     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
@@ -541,11 +568,7 @@ static void pci_update_mappings(PCIDevice *d)
         if (r->size == 0)
             continue;
 
-        if (i == PCI_ROM_SLOT) {
-            config_ofs = 0x30;
-        } else {
-            config_ofs = 0x10 + i * 4;
-        }
+        config_ofs = pci_bar_config_offset(d, i);
 
         if (pci_bar_is_64bit(r)) {
             bar = le64_to_cpu(*(uint64_t *)(d->config + config_ofs));
@@ -1165,11 +1188,19 @@ static PCIBus *pci_bridge_get_secbus(PCIBridge *bridge)
 static void pci_bridge_write_config(PCIDevice *d,
                              uint32_t address, uint32_t val, int len)
 {
-    PCIBridge *bridge = pci_dev_to_br(d);
-    PCIBus *bus = pci_bridge_get_secbus(bridge);
+    pci_default_write_config_common(d, address, val, len);
+
+    if (pci_config_changed(address, len,
+                           PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2 + 4) ||
+        pci_config_changed_with_size(address, len, PCI_ROM_ADDRESS1, 4)) {
+        pci_update_mappings(d);
+    }
+    if (pci_config_changed_with_size(address, len, PCI_SECONDARY_BUS, 1)) {
+        PCIBridge *bridge = pci_dev_to_br(d);
+        PCIBus *bus = pci_bridge_get_secbus(bridge);
 
-    pci_default_write_config(d, address, val, len);
-    bus->bus_num = d->config[PCI_SECONDARY_BUS];
+        bus->bus_num = d->config[PCI_SECONDARY_BUS];
+    }
 }
 
 PCIBus *pci_find_bus(int bus_num)
diff --git a/hw/pci.h b/hw/pci.h
index 0aedbf5..b279f2d 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -170,6 +170,9 @@ static inline int pci_bar_is_64bit(const PCIIORegion *r)
 
 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 
+/* Header type 1 (PCI-to-PCI bridges) */
+#define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
+
 /* Size of the standard PCI config header */
 #define PCI_CONFIG_HEADER_SIZE 0x40
 /* Size of the standard PCI config space */
-- 
1.6.0.2