From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MswIq-0004ss-9Y for qemu-devel@nongnu.org; Wed, 30 Sep 2009 06:20:56 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MswIO-0004Z7-Nk for qemu-devel@nongnu.org; Wed, 30 Sep 2009 06:20:50 -0400 Received: from [199.232.76.173] (port=43894 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MswIM-0004Yt-Qy for qemu-devel@nongnu.org; Wed, 30 Sep 2009 06:20:26 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:55868) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MswIL-0005ph-SC for qemu-devel@nongnu.org; Wed, 30 Sep 2009 06:20:26 -0400 From: Isaku Yamahata Date: Wed, 30 Sep 2009 19:18:33 +0900 Message-Id: <1254305917-14784-58-git-send-email-yamahata@valinux.co.jp> In-Reply-To: <1254305917-14784-1-git-send-email-yamahata@valinux.co.jp> References: <1254305917-14784-1-git-send-email-yamahata@valinux.co.jp> Subject: [Qemu-devel] [PATCH 57/61] ioapic: add callback when entry is set or ioapic is reset List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, anthony@codemonkey.ws Cc: yamahata@valinux.co.jp Add hooks to ioapic. This is necessary for pci interrupt routing mode from PIC mode to IO APIC mode. Signed-off-by: Isaku Yamahata --- hw/ioapic.c | 20 +++++++++++++++++++- hw/pc.h | 2 ++ 2 files changed, 21 insertions(+), 1 deletions(-) diff --git a/hw/ioapic.c b/hw/ioapic.c index a9a8e00..882ca9d 100644 --- a/hw/ioapic.c +++ b/hw/ioapic.c @@ -53,8 +53,16 @@ struct IOAPICState { uint32_t irr; uint64_t ioredtbl[IOAPIC_NUM_PINS]; + ioapic_update_fn update_fn; + void *opaque; }; +static void ioapic_callback(IOAPICState *s, int reset) +{ + if (s->update_fn) + s->update_fn(s->opaque, reset); +} + static void ioapic_service(IOAPICState *s) { uint8_t i; @@ -186,6 +194,7 @@ static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t va s->ioredtbl[index] &= ~0xffffffffULL; s->ioredtbl[index] |= val; } + ioapic_callback(s, 0); ioapic_service(s); } } @@ -210,6 +219,8 @@ static void ioapic_reset(void *opaque) IOAPICState *s = opaque; int i; + ioapic_callback(s, 1); + memset(s, 0, sizeof(*s)); for(i = 0; i < IOAPIC_NUM_PINS; i++) s->ioredtbl[i] = 1 << 16; /* mask LVT */ @@ -227,13 +238,15 @@ static CPUWriteMemoryFunc * const ioapic_mem_write[3] = { ioapic_mem_writel, }; -qemu_irq *ioapic_init(void) +qemu_irq *ioapic_init_with_arg(ioapic_update_fn update_fn, void *opaque) { IOAPICState *s; qemu_irq *irq; int io_memory; s = qemu_mallocz(sizeof(IOAPICState)); + s->update_fn = update_fn; + s->opaque = opaque; ioapic_reset(s); io_memory = cpu_register_io_memory(ioapic_mem_read, @@ -246,3 +259,8 @@ qemu_irq *ioapic_init(void) return irq; } + +qemu_irq *ioapic_init(void) +{ + return ioapic_init_with_arg(NULL, NULL); +} diff --git a/hw/pc.h b/hw/pc.h index 7577956..44eac49 100644 --- a/hw/pc.h +++ b/hw/pc.h @@ -52,6 +52,8 @@ int apic_accept_pic_intr(CPUState *env); void apic_deliver_pic_intr(CPUState *env, int level); int apic_get_interrupt(CPUState *env); qemu_irq *ioapic_init(void); +typedef void (*ioapic_update_fn)(void *opaque, int reset); +qemu_irq *ioapic_init_with_arg(ioapic_update_fn update_fn, void *opaque); void apic_reset_irq_delivered(void); int apic_get_irq_delivered(void); -- 1.6.0.2