* [PATCH] AM35xx: Clock table updates for AM3505/17
@ 2009-11-05 10:39 Ranjith Lohithakshan
2009-11-05 16:24 ` Menon, Nishanth
2009-11-11 21:43 ` Kevin Hilman
0 siblings, 2 replies; 8+ messages in thread
From: Ranjith Lohithakshan @ 2009-11-05 10:39 UTC (permalink / raw)
To: linux-omap; +Cc: ranjithl
AM3505/17 though a OMAP3530 derivative have the following
main differences
- Removal of the following OMAP3 modules
- IVA
- ISP/CAM
- Modem and D2D components (MAD2D, SAD2D)
- USIM
- SSI
- Mailboxes
- USB OTG
- ICR
- MSPRO
- SmartReflex
- SDRC replaced with EMIF4 Controller in the SDRC subsystem
thus adding support for DDR2 memory devices
- Addition of the following new modules
- Ethernet MAC (CPGMAC)
- CAN Controller (HECC)
- New USB OTG Controller with integrated Phy
- Video Processing Front End (VPFE)
- Additional UART (UART4)
- All security accelerators disabled on GP devices and not to
be accessed or configured
This patch defines CPU flags for AM3505/17 and update the clock table.
Clock support for new modules will be added by subsequent patches.
Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
---
Applies on for-next
arch/arm/mach-omap2/clock34xx.c | 351 ++++++++++++++++++++-------------------
1 files changed, 180 insertions(+), 171 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index c258f87..9ac5c0e 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -93,140 +93,143 @@ struct omap_clk {
#define CK_343X (1 << 0)
#define CK_3430ES1 (1 << 1)
#define CK_3430ES2 (1 << 2)
+#define CK_3517 (1 << 3)
+#define CK_3505 (1 << 4)
+#define CK_35XX (CK_3517 | CK_3505)
static struct omap_clk omap34xx_clks[] = {
- CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
- CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
- CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
- CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
- CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
- CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
- CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
- CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
- CLK(NULL, "sys_ck", &sys_ck, CK_343X),
- CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
- CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
- CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
- CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
- CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
- CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
+ CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X | CK_35XX),
+ CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X | CK_35XX),
+ CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X | CK_35XX),
+ CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_35XX),
+ CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X | CK_35XX),
+ CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X | CK_35XX),
+ CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X | CK_35XX),
+ CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X | CK_35XX),
+ CLK(NULL, "sys_ck", &sys_ck, CK_343X | CK_35XX),
+ CLK(NULL, "sys_altclk", &sys_altclk, CK_343X | CK_35XX),
+ CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X | CK_35XX),
+ CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X | CK_35XX),
+ CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X | CK_35XX),
CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
- CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
- CLK(NULL, "core_ck", &core_ck, CK_343X),
- CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
- CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
- CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
- CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
- CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
- CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
- CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
- CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
- CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
- CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
- CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
- CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
- CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
- CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
- CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
- CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
- CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
- CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
- CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
- CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
- CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
- CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
- CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
- CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
- CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
- CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
- CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
- CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
- CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
- CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
- CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
- CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
- CLK(NULL, "arm_fck", &arm_fck, CK_343X),
- CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
+ CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X | CK_35XX),
+ CLK(NULL, "core_ck", &core_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X | CK_35XX),
+ CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X | CK_35XX),
+ CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X | CK_35XX),
+ CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X | CK_35XX),
+ CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X | CK_35XX),
+ CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X | CK_35XX),
+ CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_35XX),
+ CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_35XX),
+ CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X | CK_35XX),
+ CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X | CK_35XX),
+ CLK(NULL, "corex2_fck", &corex2_fck, CK_343X | CK_35XX),
+ CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X | CK_35XX),
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_343X | CK_35XX),
+ CLK(NULL, "arm_fck", &arm_fck, CK_343X | CK_35XX),
+ CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X | CK_35XX),
CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
- CLK(NULL, "l3_ick", &l3_ick, CK_343X),
- CLK(NULL, "l4_ick", &l4_ick, CK_343X),
- CLK(NULL, "rm_ick", &rm_ick, CK_343X),
+ CLK(NULL, "l3_ick", &l3_ick, CK_343X | CK_35XX),
+ CLK(NULL, "l4_ick", &l4_ick, CK_343X | CK_35XX),
+ CLK(NULL, "rm_ick", &rm_ick, CK_343X | CK_35XX),
CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
- CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
- CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
+ CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
+ CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
CLK(NULL, "modem_fck", &modem_fck, CK_343X),
CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
- CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
- CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
- CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
- CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
- CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
- CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
- CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
- CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
+ CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X | CK_35XX),
+ CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_35XX),
+ CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_35XX),
+ CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_35XX),
+ CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X | CK_35XX),
+ CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_35XX),
+ CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X | CK_35XX),
CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
- CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
- CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
- CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
- CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
- CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
- CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
- CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
- CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
- CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
- CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
+ CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X | CK_35XX),
+ CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X | CK_35XX),
+ CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X | CK_35XX),
+ CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X | CK_35XX),
+ CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X | CK_35XX),
+ CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X | CK_35XX),
+ CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X | CK_35XX),
+ CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X | CK_35XX),
+ CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X | CK_35XX),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_343X | CK_35XX),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_343X | CK_35XX),
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
- CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
- CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
+ CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X | CK_35XX),
+ CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X | CK_35XX),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
- CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
+ CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X | CK_35XX),
CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
- CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
- CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
+ CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X | CK_35XX),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
CLK(NULL, "pka_ick", &pka_ick, CK_343X),
- CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
- CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
- CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
+ CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X | CK_35XX),
+ CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_35XX),
+ CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_35XX),
CLK(NULL, "icr_ick", &icr_ick, CK_343X),
CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
CLK(NULL, "des2_ick", &des2_ick, CK_343X),
- CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
- CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
+ CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X | CK_35XX),
+ CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X | CK_35XX),
CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
- CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
- CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
- CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
- CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
- CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
- CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
- CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
- CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
- CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
- CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
- CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
- CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
- CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
- CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X | CK_35XX),
+ CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X | CK_35XX),
+ CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X | CK_35XX),
+ CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X | CK_35XX),
+ CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X | CK_35XX),
+ CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X | CK_35XX),
+ CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X | CK_35XX),
+ CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X | CK_35XX),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_343X | CK_35XX),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X | CK_35XX),
CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
- CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
+ CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X | CK_35XX),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
@@ -237,83 +240,83 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
CLK(NULL, "des1_ick", &des1_ick, CK_343X),
CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
- CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
- CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
- CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
- CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
+ CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_35XX),
+ CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X | CK_35XX),
+ CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X | CK_35XX),
+ CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X | CK_35XX),
CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1),
- CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2),
+ CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_35XX),
CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
CLK(NULL, "cam_ick", &cam_ick, CK_343X),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
- CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
- CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
- CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
+ CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_35XX),
+ CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_35XX),
+ CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_35XX),
CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
- CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
- CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
- CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
- CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
- CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
+ CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X | CK_35XX),
+ CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X | CK_35XX),
+ CLK("omap_wdt", "fck", &wdt2_fck, CK_343X | CK_35XX),
+ CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X | CK_35XX),
CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
- CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
- CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
- CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
- CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
- CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
- CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
- CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
- CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
- CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
- CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
- CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
- CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
- CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
- CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
- CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
- CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
- CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
- CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
- CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
- CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
- CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
- CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
- CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
- CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
- CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
- CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
- CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
- CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
- CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
- CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
- CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
- CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
- CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
- CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
- CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
- CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
- CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
- CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
- CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
- CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
- CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
- CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
- CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
- CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
- CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
- CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
- CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
- CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
- CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
- CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
- CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
+ CLK("omap_wdt", "ick", &wdt2_ick, CK_343X | CK_35XX),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X | CK_35XX),
+ CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X | CK_35XX),
+ CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X | CK_35XX),
+ CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X | CK_35XX),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X | CK_35XX),
+ CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X | CK_35XX),
+ CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X | CK_35XX),
+ CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X | CK_35XX),
+ CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X | CK_35XX),
+ CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X | CK_35XX),
+ CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X | CK_35XX),
+ CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X | CK_35XX),
+ CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X | CK_35XX),
+ CLK(NULL, "uart3_ick", &uart3_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X | CK_35XX),
+ CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X | CK_35XX),
+ CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X | CK_35XX),
+ CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X | CK_35XX),
+ CLK(NULL, "pclk_fck", &pclk_fck, CK_343X | CK_35XX),
+ CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X | CK_35XX),
+ CLK(NULL, "atclk_fck", &atclk_fck, CK_343X | CK_35XX),
+ CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X | CK_35XX),
+ CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X | CK_35XX),
CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
- CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
- CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
- CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
+ CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X | CK_35XX),
+ CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X | CK_35XX),
+ CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X | CK_35XX),
};
/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
@@ -1120,7 +1123,13 @@ int __init omap2_clk_init(void)
/* u32 clkrate; */
u32 cpu_clkflg;
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap3517()) {
+ cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
+ cpu_clkflg = CK_3517;
+ } else if (cpu_is_omap3505()) {
+ cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
+ cpu_clkflg = CK_3505;
+ } else if (cpu_is_omap34xx()) {
cpu_mask = RATE_IN_343X;
cpu_clkflg = CK_343X;
--
1.6.2.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* RE: [PATCH] AM35xx: Clock table updates for AM3505/17
2009-11-05 10:39 [PATCH] AM35xx: Clock table updates for AM3505/17 Ranjith Lohithakshan
@ 2009-11-05 16:24 ` Menon, Nishanth
2009-11-05 16:26 ` Gadiyar, Anand
2009-11-06 9:22 ` Lohithakshan, Ranjith
2009-11-11 21:43 ` Kevin Hilman
1 sibling, 2 replies; 8+ messages in thread
From: Menon, Nishanth @ 2009-11-05 16:24 UTC (permalink / raw)
To: linux-omap; +Cc: Lohithakshan, Ranjith
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Ranjith Lohithakshan
> Sent: Thursday, November 05, 2009 2:39 AM
[...]
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-
> omap2/clock34xx.c
> index c258f87..9ac5c0e 100644
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -93,140 +93,143 @@ struct omap_clk {
> #define CK_343X (1 << 0)
> #define CK_3430ES1 (1 << 1)
> #define CK_3430ES2 (1 << 2)
> +#define CK_3517 (1 << 3)
> +#define CK_3505 (1 << 4)
> +#define CK_35XX (CK_3517 | CK_3505)
>
> static struct omap_clk omap34xx_clks[] = {
> - CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
> - CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
> - CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
> - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
> - CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
> - CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
> - CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
> - CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
> - CLK(NULL, "sys_ck", &sys_ck, CK_343X),
> - CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
> - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
> - CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
> - CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
> - CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
> - CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
> + CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X | CK_35XX),
> + CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X | CK_35XX),
> + CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X | CK_35XX),
> + CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_35XX),
> + CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X | CK_35XX),
> + CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X | CK_35XX),
[...]
Could we have CK_3XXX? I mean this would probably happen when 36/37xx gets
introduced also.. does that make sense?
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] AM35xx: Clock table updates for AM3505/17
2009-11-05 16:24 ` Menon, Nishanth
@ 2009-11-05 16:26 ` Gadiyar, Anand
2009-11-06 11:19 ` Lohithakshan, Ranjith
2009-11-06 9:22 ` Lohithakshan, Ranjith
1 sibling, 1 reply; 8+ messages in thread
From: Gadiyar, Anand @ 2009-11-05 16:26 UTC (permalink / raw)
To: Menon, Nishanth, Lohithakshan, Ranjith, linux-omap
Nishanth Menon wrote:
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> > owner@vger.kernel.org] On Behalf Of Ranjith Lohithakshan
> > Sent: Thursday, November 05, 2009 2:39 AM
> [...]
> > diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-
> > omap2/clock34xx.c
> > index c258f87..9ac5c0e 100644
> > --- a/arch/arm/mach-omap2/clock34xx.c
> > +++ b/arch/arm/mach-omap2/clock34xx.c
> > @@ -93,140 +93,143 @@ struct omap_clk {
> > #define CK_343X (1 << 0)
> > #define CK_3430ES1 (1 << 1)
> > #define CK_3430ES2 (1 << 2)
> > +#define CK_3517 (1 << 3)
> > +#define CK_3505 (1 << 4)
> > +#define CK_35XX (CK_3517 | CK_3505)
> >
> > static struct omap_clk omap34xx_clks[] = {
> > - CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
> > - CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
> > - CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
> > - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
Just something that I thought of when I saw this line.
Do we still support OMAP3430 ES1.0 silicon? I don't know if any of
these boards exist in the wild and if they still work with current code.
If we don't mind dropping support for these boards, then maybe we
could remove the *3430ES2* flags and cut down on some code?
Just a thought.
- Anand
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] AM35xx: Clock table updates for AM3505/17
2009-11-05 16:24 ` Menon, Nishanth
2009-11-05 16:26 ` Gadiyar, Anand
@ 2009-11-06 9:22 ` Lohithakshan, Ranjith
2009-11-12 12:08 ` Paul Walmsley
1 sibling, 1 reply; 8+ messages in thread
From: Lohithakshan, Ranjith @ 2009-11-06 9:22 UTC (permalink / raw)
To: Menon, Nishanth, linux-omap; +Cc: Paul Walmsley
> -----Original Message-----
> From: Menon, Nishanth
> Sent: Thursday, November 05, 2009 9:55 PM
> To: Lohithakshan, Ranjith; linux-omap@vger.kernel.org
> Cc: Lohithakshan, Ranjith
> Subject: RE: [PATCH] AM35xx: Clock table updates for AM3505/17
>
> > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> > owner@vger.kernel.org] On Behalf Of Ranjith Lohithakshan
> > Sent: Thursday, November 05, 2009 2:39 AM
> [...]
> > diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-
> > omap2/clock34xx.c
> > index c258f87..9ac5c0e 100644
> > --- a/arch/arm/mach-omap2/clock34xx.c
> > +++ b/arch/arm/mach-omap2/clock34xx.c
> > @@ -93,140 +93,143 @@ struct omap_clk {
> > #define CK_343X (1 << 0)
> > #define CK_3430ES1 (1 << 1)
> > #define CK_3430ES2 (1 << 2)
> > +#define CK_3517 (1 << 3)
> > +#define CK_3505 (1 << 4)
> > +#define CK_35XX (CK_3517 | CK_3505)
> >
> > static struct omap_clk omap34xx_clks[] = {
> > - CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
> > - CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
> > - CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
> > - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
> > - CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
> > - CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
> > - CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
> > - CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
> > - CLK(NULL, "sys_ck", &sys_ck, CK_343X),
> > - CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
> > - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
> > - CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
> > - CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
> > - CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
> > - CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
> > + CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X | CK_35XX),
> > + CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X | CK_35XX),
> > + CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X | CK_35XX),
> > + CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_35XX),
> > + CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X | CK_35XX),
> > + CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X | CK_35XX),
> [...]
> Could we have CK_3XXX? I mean this would probably happen when 36/37xx gets
> introduced also.. does that make sense?
>
Yes, it would help to have a CK_3XXX defined to cover all common OMAP3 clocks.
The tables would look simpler going forward.
Paul, what do you think?
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] AM35xx: Clock table updates for AM3505/17
2009-11-05 16:26 ` Gadiyar, Anand
@ 2009-11-06 11:19 ` Lohithakshan, Ranjith
0 siblings, 0 replies; 8+ messages in thread
From: Lohithakshan, Ranjith @ 2009-11-06 11:19 UTC (permalink / raw)
To: Gadiyar, Anand, Menon, Nishanth, linux-omap
> -----Original Message-----
> From: Gadiyar, Anand
> Sent: Thursday, November 05, 2009 9:56 PM
> To: Menon, Nishanth; Lohithakshan, Ranjith; linux-omap@vger.kernel.org
> Subject: RE: [PATCH] AM35xx: Clock table updates for AM3505/17
>
> Nishanth Menon wrote:
> > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> > > owner@vger.kernel.org] On Behalf Of Ranjith Lohithakshan
> > > Sent: Thursday, November 05, 2009 2:39 AM
> > [...]
> > > diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-
> > > omap2/clock34xx.c
> > > index c258f87..9ac5c0e 100644
> > > --- a/arch/arm/mach-omap2/clock34xx.c
> > > +++ b/arch/arm/mach-omap2/clock34xx.c
> > > @@ -93,140 +93,143 @@ struct omap_clk {
> > > #define CK_343X (1 << 0)
> > > #define CK_3430ES1 (1 << 1)
> > > #define CK_3430ES2 (1 << 2)
> > > +#define CK_3517 (1 << 3)
> > > +#define CK_3505 (1 << 4)
> > > +#define CK_35XX (CK_3517 | CK_3505)
> > >
> > > static struct omap_clk omap34xx_clks[] = {
> > > - CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
> > > - CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
> > > - CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
> > > - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
>
> Just something that I thought of when I saw this line.
>
> Do we still support OMAP3430 ES1.0 silicon? I don't know if any of
> these boards exist in the wild and if they still work with current code.
>
> If we don't mind dropping support for these boards, then maybe we
> could remove the *3430ES2* flags and cut down on some code?
>
> Just a thought.
>
On OMAP3530, I know the support is from ES2.1 onwards only. If there is a wider
agreement to drop ES1.0 support, the changes you are recommending can be
taken up in a separate patch
Ranjith
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] AM35xx: Clock table updates for AM3505/17
2009-11-05 10:39 [PATCH] AM35xx: Clock table updates for AM3505/17 Ranjith Lohithakshan
2009-11-05 16:24 ` Menon, Nishanth
@ 2009-11-11 21:43 ` Kevin Hilman
2009-11-12 5:06 ` Lohithakshan, Ranjith
1 sibling, 1 reply; 8+ messages in thread
From: Kevin Hilman @ 2009-11-11 21:43 UTC (permalink / raw)
To: Ranjith Lohithakshan; +Cc: linux-omap
Ranjith Lohithakshan <ranjithl@ti.com> writes:
> AM3505/17 though a OMAP3530 derivative have the following
> main differences
>
> - Removal of the following OMAP3 modules
> - IVA
> - ISP/CAM
> - Modem and D2D components (MAD2D, SAD2D)
> - USIM
> - SSI
> - Mailboxes
> - USB OTG
> - ICR
> - MSPRO
> - SmartReflex
> - SDRC replaced with EMIF4 Controller in the SDRC subsystem
> thus adding support for DDR2 memory devices
> - Addition of the following new modules
> - Ethernet MAC (CPGMAC)
> - CAN Controller (HECC)
> - New USB OTG Controller with integrated Phy
> - Video Processing Front End (VPFE)
> - Additional UART (UART4)
> - All security accelerators disabled on GP devices and not to
> be accessed or configured
>
> This patch defines CPU flags for AM3505/17 and update the clock table.
> Clock support for new modules will be added by subsequent patches.
>
> Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
A question on the approach here, as I'm wondering if this approach is
really needed.
Rather than handling these details in the clock tree, why not handle
the special cases using the feature checks: omap_has_*().
Kevin
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] AM35xx: Clock table updates for AM3505/17
2009-11-11 21:43 ` Kevin Hilman
@ 2009-11-12 5:06 ` Lohithakshan, Ranjith
0 siblings, 0 replies; 8+ messages in thread
From: Lohithakshan, Ranjith @ 2009-11-12 5:06 UTC (permalink / raw)
To: Kevin Hilman; +Cc: linux-omap
Hello Kevin,
> -----Original Message-----
> From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
> Sent: Thursday, November 12, 2009 3:13 AM
> To: Lohithakshan, Ranjith
> Cc: linux-omap@vger.kernel.org
> Subject: Re: [PATCH] AM35xx: Clock table updates for AM3505/17
>
> Ranjith Lohithakshan <ranjithl@ti.com> writes:
>
> > AM3505/17 though a OMAP3530 derivative have the following
> > main differences
> >
> > - Removal of the following OMAP3 modules
> > - IVA
> > - ISP/CAM
> > - Modem and D2D components (MAD2D, SAD2D)
> > - USIM
> > - SSI
> > - Mailboxes
> > - USB OTG
> > - ICR
> > - MSPRO
> > - SmartReflex
> > - SDRC replaced with EMIF4 Controller in the SDRC subsystem
> > thus adding support for DDR2 memory devices
> > - Addition of the following new modules
> > - Ethernet MAC (CPGMAC)
> > - CAN Controller (HECC)
> > - New USB OTG Controller with integrated Phy
> > - Video Processing Front End (VPFE)
> > - Additional UART (UART4)
> > - All security accelerators disabled on GP devices and not to
> > be accessed or configured
> >
> > This patch defines CPU flags for AM3505/17 and update the
> clock table.
> > Clock support for new modules will be added by subsequent patches.
> >
> > Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
>
> A question on the approach here, as I'm wondering if this approach is
> really needed.
>
> Rather than handling these details in the clock tree, why not handle
> the special cases using the feature checks: omap_has_*().
>
The differences (mainly removals) are many and too unique to AM3517/05.
As per the chip spec, the clock related registers for the removed modules are
not to be programmed and we need a way to prevent these clocks getting
registered from the existing table (even if they are not enabled or used later).
In my opinion, if we define feature macros for modules like (MSPRO, USIM,Mailbox etc)
they will be too specific for the AM35xx use. Taking these aspects into
consideration, I feel tha defining CK_35XX flags and using it in clock table appear
to be better.
Ranjith
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] AM35xx: Clock table updates for AM3505/17
2009-11-06 9:22 ` Lohithakshan, Ranjith
@ 2009-11-12 12:08 ` Paul Walmsley
0 siblings, 0 replies; 8+ messages in thread
From: Paul Walmsley @ 2009-11-12 12:08 UTC (permalink / raw)
To: Lohithakshan, Ranjith; +Cc: Menon, Nishanth, linux-omap
On Fri, 6 Nov 2009, Lohithakshan, Ranjith wrote:
> > -----Original Message-----
> > From: Menon, Nishanth
> > Sent: Thursday, November 05, 2009 9:55 PM
...
> > > + CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X | CK_35XX),
> > > + CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_35XX),
> > > + CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X | CK_35XX),
> > > + CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X | CK_35XX),
> > [...]
> > Could we have CK_3XXX? I mean this would probably happen when 36/37xx gets
> > introduced also.. does that make sense?
> >
> Yes, it would help to have a CK_3XXX defined to cover all common OMAP3 clocks.
> The tables would look simpler going forward.
>
> Paul, what do you think?
Sounds like a good idea to me.
- Paul
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2009-11-12 12:08 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-11-05 10:39 [PATCH] AM35xx: Clock table updates for AM3505/17 Ranjith Lohithakshan
2009-11-05 16:24 ` Menon, Nishanth
2009-11-05 16:26 ` Gadiyar, Anand
2009-11-06 11:19 ` Lohithakshan, Ranjith
2009-11-06 9:22 ` Lohithakshan, Ranjith
2009-11-12 12:08 ` Paul Walmsley
2009-11-11 21:43 ` Kevin Hilman
2009-11-12 5:06 ` Lohithakshan, Ranjith
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.