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dkim=none (message not signed) header.d=none;amd.com; dmarc=none action=none header.from=amd.com; Received: from DM6PR12MB3561.namprd12.prod.outlook.com (2603:10b6:5:3e::26) by DM6PR12MB4283.namprd12.prod.outlook.com (2603:10b6:5:211::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.19; Thu, 6 Aug 2020 18:18:05 +0000 Received: from DM6PR12MB3561.namprd12.prod.outlook.com ([fe80::6df0:61cb:d37:2a0b]) by DM6PR12MB3561.namprd12.prod.outlook.com ([fe80::6df0:61cb:d37:2a0b%6]) with mapi id 15.20.3239.022; Thu, 6 Aug 2020 18:18:05 +0000 Subject: Re: [PATCH 2/7] drm/amd/display: Reset plane when tiling flags change To: Rodrigo Siqueira References: <20200730203642.17553-1-nicholas.kazlauskas@amd.com> <20200730203642.17553-3-nicholas.kazlauskas@amd.com> <20200805211114.m5iw6f5usj2b2yrt@outlook.office365.com> From: "Kazlauskas, Nicholas" Message-ID: <1261225a-9ce1-0f21-ca93-f51282b47cf6@amd.com> Date: Thu, 6 Aug 2020 14:18:01 -0400 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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charset="us-ascii"; Format="flowed" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2020-08-05 5:11 p.m., Rodrigo Siqueira wrote: > On 07/30, Nicholas Kazlauskas wrote: >> [Why] >> Enabling or disable DCC or switching between tiled and linear formats >> can require bandwidth updates. >> >> They're currently skipping all DC validation by being treated as purely >> surface updates. >> >> [How] >> Treat tiling_flag changes (which encode DCC state) as a condition for >> resetting the plane. >> >> Cc: Bhawanpreet Lakha >> Cc: Rodrigo Siqueira >> Cc: Hersen Wu >> Signed-off-by: Nicholas Kazlauskas >> --- >> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 ++++++++++++++++--- >> 1 file changed, 16 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> index 7cc5ab90ce13..bf1881bd492c 100644 >> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> @@ -8332,6 +8332,8 @@ static bool should_reset_plane(struct drm_atomic_state *state, >> * TODO: Come up with a more elegant solution for this. >> */ >> for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { >> + struct dm_plane_state *old_dm_plane_state, *new_dm_plane_state; >> + >> if (other->type == DRM_PLANE_TYPE_CURSOR) >> continue; >> >> @@ -8342,9 +8344,20 @@ static bool should_reset_plane(struct drm_atomic_state *state, >> if (old_other_state->crtc != new_other_state->crtc) >> return true; >> >> - /* TODO: Remove this once we can handle fast format changes. */ >> - if (old_other_state->fb && new_other_state->fb && >> - old_other_state->fb->format != new_other_state->fb->format) >> + /* Framebuffer checks fall at the end. */ >> + if (!old_other_state->fb || !new_other_state->fb) >> + continue; >> + >> + /* Pixel format changes can require bandwidth updates. */ >> + if (old_other_state->fb->format != new_other_state->fb->format) >> + return true; >> + >> + old_dm_plane_state = to_dm_plane_state(old_other_state); >> + new_dm_plane_state = to_dm_plane_state(new_other_state); >> + >> + /* Tiling and DCC changes also require bandwidth updates. */ >> + if (old_dm_plane_state->tiling_flags != >> + new_dm_plane_state->tiling_flags) > > Why not add a case when we move to a TMZ area? > > Reviewed-by: Rodrigo Siqueira TMZ doesn't affect DML calculations or validation in this case so we can safely skip it. Regards, Nicholas Kazlauskas > >> return true; >> } >> >> -- >> 2.25.1 >> > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 616D5C433E0 for ; Thu, 6 Aug 2020 18:18:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A914522CBB for ; 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dkim=none (message not signed) header.d=none;amd.com; dmarc=none action=none header.from=amd.com; Received: from DM6PR12MB3561.namprd12.prod.outlook.com (2603:10b6:5:3e::26) by DM6PR12MB4283.namprd12.prod.outlook.com (2603:10b6:5:211::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.19; Thu, 6 Aug 2020 18:18:05 +0000 Received: from DM6PR12MB3561.namprd12.prod.outlook.com ([fe80::6df0:61cb:d37:2a0b]) by DM6PR12MB3561.namprd12.prod.outlook.com ([fe80::6df0:61cb:d37:2a0b%6]) with mapi id 15.20.3239.022; Thu, 6 Aug 2020 18:18:05 +0000 Subject: Re: [PATCH 2/7] drm/amd/display: Reset plane when tiling flags change To: Rodrigo Siqueira References: <20200730203642.17553-1-nicholas.kazlauskas@amd.com> <20200730203642.17553-3-nicholas.kazlauskas@amd.com> <20200805211114.m5iw6f5usj2b2yrt@outlook.office365.com> From: "Kazlauskas, Nicholas" Message-ID: <1261225a-9ce1-0f21-ca93-f51282b47cf6@amd.com> Date: Thu, 6 Aug 2020 14:18:01 -0400 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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charset="us-ascii"; Format="flowed" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2020-08-05 5:11 p.m., Rodrigo Siqueira wrote: > On 07/30, Nicholas Kazlauskas wrote: >> [Why] >> Enabling or disable DCC or switching between tiled and linear formats >> can require bandwidth updates. >> >> They're currently skipping all DC validation by being treated as purely >> surface updates. >> >> [How] >> Treat tiling_flag changes (which encode DCC state) as a condition for >> resetting the plane. >> >> Cc: Bhawanpreet Lakha >> Cc: Rodrigo Siqueira >> Cc: Hersen Wu >> Signed-off-by: Nicholas Kazlauskas >> --- >> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 ++++++++++++++++--- >> 1 file changed, 16 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> index 7cc5ab90ce13..bf1881bd492c 100644 >> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> @@ -8332,6 +8332,8 @@ static bool should_reset_plane(struct drm_atomic_state *state, >> * TODO: Come up with a more elegant solution for this. >> */ >> for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { >> + struct dm_plane_state *old_dm_plane_state, *new_dm_plane_state; >> + >> if (other->type == DRM_PLANE_TYPE_CURSOR) >> continue; >> >> @@ -8342,9 +8344,20 @@ static bool should_reset_plane(struct drm_atomic_state *state, >> if (old_other_state->crtc != new_other_state->crtc) >> return true; >> >> - /* TODO: Remove this once we can handle fast format changes. */ >> - if (old_other_state->fb && new_other_state->fb && >> - old_other_state->fb->format != new_other_state->fb->format) >> + /* Framebuffer checks fall at the end. */ >> + if (!old_other_state->fb || !new_other_state->fb) >> + continue; >> + >> + /* Pixel format changes can require bandwidth updates. */ >> + if (old_other_state->fb->format != new_other_state->fb->format) >> + return true; >> + >> + old_dm_plane_state = to_dm_plane_state(old_other_state); >> + new_dm_plane_state = to_dm_plane_state(new_other_state); >> + >> + /* Tiling and DCC changes also require bandwidth updates. */ >> + if (old_dm_plane_state->tiling_flags != >> + new_dm_plane_state->tiling_flags) > > Why not add a case when we move to a TMZ area? > > Reviewed-by: Rodrigo Siqueira TMZ doesn't affect DML calculations or validation in this case so we can safely skip it. Regards, Nicholas Kazlauskas > >> return true; >> } >> >> -- >> 2.25.1 >> > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx