From mboxrd@z Thu Jan 1 00:00:00 1970 From: jamal Subject: Re: rps perfomance WAS(Re: rps: question Date: Fri, 16 Apr 2010 09:27:35 -0400 Message-ID: <1271424455.4606.39.camel@bigi> References: <1271268242.16881.1719.camel@edumazet-laptop> <1271271222.4567.51.camel@bigi> <20100415.014857.168270765.davem@davemloft.net> <1271332528.4567.150.camel@bigi> <4BC741AE.3000108@hp.com> <1271362581.23780.12.camel@bigi> <1271395106.16881.3645.camel@edumazet-laptop> <20100416071522.GY18855@one.firstfloor.org> Reply-To: hadi@cyberus.ca Mime-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 7bit Cc: Changli Gao , Eric Dumazet , Rick Jones , David Miller , therbert@google.com, netdev@vger.kernel.org, robert@herjulf.net To: Andi Kleen Return-path: Received: from mail-qy0-f196.google.com ([209.85.221.196]:56908 "EHLO mail-qy0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753120Ab0DPN1s (ORCPT ); Fri, 16 Apr 2010 09:27:48 -0400 Received: by qyk34 with SMTP id 34so3279429qyk.22 for ; Fri, 16 Apr 2010 06:27:47 -0700 (PDT) In-Reply-To: <20100416071522.GY18855@one.firstfloor.org> Sender: netdev-owner@vger.kernel.org List-ID: On Fri, 2010-04-16 at 09:15 +0200, Andi Kleen wrote: > > resched IPI, apparently. But it is async absolutely. and its IRQ > > handler is lighter. > > It shouldn't be a lot lighter than the new fancy "queued smp_call_function" > that's in the tree for a few releases. So it would surprise me if it made > much difference. In the old days when there was only a single lock for > s_c_f() perhaps... So you are saying that the old implementation of IPI (likely what i tried pre-napi and as recent as 2-3 years ago) was bad because of a single lock? BTW, I directed some questions to you earlier but didnt get a response, to quote: --- On IPIs: Is anyone familiar with what is going on with Nehalem? Why is it this good? I expect things will get a lot nastier with other hardware like xeon based or even Nehalem with rps going across QPI. Here's why i think IPIs are bad, please correct me if i am wrong: - they are synchronous. i.e an IPI issuer has to wait for an ACK (which is in the form of an IPI). - data cache has to be synced to main memory - the instruction pipeline is flushed - what else did i miss? Andi? --- Do you know any specs i could read up which will tell me a little more? cheers, jamal