From mboxrd@z Thu Jan 1 00:00:00 1970 From: Steve Sakoman Date: Wed, 18 Aug 2010 20:30:07 -0700 Subject: [U-Boot] [PATCH 3/3] omap2: i2c: remove redundant header definitions In-Reply-To: <1282178349-24593-4-git-send-email-nm@ti.com> References: <1282178349-24593-4-git-send-email-nm@ti.com> Message-ID: <1282188607.2052.85.camel@quadra> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, 2010-08-18 at 19:39 -0500, Nishanth Menon wrote: > Remove the register offset and common defines which are > already present in drivers/i2c/omap24xx.h. All of these > defines carry the same value even. > > Cc: Steve Sakoman > Cc: Heiko > Cc: Sandeep Paulraj > Cc: Wolfang Denk > > Signed-off-by: Nishanth Menon Acked-by: Steve Sakoman Steve > --- > arch/arm/include/asm/arch-omap24xx/i2c.h | 106 ------------------------------ > 1 files changed, 0 insertions(+), 106 deletions(-) > > diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h > index 418a432..6f64519 100644 > --- a/arch/arm/include/asm/arch-omap24xx/i2c.h > +++ b/arch/arm/include/asm/arch-omap24xx/i2c.h > @@ -65,110 +65,4 @@ struct i2c { > > #define I2C_BUS_MAX 2 > > -/* I2C masks */ > - > -/* I2C Interrupt Enable Register (I2C_IE): */ > -#define I2C_IE_GC_IE (1 << 5) > -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ > -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ > -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ > -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ > -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ > - > -/* I2C Status Register (I2C_STAT): */ > - > -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ > -#define I2C_STAT_BB (1 << 12) /* Bus busy */ > -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ > -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ > -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ > -#define I2C_STAT_GC (1 << 5) > -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ > -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ > -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ > -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ > -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ > - > - > -/* I2C Interrupt Code Register (I2C_INTCODE): */ > - > -#define I2C_INTCODE_MASK 7 > -#define I2C_INTCODE_NONE 0 > -#define I2C_INTCODE_AL 1 /* Arbitration lost */ > -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ > -#define I2C_INTCODE_ARDY 3 /* Register access ready */ > -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ > -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ > - > -/* I2C Buffer Configuration Register (I2C_BUF): */ > - > -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ > -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ > - > -/* I2C Configuration Register (I2C_CON): */ > - > -#define I2C_CON_EN (1 << 15) /* I2C module enable */ > -#define I2C_CON_BE (1 << 14) /* Big endian mode */ > -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ > -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ > -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ > -#define I2C_CON_XA (1 << 8) /* Expand address */ > -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ > -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ > - > -/* I2C System Test Register (I2C_SYSTEST): */ > - > -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ > -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ > -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ > -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ > -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ > -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ > -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ > -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ > - > -/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */ > -#define OMAP_I2C_STANDARD 100000 > -#define OMAP_I2C_FAST_MODE 400000 > -#define OMAP_I2C_HIGH_SPEED 3400000 > - > -#define SYSTEM_CLOCK_12 12000000 > -#define SYSTEM_CLOCK_13 13000000 > -#define SYSTEM_CLOCK_192 19200000 > -#define SYSTEM_CLOCK_96 96000000 > - > -#ifndef I2C_IP_CLK > -#define I2C_IP_CLK SYSTEM_CLOCK_96 > -#endif > - > -#ifndef I2C_INTERNAL_SAMPLING_CLK > -#define I2C_INTERNAL_SAMPLING_CLK 19200000 > -#endif > - > -/* These are the trim values for standard and fast speed */ > -#ifndef I2C_FASTSPEED_SCLL_TRIM > -#define I2C_FASTSPEED_SCLL_TRIM 6 > -#endif > -#ifndef I2C_FASTSPEED_SCLH_TRIM > -#define I2C_FASTSPEED_SCLH_TRIM 6 > -#endif > - > -/* These are the trim values for high speed */ > -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM > -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM > -#endif > -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM > -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM > -#endif > -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM > -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM > -#endif > -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM > -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM > -#endif > - > -#define I2C_PSC_MAX 0x0f > -#define I2C_PSC_MIN 0x00 > - > - > #endif