From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eduard - Gabriel Munteanu Subject: [PATCH 6/7] eepro100: use the PCI memory access interface Date: Sat, 28 Aug 2010 17:54:57 +0300 Message-ID: <1283007298-10942-7-git-send-email-eduard.munteanu@linux360.ro> References: <1283007298-10942-1-git-send-email-eduard.munteanu@linux360.ro> Cc: joro@8bytes.org, blauwirbel@gmail.com, paul@codesourcery.com, avi@redhat.com, anthony@codemonkey.ws, av1474@comtv.ru, yamahata@valinux.co.jp, kvm@vger.kernel.org, qemu-devel@nongnu.org, Eduard - Gabriel Munteanu To: mst@redhat.com Return-path: Received: from mail-bw0-f46.google.com ([209.85.214.46]:38181 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751887Ab0H1O44 (ORCPT ); Sat, 28 Aug 2010 10:56:56 -0400 Received: by mail-bw0-f46.google.com with SMTP id 11so2651956bwz.19 for ; Sat, 28 Aug 2010 07:56:56 -0700 (PDT) In-Reply-To: <1283007298-10942-1-git-send-email-eduard.munteanu@linux360.ro> Sender: kvm-owner@vger.kernel.org List-ID: This allows the device to work properly with an emulated IOMMU. Signed-off-by: Eduard - Gabriel Munteanu --- hw/eepro100.c | 86 ++++++++++++++++++++++++++++++-------------------------- 1 files changed, 46 insertions(+), 40 deletions(-) diff --git a/hw/eepro100.c b/hw/eepro100.c index 2b75c8f..5b7d82a 100644 --- a/hw/eepro100.c +++ b/hw/eepro100.c @@ -306,10 +306,10 @@ static const uint16_t eepro100_mdi_mask[] = { }; /* XXX: optimize */ -static void stl_le_phys(target_phys_addr_t addr, uint32_t val) +static void stl_le_phys(EEPRO100State * s, pcibus_t addr, uint32_t val) { val = cpu_to_le32(val); - cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val)); + pci_memory_write(&s->dev, addr, (const uint8_t *)&val, sizeof(val)); } #define POLYNOMIAL 0x04c11db6 @@ -692,12 +692,12 @@ static void dump_statistics(EEPRO100State * s) * values which really matter. * Number of data should check configuration!!! */ - cpu_physical_memory_write(s->statsaddr, - (uint8_t *) & s->statistics, s->stats_size); - stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames); - stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames); - stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); - stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); + pci_memory_write(&s->dev, s->statsaddr, + (uint8_t *) & s->statistics, s->stats_size); + stl_le_phys(s, s->statsaddr + 0, s->statistics.tx_good_frames); + stl_le_phys(s, s->statsaddr + 36, s->statistics.rx_good_frames); + stl_le_phys(s, s->statsaddr + 48, s->statistics.rx_resource_errors); + stl_le_phys(s, s->statsaddr + 60, s->statistics.rx_short_frame_errors); #if 0 stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); @@ -707,7 +707,8 @@ static void dump_statistics(EEPRO100State * s) static void read_cb(EEPRO100State *s) { - cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx)); + pci_memory_read(&s->dev, + s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx)); s->tx.status = le16_to_cpu(s->tx.status); s->tx.command = le16_to_cpu(s->tx.command); s->tx.link = le32_to_cpu(s->tx.link); @@ -737,18 +738,18 @@ static void tx_command(EEPRO100State *s) } assert(tcb_bytes <= sizeof(buf)); while (size < tcb_bytes) { - uint32_t tx_buffer_address = ldl_phys(tbd_address); - uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); + uint32_t tx_buffer_address = pci_ldl(&s->dev, tbd_address); + uint16_t tx_buffer_size = pci_lduw(&s->dev, tbd_address + 4); #if 0 - uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); + uint16_t tx_buffer_el = pci_lduw(&s->dev, tbd_address + 6); #endif tbd_address += 8; TRACE(RXTX, logout ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", tx_buffer_address, tx_buffer_size)); tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); - cpu_physical_memory_read(tx_buffer_address, &buf[size], - tx_buffer_size); + pci_memory_read(&s->dev, + tx_buffer_address, &buf[size], tx_buffer_size); size += tx_buffer_size; } if (tbd_array == 0xffffffff) { @@ -759,16 +760,16 @@ static void tx_command(EEPRO100State *s) if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { /* Extended Flexible TCB. */ for (; tbd_count < 2; tbd_count++) { - uint32_t tx_buffer_address = ldl_phys(tbd_address); - uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); - uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); + uint32_t tx_buffer_address = pci_ldl(&s->dev, tbd_address); + uint16_t tx_buffer_size = pci_lduw(&s->dev, tbd_address + 4); + uint16_t tx_buffer_el = pci_lduw(&s->dev, tbd_address + 6); tbd_address += 8; TRACE(RXTX, logout ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", tx_buffer_address, tx_buffer_size)); tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); - cpu_physical_memory_read(tx_buffer_address, &buf[size], - tx_buffer_size); + pci_memory_read(&s->dev, + tx_buffer_address, &buf[size], tx_buffer_size); size += tx_buffer_size; if (tx_buffer_el & 1) { break; @@ -777,16 +778,16 @@ static void tx_command(EEPRO100State *s) } tbd_address = tbd_array; for (; tbd_count < s->tx.tbd_count; tbd_count++) { - uint32_t tx_buffer_address = ldl_phys(tbd_address); - uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); - uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); + uint32_t tx_buffer_address = pci_ldl(&s->dev, tbd_address); + uint16_t tx_buffer_size = pci_lduw(&s->dev, tbd_address + 4); + uint16_t tx_buffer_el = pci_lduw(&s->dev, tbd_address + 6); tbd_address += 8; TRACE(RXTX, logout ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", tx_buffer_address, tx_buffer_size)); tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); - cpu_physical_memory_read(tx_buffer_address, &buf[size], - tx_buffer_size); + pci_memory_read(&s->dev, + tx_buffer_address, &buf[size], tx_buffer_size); size += tx_buffer_size; if (tx_buffer_el & 1) { break; @@ -811,7 +812,7 @@ static void set_multicast_list(EEPRO100State *s) TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count)); for (i = 0; i < multicast_count; i += 6) { uint8_t multicast_addr[6]; - cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6); + pci_memory_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6); TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6))); unsigned mcast_idx = compute_mcast_idx(multicast_addr); assert(mcast_idx < 64); @@ -845,12 +846,14 @@ static void action_command(EEPRO100State *s) /* Do nothing. */ break; case CmdIASetup: - cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6); + pci_memory_read(&s->dev, + s->cb_address + 8, &s->conf.macaddr.a[0], 6); TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6))); break; case CmdConfigure: - cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0], - sizeof(s->configuration)); + pci_memory_read(&s->dev, + s->cb_address + 8, + &s->configuration[0], sizeof(s->configuration)); TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16))); break; case CmdMulticastList: @@ -880,7 +883,7 @@ static void action_command(EEPRO100State *s) break; } /* Write new status. */ - stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C); + pci_stw(&s->dev, s->cb_address, s->tx.status | ok_status | STATUS_C); if (bit_i) { /* CU completed action. */ eepro100_cx_interrupt(s); @@ -947,7 +950,7 @@ static void eepro100_cu_command(EEPRO100State * s, uint8_t val) /* Dump statistical counters. */ TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); dump_statistics(s); - stl_le_phys(s->statsaddr + s->stats_size, 0xa005); + stl_le_phys(s, s->statsaddr + s->stats_size, 0xa005); break; case CU_CMD_BASE: /* Load CU base. */ @@ -958,7 +961,7 @@ static void eepro100_cu_command(EEPRO100State * s, uint8_t val) /* Dump and reset statistical counters. */ TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); dump_statistics(s); - stl_le_phys(s->statsaddr + s->stats_size, 0xa007); + stl_le_phys(s, s->statsaddr + s->stats_size, 0xa007); memset(&s->statistics, 0, sizeof(s->statistics)); break; case CU_SRESUME: @@ -1259,10 +1262,10 @@ static void eepro100_write_port(EEPRO100State * s, uint32_t val) case PORT_SELFTEST: TRACE(OTHER, logout("selftest address=0x%08x\n", address)); eepro100_selftest_t data; - cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); + pci_memory_read(&s->dev, address, (uint8_t *) & data, sizeof(data)); data.st_sign = 0xffffffff; data.st_result = 0; - cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data)); + pci_memory_write(&s->dev, address, (uint8_t *) & data, sizeof(data)); break; case PORT_SELECTIVE_RESET: TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); @@ -1721,8 +1724,9 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size } /* !!! */ eepro100_rx_t rx; - cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, - offsetof(eepro100_rx_t, packet)); + pci_memory_read(&s->dev, + s->ru_base + s->ru_offset, + (uint8_t *) & rx, offsetof(eepro100_rx_t, packet)); uint16_t rfd_command = le16_to_cpu(rx.command); uint16_t rfd_size = le16_to_cpu(rx.size); @@ -1736,9 +1740,11 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size } TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); - stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), - rfd_status); - stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); + pci_stw(&s->dev, + s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), + rfd_status); + pci_stw(&s->dev, + s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); /* Early receive interrupt not supported. */ #if 0 eepro100_er_interrupt(s); @@ -1752,8 +1758,8 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size #if 0 assert(!(s->configuration[17] & BIT(0))); #endif - cpu_physical_memory_write(s->ru_base + s->ru_offset + - offsetof(eepro100_rx_t, packet), buf, size); + pci_memory_write(&s->dev, s->ru_base + s->ru_offset + + offsetof(eepro100_rx_t, packet), buf, size); s->statistics.rx_good_frames++; eepro100_fr_interrupt(s); s->ru_offset = le32_to_cpu(rx.link); -- 1.7.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=60009 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OpMq2-0008W1-Pd for qemu-devel@nongnu.org; Sat, 28 Aug 2010 10:57:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OpMq0-0000HT-MF for qemu-devel@nongnu.org; Sat, 28 Aug 2010 10:56:58 -0400 Received: from mail-bw0-f45.google.com ([209.85.214.45]:45845) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OpMq0-0000Gc-Cj for qemu-devel@nongnu.org; Sat, 28 Aug 2010 10:56:56 -0400 Received: by mail-bw0-f45.google.com with SMTP id 3so2801900bwz.4 for ; Sat, 28 Aug 2010 07:56:56 -0700 (PDT) Sender: Eduard - Gabriel Munteanu From: Eduard - Gabriel Munteanu Date: Sat, 28 Aug 2010 17:54:57 +0300 Message-Id: <1283007298-10942-7-git-send-email-eduard.munteanu@linux360.ro> In-Reply-To: <1283007298-10942-1-git-send-email-eduard.munteanu@linux360.ro> References: <1283007298-10942-1-git-send-email-eduard.munteanu@linux360.ro> Subject: [Qemu-devel] [PATCH 6/7] eepro100: use the PCI memory access interface List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mst@redhat.com Cc: kvm@vger.kernel.org, joro@8bytes.org, qemu-devel@nongnu.org, blauwirbel@gmail.com, yamahata@valinux.co.jp, paul@codesourcery.com, Eduard - Gabriel Munteanu , avi@redhat.com This allows the device to work properly with an emulated IOMMU. Signed-off-by: Eduard - Gabriel Munteanu --- hw/eepro100.c | 86 ++++++++++++++++++++++++++++++-------------------------- 1 files changed, 46 insertions(+), 40 deletions(-) diff --git a/hw/eepro100.c b/hw/eepro100.c index 2b75c8f..5b7d82a 100644 --- a/hw/eepro100.c +++ b/hw/eepro100.c @@ -306,10 +306,10 @@ static const uint16_t eepro100_mdi_mask[] = { }; /* XXX: optimize */ -static void stl_le_phys(target_phys_addr_t addr, uint32_t val) +static void stl_le_phys(EEPRO100State * s, pcibus_t addr, uint32_t val) { val = cpu_to_le32(val); - cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val)); + pci_memory_write(&s->dev, addr, (const uint8_t *)&val, sizeof(val)); } #define POLYNOMIAL 0x04c11db6 @@ -692,12 +692,12 @@ static void dump_statistics(EEPRO100State * s) * values which really matter. * Number of data should check configuration!!! */ - cpu_physical_memory_write(s->statsaddr, - (uint8_t *) & s->statistics, s->stats_size); - stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames); - stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames); - stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); - stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); + pci_memory_write(&s->dev, s->statsaddr, + (uint8_t *) & s->statistics, s->stats_size); + stl_le_phys(s, s->statsaddr + 0, s->statistics.tx_good_frames); + stl_le_phys(s, s->statsaddr + 36, s->statistics.rx_good_frames); + stl_le_phys(s, s->statsaddr + 48, s->statistics.rx_resource_errors); + stl_le_phys(s, s->statsaddr + 60, s->statistics.rx_short_frame_errors); #if 0 stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); @@ -707,7 +707,8 @@ static void dump_statistics(EEPRO100State * s) static void read_cb(EEPRO100State *s) { - cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx)); + pci_memory_read(&s->dev, + s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx)); s->tx.status = le16_to_cpu(s->tx.status); s->tx.command = le16_to_cpu(s->tx.command); s->tx.link = le32_to_cpu(s->tx.link); @@ -737,18 +738,18 @@ static void tx_command(EEPRO100State *s) } assert(tcb_bytes <= sizeof(buf)); while (size < tcb_bytes) { - uint32_t tx_buffer_address = ldl_phys(tbd_address); - uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); + uint32_t tx_buffer_address = pci_ldl(&s->dev, tbd_address); + uint16_t tx_buffer_size = pci_lduw(&s->dev, tbd_address + 4); #if 0 - uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); + uint16_t tx_buffer_el = pci_lduw(&s->dev, tbd_address + 6); #endif tbd_address += 8; TRACE(RXTX, logout ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", tx_buffer_address, tx_buffer_size)); tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); - cpu_physical_memory_read(tx_buffer_address, &buf[size], - tx_buffer_size); + pci_memory_read(&s->dev, + tx_buffer_address, &buf[size], tx_buffer_size); size += tx_buffer_size; } if (tbd_array == 0xffffffff) { @@ -759,16 +760,16 @@ static void tx_command(EEPRO100State *s) if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { /* Extended Flexible TCB. */ for (; tbd_count < 2; tbd_count++) { - uint32_t tx_buffer_address = ldl_phys(tbd_address); - uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); - uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); + uint32_t tx_buffer_address = pci_ldl(&s->dev, tbd_address); + uint16_t tx_buffer_size = pci_lduw(&s->dev, tbd_address + 4); + uint16_t tx_buffer_el = pci_lduw(&s->dev, tbd_address + 6); tbd_address += 8; TRACE(RXTX, logout ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", tx_buffer_address, tx_buffer_size)); tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); - cpu_physical_memory_read(tx_buffer_address, &buf[size], - tx_buffer_size); + pci_memory_read(&s->dev, + tx_buffer_address, &buf[size], tx_buffer_size); size += tx_buffer_size; if (tx_buffer_el & 1) { break; @@ -777,16 +778,16 @@ static void tx_command(EEPRO100State *s) } tbd_address = tbd_array; for (; tbd_count < s->tx.tbd_count; tbd_count++) { - uint32_t tx_buffer_address = ldl_phys(tbd_address); - uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); - uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); + uint32_t tx_buffer_address = pci_ldl(&s->dev, tbd_address); + uint16_t tx_buffer_size = pci_lduw(&s->dev, tbd_address + 4); + uint16_t tx_buffer_el = pci_lduw(&s->dev, tbd_address + 6); tbd_address += 8; TRACE(RXTX, logout ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", tx_buffer_address, tx_buffer_size)); tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); - cpu_physical_memory_read(tx_buffer_address, &buf[size], - tx_buffer_size); + pci_memory_read(&s->dev, + tx_buffer_address, &buf[size], tx_buffer_size); size += tx_buffer_size; if (tx_buffer_el & 1) { break; @@ -811,7 +812,7 @@ static void set_multicast_list(EEPRO100State *s) TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count)); for (i = 0; i < multicast_count; i += 6) { uint8_t multicast_addr[6]; - cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6); + pci_memory_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6); TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6))); unsigned mcast_idx = compute_mcast_idx(multicast_addr); assert(mcast_idx < 64); @@ -845,12 +846,14 @@ static void action_command(EEPRO100State *s) /* Do nothing. */ break; case CmdIASetup: - cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6); + pci_memory_read(&s->dev, + s->cb_address + 8, &s->conf.macaddr.a[0], 6); TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6))); break; case CmdConfigure: - cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0], - sizeof(s->configuration)); + pci_memory_read(&s->dev, + s->cb_address + 8, + &s->configuration[0], sizeof(s->configuration)); TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16))); break; case CmdMulticastList: @@ -880,7 +883,7 @@ static void action_command(EEPRO100State *s) break; } /* Write new status. */ - stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C); + pci_stw(&s->dev, s->cb_address, s->tx.status | ok_status | STATUS_C); if (bit_i) { /* CU completed action. */ eepro100_cx_interrupt(s); @@ -947,7 +950,7 @@ static void eepro100_cu_command(EEPRO100State * s, uint8_t val) /* Dump statistical counters. */ TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); dump_statistics(s); - stl_le_phys(s->statsaddr + s->stats_size, 0xa005); + stl_le_phys(s, s->statsaddr + s->stats_size, 0xa005); break; case CU_CMD_BASE: /* Load CU base. */ @@ -958,7 +961,7 @@ static void eepro100_cu_command(EEPRO100State * s, uint8_t val) /* Dump and reset statistical counters. */ TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); dump_statistics(s); - stl_le_phys(s->statsaddr + s->stats_size, 0xa007); + stl_le_phys(s, s->statsaddr + s->stats_size, 0xa007); memset(&s->statistics, 0, sizeof(s->statistics)); break; case CU_SRESUME: @@ -1259,10 +1262,10 @@ static void eepro100_write_port(EEPRO100State * s, uint32_t val) case PORT_SELFTEST: TRACE(OTHER, logout("selftest address=0x%08x\n", address)); eepro100_selftest_t data; - cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); + pci_memory_read(&s->dev, address, (uint8_t *) & data, sizeof(data)); data.st_sign = 0xffffffff; data.st_result = 0; - cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data)); + pci_memory_write(&s->dev, address, (uint8_t *) & data, sizeof(data)); break; case PORT_SELECTIVE_RESET: TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); @@ -1721,8 +1724,9 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size } /* !!! */ eepro100_rx_t rx; - cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, - offsetof(eepro100_rx_t, packet)); + pci_memory_read(&s->dev, + s->ru_base + s->ru_offset, + (uint8_t *) & rx, offsetof(eepro100_rx_t, packet)); uint16_t rfd_command = le16_to_cpu(rx.command); uint16_t rfd_size = le16_to_cpu(rx.size); @@ -1736,9 +1740,11 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size } TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); - stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), - rfd_status); - stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); + pci_stw(&s->dev, + s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), + rfd_status); + pci_stw(&s->dev, + s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); /* Early receive interrupt not supported. */ #if 0 eepro100_er_interrupt(s); @@ -1752,8 +1758,8 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size #if 0 assert(!(s->configuration[17] & BIT(0))); #endif - cpu_physical_memory_write(s->ru_base + s->ru_offset + - offsetof(eepro100_rx_t, packet), buf, size); + pci_memory_write(&s->dev, s->ru_base + s->ru_offset + + offsetof(eepro100_rx_t, packet), buf, size); s->statistics.rx_good_frames++; eepro100_fr_interrupt(s); s->ru_offset = le32_to_cpu(rx.link); -- 1.7.1