From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=48753 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PUn2x-0000CG-E6 for qemu-devel@nongnu.org; Mon, 20 Dec 2010 16:13:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PUn2t-0004nX-I1 for qemu-devel@nongnu.org; Mon, 20 Dec 2010 16:13:31 -0500 Received: from cantor2.suse.de ([195.135.220.15]:43146 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PUn2t-0004n0-42 for qemu-devel@nongnu.org; Mon, 20 Dec 2010 16:13:27 -0500 From: Alexander Graf Date: Mon, 20 Dec 2010 22:13:21 +0100 Message-Id: <1292879604-22268-6-git-send-email-agraf@suse.de> In-Reply-To: <1292879604-22268-1-git-send-email-agraf@suse.de> References: <1292879604-22268-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 5/8] ahci: Implement HBA reset List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel Developers Cc: Kevin Wolf , Joerg Roedel , Gerd Hoffmann , Sebastian Herbszt The ahci code was missing its soft reset functionality. This wasn't really an issue for Linux guests, but Windows gets confused when the controller doesn't reset when it tells it so. Using this patch I can now successfully boot Windows 7 from AHCI using AHCI enabled SeaBIOS. Signed-off-by: Alexander Graf --- hw/ide/ahci.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 7a29925..bd4f8a4 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -332,7 +332,7 @@ static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) case HOST_CTL: /* R/W */ if (val & HOST_CTL_RESET) { DPRINTF(-1, "HBA Reset\n"); - /* FIXME reset? */ + ahci_reset(container_of(s, AHCIPCIState, ahci)); } else { s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; ahci_check_irq(s); @@ -1215,6 +1215,9 @@ void ahci_reset(void *opaque) struct AHCIPCIState *d = opaque; int i; + d->ahci.control_regs.irqstatus = 0; + d->ahci.control_regs.ghc = 0; + for (i = 0; i < SATA_PORTS; i++) { ahci_reset_port(&d->ahci, i); } -- 1.6.0.2