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From:   David Daney <ddaney@caviumnetworks.com>
To:     linux-mips@linux-mips.org, ralf@linux-mips.org
Cc:     David Daney <ddaney@caviumnetworks.com>
Subject: [PATCH 0/3] Allow processors with scratch registers to use them for TLB refill.
Date:   Mon, 20 Dec 2010 13:17:05 -0800
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The MIPS32r2 and MIPS64r2 specifications allow processors to have
scratch registers in coprocessor 0.  If these are present, we can use
one of them to carry the current PGD and save three instructions in
the TLB handlers.

There are three patches:

1 - Probe for presence of scratch registers an print number found in
    /proc/cpuinfo.

2 - Add DINSM to uasm for use by patch 3.

3 - Convert the TLB handlers.  This also involves dynamically
    generating tlbmiss_handler_setup_pgd, which used to be statically
    defined.


David Daney (3):
  MIPS: Probe for presence of KScratch registers.
  MIPS: Add DINSM to uasm.
  MIPS: Use C0_KScratch (if present) to hold PGD pointer.

 arch/mips/include/asm/cpu-info.h    |    1 +
 arch/mips/include/asm/mmu_context.h |    8 +--
 arch/mips/include/asm/uasm.h        |    1 +
 arch/mips/kernel/cpu-probe.c        |    2 +
 arch/mips/kernel/proc.c             |    2 +
 arch/mips/kernel/traps.c            |    2 +-
 arch/mips/mm/tlbex.c                |  110 +++++++++++++++++++++++++++++++---
 arch/mips/mm/uasm.c                 |   11 +++-
 8 files changed, 118 insertions(+), 19 deletions(-)

-- 
1.7.2.3