From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=48460 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PiqbU-0005Oo-O5 for qemu-devel@nongnu.org; Fri, 28 Jan 2011 10:51:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PiqbS-00010a-J4 for qemu-devel@nongnu.org; Fri, 28 Jan 2011 10:51:16 -0500 Received: from eu1sys200aog120.obsmtp.com ([207.126.144.149]:59985) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PiqbS-0000zy-BH for qemu-devel@nongnu.org; Fri, 28 Jan 2011 10:51:14 -0500 Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 15E9822A for ; Fri, 28 Jan 2011 15:51:13 +0000 (GMT) Received: from Webmail-eu.st.com (safex1hubcas5.st.com [10.75.90.71]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D6A642B0F for ; Fri, 28 Jan 2011 15:51:12 +0000 (GMT) From: Date: Fri, 28 Jan 2011 16:51:05 +0100 Message-ID: <1296229866-32011-8-git-send-email-christophe.lyon@st.com> In-Reply-To: <1296229866-32011-1-git-send-email-christophe.lyon@st.com> References: <1296229866-32011-1-git-send-email-christophe.lyon@st.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 7/8] implement vsli.64, vsri.64 List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Christophe Lyon Signed-off-by: Peter Maydell Signed-off-by: Christophe Lyon --- target-arm/translate.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 3b14b8f..984df08 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4711,7 +4711,16 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1); } else if (op == 4 || (op == 5 && u)) { /* Insert */ - cpu_abort(env, "VS[LR]I.64 not implemented"); + neon_load_reg64(cpu_V1, rd + pass); + uint64_t mask; + if (op == 4) { + mask = 0xffffffffffffffffull >> -shift; + } else { + mask = 0xffffffffffffffffull << shift; + } + tcg_gen_andi_i64(cpu_V0, cpu_V0, mask); + tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask); + tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); } neon_store_reg64(cpu_V0, rd + pass); } else { /* size < 3 */ -- 1.7.2.3