* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
@ 2011-01-31 18:41 Haiying.Wang at freescale.com
2011-01-31 18:41 ` [U-Boot] [PATCH 1/6] Introduce the Tertiary Program loader Haiying.Wang at freescale.com
` (7 more replies)
0 siblings, 8 replies; 46+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-31 18:41 UTC (permalink / raw)
To: u-boot
This patchset adds support for TPL(Tertiary Program Loader) and P1021MDS board.
It is a rework of patchset at
http://lists.denx.de/pipermail/u-boot/2010-December/082881.html,
addresses the comments from the list and is based on the top of the tree.
It needs to be applied after patch
http://lists.denx.de/pipermail/u-boot/2011-January/086346.html and patch
http://lists.denx.de/pipermail/u-boot/2011-January/086524.html
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 1/6] Introduce the Tertiary Program loader
2011-01-31 18:41 [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Haiying.Wang at freescale.com
@ 2011-01-31 18:41 ` Haiying.Wang at freescale.com
2011-01-31 18:41 ` [U-Boot] [PATCH 2/6] powerpc/85xx: add TPL support Haiying.Wang at freescale.com
` (6 subsequent siblings)
7 siblings, 0 replies; 46+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-31 18:41 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold the final uboot image and
the nand spl code needs to be limitated to 4K byte, then tpl code will load the
final uboot image after ddr is initialized.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
Makefile | 15 ++++++++++++++-
README | 27 +++++++++++++++++++++++++++
2 files changed, 41 insertions(+), 1 deletions(-)
diff --git a/Makefile b/Makefile
index 0d1ea5d..ae5db69 100644
--- a/Makefile
+++ b/Makefile
@@ -402,8 +402,19 @@ $(obj)u-boot.lds: $(LDSCRIPT)
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
+tpl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
+ $(MAKE) -C tpl/board/$(BOARDDIR) all
+
+NAND_SPL_OBJS-y += $(obj)nand_spl/u-boot-spl-16k.bin
+NAND_SPL_OBJS-$(CONFIG_HAS_TPL) += $(obj)tpl/u-boot-tpl.bin
+NAND_SPL_OBJS-y += $(obj)u-boot.bin
+
+ifeq ($(CONFIG_HAS_TPL),y)
+$(obj)u-boot-nand.bin: nand_spl tpl $(obj)u-boot.bin
+else
$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
- cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+endif
+ cat $(NAND_SPL_OBJS-y) > $(obj)u-boot-nand.bin
onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
@@ -1221,6 +1232,7 @@ clean:
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
+ @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -1245,6 +1257,7 @@ clobber: clean
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
+ @[ ! -d $(obj)tpl ] || find $(obj)tpl -name "*" -type l -print | xargs rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
diff --git a/README b/README
index 755d17c..447fff0 100644
--- a/README
+++ b/README
@@ -2124,6 +2124,33 @@ FIT uImage format:
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
+- NAND Boot Support
+ CONFIG_NAND_U_BOOT
+
+ Builds a U-Boot image that boots from NAND, prefixed by a small
+ loader stub (secondary program loader -- SPL) that loads the
+ rest of U-Boot into RAM. This symbol will be set in all build
+ phases.
+
+ CONFIG_NAND_SPL
+
+ This is set by the build system when compiling code to go into
+ the SPL. It is not set when building the code that the SPL
+ loads.
+
+- TPL Boot Support
+ CONFIG_HAS_TPL
+
+ Builds a U-Boot image that contains a loader stub (tertiary
+ program loader -- TPL) that boots out of some type of RAM,
+ after being loaded by an SPL or similar platform-specific
+ mechanism. This symbol will be set in all build phases.
+
+ CONFIG_IN_TPL
+
+ This is set by the build system when compiling code to go into
+ the TPL. It is not set when building the code that the TPL
+ loads, or when building the SPL.
Modem Support:
--------------
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 2/6] powerpc/85xx: add TPL support
2011-01-31 18:41 [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Haiying.Wang at freescale.com
2011-01-31 18:41 ` [U-Boot] [PATCH 1/6] Introduce the Tertiary Program loader Haiying.Wang at freescale.com
@ 2011-01-31 18:41 ` Haiying.Wang at freescale.com
2011-01-31 18:41 ` [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support Haiying.Wang at freescale.com
` (5 subsequent siblings)
7 siblings, 0 replies; 46+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-31 18:41 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu.c | 7 ++
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 22 ++++++-
arch/powerpc/cpu/mpc85xx/start.S | 12 ++--
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds | 99 ++++++++++++++++++++++++++++++
4 files changed, 132 insertions(+), 8 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1aad2ba..e923547 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -296,6 +296,12 @@ void mpc85xx_reginfo(void)
#ifndef CONFIG_FSL_CORENET
phys_size_t initdram(int board_type)
{
+#if defined(CONFIG_HAS_TPL) && !defined(CONFIG_IN_TPL)
+ /* ddr has been initialized in tpl boot stage thus we only need
+ * to get the ddr dram size for the final uboot.
+ */
+ return fsl_ddr_sdram_size();
+#else
phys_size_t dram_size = 0;
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
@@ -342,6 +348,7 @@ phys_size_t initdram(int board_type)
puts("DDR: ");
return dram_size;
+#endif /* CONFIG_HAS_TPL */
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 8fb27ab..65c32d9 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009 - 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,6 +23,8 @@
#include <common.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void cpu_init_f(void)
{
fsl_lbc_t *lbc = LBC_BASE_ADDR;
@@ -40,7 +42,8 @@ void cpu_init_f(void)
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) \
+ && !defined(CONFIG_IN_TPL)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
char *l2srbar;
int i;
@@ -60,4 +63,19 @@ void cpu_init_f(void)
for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
l2srbar[i] = 0;
#endif
+#ifdef CONFIG_IN_TPL
+ init_used_tlb_cams();
+#endif
+}
+
+#ifdef CONFIG_IN_TPL
+/*
+ * Because the primary cpu's info is enough for the 2nd stage, we define the
+ * cpu number to 1 so as to keep code size for 2nd stage binary as small as
+ * possible.
+ */
+int cpu_numcores()
+{
+ return 1;
}
+#endif /* CONFIG_IN_TPL */
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index fa98af6..5496fc4 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -58,12 +58,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_IN_TPL)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
-#endif
+#endif /* !CONFIG_NAND_SPL && !CONFIG_IN_TPL*/
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@@ -435,7 +435,7 @@ _start_cont:
/* NOTREACHED - board_init_f() does not return */
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_IN_TPL)
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
@@ -877,7 +877,7 @@ in32:
in32r:
lwbrx r3,r0,r3
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !CONFIG_NAND_SPL && !CONFIG_IN_TPL */
/*------------------------------------------------------------------------------*/
@@ -1067,7 +1067,7 @@ clear_bss:
mr r4,r10 /* Destination Address */
bl board_init_r
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_IN_TPL)
/*
* Copy exception vector code to low memory
*
@@ -1207,4 +1207,4 @@ setup_ivors:
#include "fixed_ivor.S"
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !CONFIG_NAND_SPL && !CONFIG_IN_TPL */
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
new file mode 100644
index 0000000..d8ff62b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .text :
+ {
+ *(.text*)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } :text
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ KEEP(*(.got))
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ start.o KEEP(*(.bootpg))
+ } :text = 0xffff
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 18:41 [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Haiying.Wang at freescale.com
2011-01-31 18:41 ` [U-Boot] [PATCH 1/6] Introduce the Tertiary Program loader Haiying.Wang at freescale.com
2011-01-31 18:41 ` [U-Boot] [PATCH 2/6] powerpc/85xx: add TPL support Haiying.Wang at freescale.com
@ 2011-01-31 18:41 ` Haiying.Wang at freescale.com
2011-01-31 20:03 ` Wolfgang Denk
2011-01-31 18:41 ` [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines Haiying.Wang at freescale.com
` (4 subsequent siblings)
7 siblings, 1 reply; 46+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-31 18:41 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
Support P1021MDS board to boot from NAND flash (No NOR flash on this
board). And because P1021 only has 256K L2 SRAM, which can not used for final
uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can
be initialized in L2 SRAM through SPD code. So there are three stage uboot
images:
* nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND.
* tpl_boot, 112KB size. The env variables are copied to offset 128KB
in L2 SRAM, so that ddr spd code can get the interleaving mode setting in env.
It loads final uboot image from offset 128KB in NAND.
* final uboot image, size is variable depends on the functions enabled.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Mohit Kumar <Mohit.Kumar@freescale.com>
Signed-off-by: Yu Liu <Yu.Liu@freescale.com>
Signed-off-by: Kai Jiang <Kai.Jiang@freescale.com>
---
MAINTAINERS | 4 +
board/freescale/p1021mds/Makefile | 52 +++
board/freescale/p1021mds/config.mk | 31 ++
board/freescale/p1021mds/ddr.c | 107 +++++
board/freescale/p1021mds/law.c | 34 ++
board/freescale/p1021mds/p1021mds.c | 133 ++++++
board/freescale/p1021mds/tlb.c | 102 +++++
boards.cfg | 1 +
include/configs/P1021MDS.h | 535 +++++++++++++++++++++++++
nand_spl/board/freescale/p1021mds/Makefile | 134 ++++++
nand_spl/board/freescale/p1021mds/nand_boot.c | 69 ++++
nand_spl/nand_boot_fsl_elbc.c | 6 +-
tpl/board/freescale/p1021mds/Makefile | 257 ++++++++++++
tpl/board/freescale/p1021mds/tpl_boot.c | 79 ++++
14 files changed, 1543 insertions(+), 1 deletions(-)
create mode 100644 board/freescale/p1021mds/Makefile
create mode 100644 board/freescale/p1021mds/config.mk
create mode 100644 board/freescale/p1021mds/ddr.c
create mode 100644 board/freescale/p1021mds/law.c
create mode 100644 board/freescale/p1021mds/p1021mds.c
create mode 100644 board/freescale/p1021mds/tlb.c
create mode 100644 include/configs/P1021MDS.h
create mode 100644 nand_spl/board/freescale/p1021mds/Makefile
create mode 100644 nand_spl/board/freescale/p1021mds/nand_boot.c
create mode 100644 tpl/board/freescale/p1021mds/Makefile
create mode 100644 tpl/board/freescale/p1021mds/tpl_boot.c
diff --git a/MAINTAINERS b/MAINTAINERS
index edd1c5c..da1b2a3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17,6 +17,10 @@
# Board CPU #
#########################################################################
+Haiying Wang <Haiying.Wang@freescale.com>
+
+ P1021MDS P1021
+
Poonam Aggrwal <poonam.aggrwal@freescale.com>
P2020RDB P2020
diff --git a/board/freescale/p1021mds/Makefile b/board/freescale/p1021mds/Makefile
new file mode 100644
index 0000000..50d4743
--- /dev/null
+++ b/board/freescale/p1021mds/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += law.o
+COBJS-y += tlb.o
+COBJS-y += ddr.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk
new file mode 100644
index 0000000..3888f61
--- /dev/null
+++ b/board/freescale/p1021mds/config.mk
@@ -0,0 +1,31 @@
+#
+# Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# p1021mds board
+#
+
+ifndef NAND_SPL
+ifndef IN_TPL
+ifeq ($(CONFIG_NAND), y)
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+endif
+endif
+endif
diff --git a/board/freescale/p1021mds/ddr.c b/board/freescale/p1021mds/ddr.c
new file mode 100644
index 0000000..594a4a8
--- /dev/null
+++ b/board/freescale/p1021mds/ddr.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
+{
+ int ret;
+
+ /*
+ * The P1021 only has one DDR controller, and the P1021MDS board has
+ * only one DIMM slot.
+ */
+
+ ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd,
+ sizeof(ddr3_spd_eeprom_t));
+
+ if (ret) {
+ debug("DDR: failed to read SPD from address %u\n",
+ SPD_EEPROM_ADDRESS1);
+ memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t));
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ */
+ popts->clk_adjust = 6;
+
+ /*
+ * Factors to consider for CPO:
+ */
+ popts->cpo_override = 0x1f;
+
+ /*
+ * Factors to consider for write data delay:
+ */
+ popts->write_data_delay = 2;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ */
+ popts->half_strength_driver_enable = 1;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = DDR3_RTT_40_OHM; /* 40 Ohm rtt */
+ popts->rtt_wr_override_value = 2; /* Rtt_WR */
+
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xa;
+ popts->wrlvl_start = 0x8;
+ /*
+ * P1021 supports max 32-bit DDR width
+ */
+ popts->data_bus_width = 1;
+
+ /*
+ * disable on-the-fly burst chop mode for 32 bit data bus
+ */
+ popts->OTF_burst_chop_en = 0;
+
+ /*
+ * Set fixed 8 beat burst for 32 bit data bus
+ */
+ popts->burst_length = DDR_BL8;
+}
diff --git a/board/freescale/p1021mds/law.c b/board/freescale/p1021mds/law.c
new file mode 100644
index 0000000..cdbdcb2
--- /dev/null
+++ b/board/freescale/p1021mds/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_IN_TPL
+ SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256K, LAW_TRGT_IF_LBC),
+#endif /* !CONFIG_IN_TPL */
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c
new file mode 100644
index 0000000..c7a7e57
--- /dev/null
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/mp.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <tsec.h>
+#include <netdev.h>
+
+int board_early_init_f(void)
+{
+
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+#ifdef CONFIG_MMC
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+#endif
+
+ /* Set ABSWP to implement conversion of addresses in the LBC */
+ setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: P1021 MDS\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct tsec_info_struct tsec_info[3];
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII3_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, base, size);
+
+ FT_FSL_PCI_SETUP;
+
+}
+#endif
+;
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/freescale/p1021mds/tlb.c b/board/freescale/p1021mds/tlb.c
new file mode 100644
index 0000000..30af6dd
--- /dev/null
+++ b/board/freescale/p1021mds/tlb.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_IN_TPL
+ /* *I*G* - PCIE */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE2_MEM_VIRT + 0x10000000),
+ (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
+ (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIE I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /*
+ * *I*G BCSR/PMC0/PMC1
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+#endif /* !CONFIG_IN_TPL */
+
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_NAND_SPL) || defined(CONFIG_IN_TPL)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256K, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index eceacf6..0787a9a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -483,6 +483,7 @@ P1020RDB powerpc mpc85xx p1_p2_rdb freesca
P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND
P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD
P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020,SPIFLASH
+P1021MDS_NAND powerpc mpc85xx p1021mds freescale - P1021MDS:NAND
P1022DS powerpc mpc85xx p1022ds freescale
P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010
P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,NAND
diff --git a/include/configs/P1021MDS.h b/include/configs/P1021MDS.h
new file mode 100644
index 0000000..c860a24
--- /dev/null
+++ b/include/configs/P1021MDS.h
@@ -0,0 +1,535 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * p1021mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_HAS_TPL
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_U_BOOT
+#define CONFIG_RAMBOOT_NAND
+#endif
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#ifdef CONFIG_HAS_TPL
+#define CONFIG_SYS_TEXT_BASE_TPL 0xf8f81000
+#endif
+#define CONFIG_SYS_TEXT_BASE 0x01001000
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#elif CONFIG_IN_TPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_TPL /* start of monitor */
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE /* BOOKE */
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/68/P1021 */
+#define CONFIG_P1021 /* P1021 silicon support */
+#define CONFIG_P1021MDS /* P1021MDS board specific */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_FSL_ELBC /* Has Enhance localbus controller */
+
+/* Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_HWCONFIG
+
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x1fffffff
+
+#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
+ addresses in the LBC */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
+ /* physical addr of CCSRBAR */
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#endif
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+ /* PQII uses CONFIG_SYS_IMMR */
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_TLB_START 11
+
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+ /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff DDR3 512MB cacheable
+ * 0xa000_0000 0xbfff_ffff PCIE2 Mem 512MB non-cacheable
+ * 0xc000_0000 0xdfff_ffff PCIE1 Mem 512MB non-cacheable
+ * 0xffc1_0000 0xffc1_ffff PCIE2 IO range 64K non-cacheable
+ * 0xffc2_0000 0xffc2_ffff PCIE1 IO range 64K non-cacheable
+ * 0xf800_0000 0xf800_7fff BCSR on CS1 32KB non-cacheable
+ * 0xf801_0000 0xf801_ffff PMC1 on CS2 64KB non-cacheable
+ * 0xf802_0000 0xf802_ffff PMC0 on CS3 64KB non-cacheable
+ * 0xfc00_0000 0xfdff_ffff NAND on CS0 32MB non-cacheable
+ * 0xffe0_0000 0xffef_ffff CCSRBAR 1M
+ */
+
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_BCSR_BASE 0xf8000000
+#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
+
+#define CONFIG_SYS_PIB_PMC1_BASE 0xf8010000
+ /* start of PIB-QOC3(PMC1) 64K */
+#define CONFIG_SYS_PIB_PMC1_BASE_PHYS CONFIG_SYS_PIB_PMC1_BASE
+
+#define CONFIG_SYS_PIB_PMC0_BASE 0xf8020000
+ /* start of PIB-T1/E1(PMC0) 64K */
+#define CONFIG_SYS_PIB_PMC0_BASE_PHYS CONFIG_SYS_PIB_PMC0_BASE
+
+/* chip select 1 - BCSR*/
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
+ | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+ | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+
+/* chip select 2 - PIB(QOC3-PMC1)*/
+#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PIB_PMC1_BASE_PHYS) \
+ | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+ | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+
+/* chip select 3 - PIB(T1/E1-PMC0)*/
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PIB_PMC0_BASE_PHYS) \
+ | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+ | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+
+#define CONFIG_SYS_NO_FLASH
+
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) \
+ || defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE 0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE 0xFC000000
+#endif
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
+
+/* NAND boot: 4K NAND loader config */
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (112 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#ifdef CONFIG_IN_TPL
+/* tpl boot: 112K tpl uboot config*/
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x01000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x01000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+
+/* NAND FLASH CONFIG */
+#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+/* chip select 0 - NAND */
+#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SERIAL_MULTI
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+/* Use the HUSH parser*/
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (576 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (128 << 10))
+
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot Argument Buffer Size */
+
+/*********************************/
+#ifndef CONFIG_IN_TPL
+
+#define CONFIG_MP /* Multiprocessor support */
+
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controller */
+#define CONFIG_PCIE2 /* PCIE controller */
+#define CONFIG_FSL_PCI_INIT /* use common fsl pci init code */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* TSEC support */
+#if defined(CONFIG_TSEC_ENET)
+
+/* TSECV2 */
+#define CONFIG_TSECV2
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME "eTSEC3"
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHYIDX 0
+
+#define TSEC2_PHY_ADDR 4
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_SGMII)
+#define TSEC2_PHYIDX 0
+
+#ifdef CONFIG_TSEC3_IN_SGMII /* Need to set SW8.6 to 0 */
+#define TSEC3_PHY_ADDR 6
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_SGMII)
+#else
+#define TSEC3_PHY_ADDR 1
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#endif
+#define TSEC3_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM 1
+
+#define PLPPAR1_I2C_BIT_MASK 0x0000000F
+#define PLPPAR1_I2C2_VAL 0x00000000
+#define PLPPAR1_ESDHC_VAL 0x0000000A
+#define PLPDIR1_I2C_BIT_MASK 0x0000000F
+#define PLPDIR1_I2C2_VAL 0x0000000F
+#define PLPDIR1_ESDHC_VAL 0x00000006
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64K */
+
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
+ /* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME p1021mds
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE your.uImage
+
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=your.fdt.dtb\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs\0" \
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "run nfsargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "run ramargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* !CONFIG_IN_TPL */
+#endif /* __CONFIG_H */
diff --git a/nand_spl/board/freescale/p1021mds/Makefile b/nand_spl/board/freescale/p1021mds/Makefile
new file mode 100644
index 0000000..d2ebb70
--- /dev/null
+++ b/nand_spl/board/freescale/p1021mds/Makefile
@@ -0,0 +1,134 @@
+#
+# Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+PAD_TO := 0xfff04000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDFLAGS_spl := -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
+ $(LDFLAGS_FINAL)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS = start.o resetvec.o
+COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS_spl) $(__OBJS) $(PLATFORM_LIBS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+ @rm -f $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+ @rm -f $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c \
+ $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+ @rm -f $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c \
+ $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+ @rm -f $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+ @rm -f $(obj)law.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+ @rm -f $(obj)nand_boot_fsl_elbc.c
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+ $(obj)nand_boot_fsl_elbc.c
+
+$(obj)ns16550.c:
+ @rm -f $(obj)ns16550.c
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)resetvec.S:
+ @rm -f $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+
+$(obj)fixed_ivor.S:
+ @rm -f $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S \
+ $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+ @rm -f $(obj)start.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+
+$(obj)tlb.c:
+ @rm -f $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+ @rm -f $(obj)tlb_table.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_boot.c:
+ @rm -f $(obj)nand_boot.c
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c \
+ $(obj)nand_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/p1021mds/nand_boot.c b/nand_spl/board/freescale/p1021mds/nand_boot.c
new file mode 100644
index 0000000..73a66fa
--- /dev/null
+++ b/nand_spl/board/freescale/p1021mds/nand_boot.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ uint plat_ratio, bus_clk, sys_clk = 0;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ sys_clk = CONFIG_SYS_CLK_FREQ;
+
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = plat_ratio * sys_clk;
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+ /* copy code to DDR and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 9547d44..8b135bc 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -4,7 +4,7 @@
* (C) Copyright 2006-2008
* Stefan Roese, DENX Software Engineering, sr at denx.de.
*
- * Copyright (c) 2008 Freescale Semiconductor, Inc.
+ * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* Author: Scott Wood <scottwood@freescale.com>
*
* This program is free software; you can redistribute it and/or
@@ -47,7 +47,11 @@ static void nand_wait(void)
}
}
+#ifdef CONFIG_IN_TPL
+void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#else
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#endif
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
diff --git a/tpl/board/freescale/p1021mds/Makefile b/tpl/board/freescale/p1021mds/Makefile
new file mode 100644
index 0000000..e312e79
--- /dev/null
+++ b/tpl/board/freescale/p1021mds/Makefile
@@ -0,0 +1,257 @@
+#
+# Copyright (C) 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+IN_TPL := y
+PAD_TO := 0xf8f9c000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-tpl.lds
+LDFLAGS_tpl := -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_TPL) \
+ $(LDFLAGS_FINAL)
+AFLAGS += -DCONFIG_IN_TPL
+CFLAGS += -DCONFIG_IN_TPL
+
+SOBJS = start.o ticks.o ppcstring.o
+COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o speed.o \
+ tpl_boot.o tlb.o tlb_table.o ddr-gen3.o time.o ddr.o cpu.o fsl_lbc.o \
+ string.o hwconfig.o time_lib.o ddr_spd.o ctype.o div64.o crc32.o\
+ console.o cmd_nvedit.o env_common.o env_nand.o vsprintf.o \
+ display_options.o hashtable.o dlmalloc.o stdio.o ns16550.o serial.o \
+ errno.o command.o serial_driver.o qsort.o
+
+ifdef CONFIG_RAMBOOT_NAND
+COBJS += nand_boot_fsl_elbc.o
+endif
+
+LIBS = $(OBJTREE)/arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+LIBS += $(OBJTREE)/drivers/i2c/libi2c.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+__LIBS := $(addprefix $(obj), $(LIBS))
+LNDIR := $(OBJTREE)/tpl/board/$(BOARDDIR)
+
+tplobj := $(OBJTREE)/tpl/
+
+ALL = $(tplobj)u-boot-tpl $(tplobj)u-boot-tpl.bin
+
+all: $(obj).depend $(ALL)
+
+$(tplobj)u-boot-tpl.bin: $(tplobj)u-boot-tpl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(tplobj)u-boot-tpl: $(OBJS) $(LIBS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS_tpl) $(__OBJS) $(__LIBS) \
+ $(PLATFORM_LIBS) \
+ -Map $(tplobj)u-boot-tpl.map \
+ -o $(tplobj)u-boot-tpl
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+ @rm -f $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+ @rm -f $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
+
+$(obj)fsl_lbc.c:
+ @rm -f $(obj)fsl_lbc.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c $(obj)fsl_lbc.c
+
+$(obj)cpu.c:
+ @rm -f $(obj)cpu.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu.c $(obj)cpu.c
+
+$(obj)cpu_init_nand.c:
+ @rm -f $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+ @rm -f $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+ @rm -f $(obj)law.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+ @rm -f $(obj)nand_boot_fsl_elbc.c
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+ $(obj)nand_boot_fsl_elbc.c
+
+$(obj)fixed_ivor.S:
+ @rm -f $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+ @rm -f $(obj)start.S
+ ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
+
+$(obj)speed.c:
+ @rm -f $(obj)speed.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/speed.c $(obj)speed.c
+
+$(obj)interrupts.c:
+ @rm -f $(obj)interrupts.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/interrupts.c $(obj)interrupts.c
+
+$(obj)ticks.S:
+ @rm -f $(obj)ticks.S
+ ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
+
+$(obj)bootm.c:
+ @rm -f $(obj)bootm.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/bootm.c $(obj)bootm.c
+
+$(obj)tlb.c:
+ @rm -f $(obj)tlb.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+ @rm -f $(obj)tlb_table.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+$(obj)ddr.c:
+ @rm -f $(obj)ddr.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/ddr.c $(obj)ddr.c
+
+$(obj)time.c:
+ @rm -f $(obj)time.o
+ ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c
+
+$(obj)ddr-gen3.c:
+ @rm -f $(obj)ddr-gen3.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/ddr-gen3.c $(obj)ddr-gen3.c
+
+$(obj)ppcstring.S:
+ @rm -f $(obj)ppcstring.S
+ ln -sf $(SRCTREE)/arch/powerpc/lib/ppcstring.S $(obj)ppcstring.S
+
+$(obj)ns16550.c:
+ @rm -f $(obj)ns16550.c
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)serial_driver.c:
+ @rm -f $(obj)serial_driver.c
+ ln -sf $(SRCTREE)/drivers/serial/serial.c $(obj)serial_driver.c
+
+$(obj)time_lib.c:
+ @rm -f $(obj)time_lib.o
+ ln -sf $(SRCTREE)/lib/time.c $(obj)time_lib.c
+
+$(obj)ddr_spd.c:
+ @rm -f $(obj)ddr_spd.c
+ ln -sf $(SRCTREE)/common/ddr_spd.c $(obj)ddr_spd.c
+
+$(obj)ctype.c:
+ @rm -f $(obj)ctype.c
+ ln -sf $(SRCTREE)/lib/ctype.c $(obj)ctype.c
+
+$(obj)div64.c:
+ @rm -f $(obj)div64.c
+ ln -sf $(SRCTREE)/lib/div64.c $(obj)div64.c
+
+$(obj)crc32.c:
+ @rm -f $(obj)crc32.c
+ ln -sf $(SRCTREE)/lib/crc32.c $(obj)crc32.c
+
+$(obj)env_common.c:
+ @rm -f $(obj)env_common.c
+ ln -sf $(SRCTREE)/common/env_common.c $(obj)env_common.c
+
+$(obj)env_nand.c:
+ @rm -f $(obj)env_nand.c
+ ln -sf $(SRCTREE)/common/env_nand.c $(obj)env_nand.c
+
+$(obj)cmd_nvedit.c:
+ @rm -f $(obj)cmd_nvedit.c
+ ln -sf $(SRCTREE)/common/cmd_nvedit.c $(obj)cmd_nvedit.c
+
+$(obj)console.c:
+ @rm -f $(obj)console.c
+ ln -sf $(SRCTREE)/common/console.c $(obj)console.c
+
+$(obj)dlmalloc.c:
+ @rm -f $(obj)dlmalloc.c
+ ln -sf $(SRCTREE)/common/dlmalloc.c $(obj)dlmalloc.c
+
+$(obj)hwconfig.c:
+ @rm -f $(obj)hwconfig.c
+ ln -sf $(SRCTREE)/common/hwconfig.c $(obj)hwconfig.c
+
+$(obj)stdio.c:
+ @rm -f $(obj)stdio.c
+ ln -sf $(SRCTREE)/common/stdio.c $(obj)stdio.c
+
+$(obj)string.c:
+ @rm -f $(obj)string.c
+ ln -sf $(SRCTREE)/lib/string.c $(obj)string.c
+
+$(obj)vsprintf.c:
+ @rm -f $(obj)vsprintf.c
+ ln -sf $(SRCTREE)/lib/vsprintf.c $(obj)vsprintf.c
+
+$(obj)display_options.c:
+ @rm -f $(obj)display_options.c
+ ln -sf $(SRCTREE)/lib/display_options.c $(obj)display_options.c
+
+$(obj)hashtable.c:
+ @rm -f $(obj)hashtable.c
+ ln -sf $(SRCTREE)/lib/hashtable.c $(obj)hashtable.c
+
+$(obj)serial.c:
+ @rm -f $(obj)serial.c
+ ln -sf $(SRCTREE)/common/serial.c $(obj)serial.c
+
+$(obj)command.c:
+ @rm -f $(obj)command.c
+ ln -sf $(SRCTREE)/common/command.c $(obj)command.c
+
+$(obj)errno.c:
+ @rm -f $(obj)errno.c
+ ln -sf $(SRCTREE)/lib/errno.c $(obj)errno.c
+
+$(obj)qsort.c:
+ @rm -f $(obj)qsort.c
+ ln -sf $(SRCTREE)/lib/qsort.c $(obj)qsort.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)tpl_boot.c:
+ @rm -f $(obj)tpl_boot.c
+ ln -s $(SRCTREE)/tpl/freescale/tpl_boot.c $(obj)tpl_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/tpl/board/freescale/p1021mds/tpl_boot.c b/tpl/board/freescale/p1021mds/tpl_boot.c
new file mode 100644
index 0000000..386d76c
--- /dev/null
+++ b/tpl/board/freescale/p1021mds/tpl_boot.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void nand_load(unsigned int offs, int uboot_size, uchar *dst);
+extern phys_size_t init_ddr_dram(void);
+
+void board_init_f(ulong bootflag)
+{
+ uint plat_ratio, bus_clk, sys_clk = 0;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ sys_clk = CONFIG_SYS_CLK_FREQ;
+
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = plat_ratio * sys_clk;
+ get_clocks();
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* load environment */
+#ifdef CONFIG_NAND_U_BOOT
+ nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ /* board specific DDR initialization */
+ gd->ram_size = initdram(0);
+ puts("DRAM:");
+ print_size(gd->ram_size, "");
+
+ puts("\nThird program loader running in sram... ");
+
+ /*
+ * Load final image to DDR and let it run from there.
+ */
+#ifdef CONFIG_NAND_U_BOOT
+ nand_boot();
+#endif
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+}
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines.
2011-01-31 18:41 [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Haiying.Wang at freescale.com
` (2 preceding siblings ...)
2011-01-31 18:41 ` [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support Haiying.Wang at freescale.com
@ 2011-01-31 18:41 ` Haiying.Wang at freescale.com
2011-01-31 20:07 ` Wolfgang Denk
2011-01-31 21:08 ` Kumar Gala
2011-01-31 18:41 ` [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash Haiying.Wang at freescale.com
` (3 subsequent siblings)
7 siblings, 2 replies; 46+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-31 18:41 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/include/asm/immap_85xx.h | 6 ++++++
arch/powerpc/include/asm/immap_qe.h | 9 +++++++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 6bd83ba..77e3629 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1948,6 +1948,12 @@ typedef struct ccsr_gur {
u8 res10b[76];
par_io_t qe_par_io[7];
u8 res10c[1600];
+#elif defined(CONFIG_P1021)
+ u8 res10b1[12];
+ u32 iovselsr;
+ u8 res10b2[60];
+ par_io_t qe_par_io[3];
+ u8 res10c[1496];
#else
u8 res10b[1868];
#endif
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 531cfc8..0fffba2 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -3,7 +3,7 @@
* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
*
- * Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
* Author: Shlomi Gridih <gridish@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
@@ -588,6 +588,9 @@ typedef struct qe_immap {
#elif defined(CONFIG_MPC8569)
u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */
u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */
+#elif defined(CONFIG_P1021)
+ u8 muram[0x06000]; /* 0x1_0000 - 0x1_6000 Multi-user RAM */
+ u8 res17[0x1a000]; /* 0x1_6000 - 0x3_0000 */
#else
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
@@ -601,13 +604,15 @@ extern qe_map_t *qe_immr;
#define QE_MURAM_SIZE 0x10000UL
#elif defined(CONFIG_MPC8569)
#define QE_MURAM_SIZE 0x20000UL
+#elif defined(CONFIG_P1021)
+#define QE_MURAM_SIZE 0x6000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832x)
#define QE_MURAM_SIZE 0x4000UL
#endif
-#if defined(CONFIG_MPC8323)
+#if defined(CONFIG_MPC8323) || defined(CONFIG_P1021)
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC8569)
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
2011-01-31 18:41 [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Haiying.Wang at freescale.com
` (3 preceding siblings ...)
2011-01-31 18:41 ` [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines Haiying.Wang at freescale.com
@ 2011-01-31 18:41 ` Haiying.Wang at freescale.com
2011-01-31 20:08 ` Wolfgang Denk
2011-01-31 18:41 ` [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support Haiying.Wang at freescale.com
` (2 subsequent siblings)
7 siblings, 1 reply; 46+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-31 18:41 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
For some board which doesn't have NOR flash and the QE's firmware(ucode) is
saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will
call it later after nand is initialized.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 8ece970..fcf9e7b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -384,7 +384,7 @@ int cpu_init_r(void)
enable_cpc();
-#ifdef CONFIG_QE
+#if defined(CONFIG_QE) && !defined(CONFIG_SYS_QE_FW_IN_NAND)
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
qe_init(qe_base);
qe_reset();
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-01-31 18:41 [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Haiying.Wang at freescale.com
` (4 preceding siblings ...)
2011-01-31 18:41 ` [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash Haiying.Wang at freescale.com
@ 2011-01-31 18:41 ` Haiying.Wang at freescale.com
2011-01-31 20:11 ` Wolfgang Denk
2011-01-31 19:39 ` [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Wolfgang Denk
2011-02-01 5:26 ` Kumar Gala
7 siblings, 1 reply; 46+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-31 18:41 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines
misc_init_r() for loading ucode and initializing qe.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/cpu/mpc85xx/speed.c | 4 ++
arch/powerpc/include/asm/immap_85xx.h | 13 +++++
board/freescale/p1021mds/p1021mds.c | 83 +++++++++++++++++++++++++++++++++
drivers/qe/uec.c | 40 +++++++++++++++-
include/configs/P1021MDS.h | 47 ++++++++++++++++++
5 files changed, 186 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..ae94ee8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo->freqQE = sysInfo->freqSystemBus;
+#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 77e3629..9b7de6b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1909,6 +1909,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x80000000
#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
+#define MPC85xx_PMUXCR_QE0 0x00008000
+#define MPC85xx_PMUXCR_QE1 0x00004000
+#define MPC85xx_PMUXCR_QE2 0x00002000
+#define MPC85xx_PMUXCR_QE3 0x00001000
+#define MPC85xx_PMUXCR_QE4 0x00000800
+#define MPC85xx_PMUXCR_QE5 0x00000400
+#define MPC85xx_PMUXCR_QE6 0x00000200
+#define MPC85xx_PMUXCR_QE7 0x00000100
+#define MPC85xx_PMUXCR_QE8 0x00000080
+#define MPC85xx_PMUXCR_QE9 0x00000040
+#define MPC85xx_PMUXCR_QE10 0x00000020
+#define MPC85xx_PMUXCR_QE11 0x00000010
+#define MPC85xx_PMUXCR_QE12 0x00000008
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr; /* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c
index c7a7e57..e1ee1cf 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,54 @@
#include <tsec.h>
#include <netdev.h>
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include <nand.h>
+#include <asm/errno.h>
+#endif
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+#endif
+
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
+ {0, 17, 2, 0, 2}, /* ENET1_CRS */
+ {0, 16, 2, 0, 2}, /* ENET1_COL */
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -100,6 +148,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
+
+ uec_standard_init(bis);
+#endif
+
return pci_eth_init(bis);
}
#endif
@@ -120,6 +176,10 @@ void ft_board_setup(void *blob, bd_t *bd)
FT_FSL_PCI_SETUP;
+#ifdef CONFIG_QE
+ do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
+ sizeof("okay"), 0);
+#endif
}
#endif
;
@@ -131,3 +191,26 @@ void board_lmb_reserve(struct lmb *lmb)
cpu_mp_lmb_reserve(lmb);
}
#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r()
+{
+#if defined(CONFIG_QE) && defined(CONFIG_SYS_QE_FW_LENGTH)
+ int ret;
+ size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+
+ /* load QE firmware from NAND flash to DDR first */
+ ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+ &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+
+ if (ret && ret == -EUCLEAN) {
+ printf ("NAND read for QE firmware at offset %x failed %d\n",
+ CONFIG_SYS_QE_FW_IN_NAND, ret);
+ }
+
+ qe_init(CONFIG_SYS_IMMR + 0x00080000);
+ qe_reset();
+#endif
+ return 0;
+}
+#endif
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 282ab23..04d7987 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@@ -30,6 +30,9 @@
#include "uec.h"
#include "uec_phy.h"
#include "miiphy.h"
+#ifdef CONFIG_P1021
+#define BCSR11_ENET_MICRST 0x20
+#endif
/* Default UTBIPAR SMI address */
#ifndef CONFIG_UTBIPAR_INIT_TBIPA
@@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
+#ifdef CONFIG_P1021
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* QE9 and QE12 need to be set for enabling QE MII managment signals */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
+#ifdef CONFIG_P1021
+ /*
+ * QE12 is muxed with LBCTL, it needs to be released for enabling
+ * LBCTL signal for LBC usage.
+ */
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
/* Adjust the interface according to speed */
adjust_link(dev);
}
@@ -1198,10 +1217,24 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
+#ifdef CONFIG_P1021
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for each UEC */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+ udelay(200);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+
+ /* QE9 and QE12 need to be set for enabling QE MII managment signals */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
err = init_phy(dev);
if (err) {
printf("%s: Cannot initialize PHY, aborting.\n",
@@ -1228,6 +1261,11 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
udelay(100000);
} while (1);
+#ifdef CONFIG_P1021
+ /* QE12 needs to be released for enabling LBCTL signal*/
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
if (err || i <= 0)
printf("warning: %s: timeout on PHY link\n", dev->name);
diff --git a/include/configs/P1021MDS.h b/include/configs/P1021MDS.h
index c860a24..a946d3c 100644
--- a/include/configs/P1021MDS.h
+++ b/include/configs/P1021MDS.h
@@ -383,6 +383,50 @@
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
+#define CONFIG_QE
+
+#ifdef CONFIG_QE
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000
+#define CONFIG_SYS_QE_FW_ADDR 0x10000000
+#define CONFIG_SYS_QE_FW_LENGTH 0x10000
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
+
+#define CONFIG_UEC_ETH
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1 /* GETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH5 /* GETH5 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH5
+#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
+#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
+#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
+#define CONFIG_SYS_UEC5_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
+#endif /* CONFIG_UEC_ETH2 */
+
+#endif /* CONFIG_QE */
+
/*
* I2C2 EEPROM
*/
@@ -425,6 +469,8 @@
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#endif
+#define CONFIG_E1000
+
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
@@ -458,6 +504,7 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
+#define CONFIG_MISC_INIT_R /* Call misc_init_r */
#define CONFIG_MMC
#ifdef CONFIG_MMC
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 18:41 [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Haiying.Wang at freescale.com
` (5 preceding siblings ...)
2011-01-31 18:41 ` [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support Haiying.Wang at freescale.com
@ 2011-01-31 19:39 ` Wolfgang Denk
2011-01-31 20:13 ` Scott Wood
2011-02-01 5:26 ` Kumar Gala
7 siblings, 1 reply; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 19:39 UTC (permalink / raw)
To: u-boot
Dear Haiying.Wang at freescale.com,
In message <1296499317-26616-1-git-send-email-Haiying.Wang@freescale.com> you wrote:
> This patchset adds support for TPL(Tertiary Program Loader) and P1021MDS board.
> It is a rework of patchset at
> http://lists.denx.de/pipermail/u-boot/2010-December/082881.html,
> addresses the comments from the list and is based on the top of the tree.
> It needs to be applied after patch
> http://lists.denx.de/pipermail/u-boot/2011-January/086346.html and patch
> http://lists.denx.de/pipermail/u-boot/2011-January/086524.html
I think these patches are incorrectly split.
[PATCH 1/6] Introduce the Tertiary Program loader
This patch adds stuff to the Makefile, which would result in
errors if used, as the referenced directories don't exist yet.
[PATCH 2/6] powerpc/85xx: add TPL support
This patch creates unused files, like
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
This makes no sense to me.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Misquotation is, in fact, the pride and privilege of the learned. A
widely-read man never quotes accurately, for the rather obvious
reason that he has read too widely.
- Hesketh Pearson _Common Misquotations_ introduction
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 18:41 ` [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support Haiying.Wang at freescale.com
@ 2011-01-31 20:03 ` Wolfgang Denk
2011-01-31 20:08 ` Scott Wood
` (2 more replies)
0 siblings, 3 replies; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 20:03 UTC (permalink / raw)
To: u-boot
Dear Haiying.Wang at freescale.com,
In message <1296499317-26616-4-git-send-email-Haiying.Wang@freescale.com> you wrote:
> From: Haiying Wang <Haiying.Wang@freescale.com>
>
> Support P1021MDS board to boot from NAND flash (No NOR flash on this
> board). And because P1021 only has 256K L2 SRAM, which can not used for final
> uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can
> be initialized in L2 SRAM through SPD code. So there are three stage uboot
> images:
> * nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND.
> * tpl_boot, 112KB size. The env variables are copied to offset 128KB
> in L2 SRAM, so that ddr spd code can get the interleaving mode setting in env.
> It loads final uboot image from offset 128KB in NAND.
> * final uboot image, size is variable depends on the functions enabled.
> diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk
> new file mode 100644
> index 0000000..3888f61
> --- /dev/null
> +++ b/board/freescale/p1021mds/config.mk
...
> +ifndef NAND_SPL
> +ifndef IN_TPL
> +ifeq ($(CONFIG_NAND), y)
> +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
> +endif
> +endif
> +endif
Why is this config.mk needed? Can you not do all this in the board
config file instead?
> diff --git a/board/freescale/p1021mds/ddr.c b/board/freescale/p1021mds/ddr.c
> new file mode 100644
> index 0000000..594a4a8
> --- /dev/null
> +++ b/board/freescale/p1021mds/ddr.c
It seems there are a number of functions here which ar actually shared
with other files, for example board/freescale/p1022ds/ddr.c.
I wonder if it is not possible to use more common code here - especially
given the fact that we already have a nice collection of such files:
board/freescale/corenet_ds/ddr.c
board/freescale/mpc8536ds/ddr.c
board/freescale/mpc8540ads/ddr.c
board/freescale/mpc8541cds/ddr.c
board/freescale/mpc8544ds/ddr.c
board/freescale/mpc8548cds/ddr.c
board/freescale/mpc8555cds/ddr.c
board/freescale/mpc8560ads/ddr.c
board/freescale/mpc8568mds/ddr.c
board/freescale/mpc8569mds/ddr.c
board/freescale/mpc8572ds/ddr.c
board/freescale/mpc8610hpcd/ddr.c
board/freescale/mpc8641hpcn/ddr.c
board/freescale/p1022ds/ddr.c
board/freescale/p1_p2_rdb/ddr.c
board/freescale/p2020ds/ddr.c
> diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c
> new file mode 100644
> index 0000000..c7a7e57
> --- /dev/null
> +++ b/board/freescale/p1021mds/p1021mds.c
...
> +extern void cpu_mp_lmb_reserve(struct lmb *lmb);
Please move prototypes to header file.
> +void board_lmb_reserve(struct lmb *lmb)
> +{
> + cpu_mp_lmb_reserve(lmb);
> +}
How many board/freescale/<name>/<name>.c file share this same code?
> diff --git a/board/freescale/p1021mds/tlb.c b/board/freescale/p1021mds/tlb.c
> new file mode 100644
> index 0000000..30af6dd
> --- /dev/null
> +++ b/board/freescale/p1021mds/tlb.c
How much of this is actually different from - say -
board/freescale/p1022ds/tlb.c ?
...
> +/*
> + * Environment Configuration
> + */
> +#define CONFIG_HOSTNAME p1021mds
> +#define CONFIG_ROOTPATH /nfsroot
> +#define CONFIG_BOOTFILE your.uImage
Please rather omit the setting instead of using fillers that are of no
practical value.
> +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
> +
> +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
> +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "netdev=eth0\0" \
> + "consoledev=ttyS0\0" \
> + "ramdiskaddr=2000000\0" \
> + "ramdiskfile=your.ramdisk.u-boot\0" \
Ditto. [BTW: why "....ramdisk.u-boot"? U-Boot does not use ramdisks.
The ramdisk is only used for some OS, so that should probably be
"...ramdisk.linux" instead?]
> + "fdtaddr=c00000\0" \
> + "fdtfile=your.fdt.dtb\0" \
Ditto. [Are "fdt" and "dtb" not redundant?]
> diff --git a/tpl/board/freescale/p1021mds/tpl_boot.c b/tpl/board/freescale/p1021mds/tpl_boot.c
> new file mode 100644
> index 0000000..386d76c
> --- /dev/null
> +++ b/tpl/board/freescale/p1021mds/tpl_boot.c
...
> +extern void nand_load(unsigned int offs, int uboot_size, uchar *dst);
> +extern phys_size_t init_ddr_dram(void);
Please move prototypes to header files.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Any sufficiently advanced bug is indistinguishable from a feature.
- Rich Kulawiec
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines.
2011-01-31 18:41 ` [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines Haiying.Wang at freescale.com
@ 2011-01-31 20:07 ` Wolfgang Denk
2011-01-31 21:08 ` Kumar Gala
1 sibling, 0 replies; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 20:07 UTC (permalink / raw)
To: u-boot
Dear Haiying.Wang at freescale.com,
In message <1296499317-26616-5-git-send-email-Haiying.Wang@freescale.com> you wrote:
> From: Haiying Wang <Haiying.Wang@freescale.com>
>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> ---
> arch/powerpc/include/asm/immap_85xx.h | 6 ++++++
> arch/powerpc/include/asm/immap_qe.h | 9 +++++++--
> 2 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
> index 6bd83ba..77e3629 100644
> --- a/arch/powerpc/include/asm/immap_85xx.h
> +++ b/arch/powerpc/include/asm/immap_85xx.h
> @@ -1948,6 +1948,12 @@ typedef struct ccsr_gur {
> u8 res10b[76];
> par_io_t qe_par_io[7];
> u8 res10c[1600];
> +#elif defined(CONFIG_P1021)
> + u8 res10b1[12];
> + u32 iovselsr;
> + u8 res10b2[60];
> + par_io_t qe_par_io[3];
> + u8 res10c[1496];
> #else
res10b1? Two levels of insertions already. Isn't it time to renumber
the reserved fields?
> @@ -601,13 +604,15 @@ extern qe_map_t *qe_immr;
> #define QE_MURAM_SIZE 0x10000UL
> #elif defined(CONFIG_MPC8569)
> #define QE_MURAM_SIZE 0x20000UL
> +#elif defined(CONFIG_P1021)
> +#define QE_MURAM_SIZE 0x6000UL
> #elif defined(CONFIG_MPC8360)
> #define QE_MURAM_SIZE 0xc000UL
> #elif defined(CONFIG_MPC832x)
> #define QE_MURAM_SIZE 0x4000UL
> #endif
Can you please keep the "if defined(..)" list sorted? Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If you want strict real-time behavior, run in the real time schedu-
ling class. But there are no seatbelts or airbags; main(){for(;;);}
can hard hang your system. -- Bart Smaalders
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 20:03 ` Wolfgang Denk
@ 2011-01-31 20:08 ` Scott Wood
2011-01-31 20:18 ` Wolfgang Denk
2011-01-31 21:39 ` Haiying Wang
2011-01-31 21:40 ` Kumar Gala
2 siblings, 1 reply; 46+ messages in thread
From: Scott Wood @ 2011-01-31 20:08 UTC (permalink / raw)
To: u-boot
On Mon, 31 Jan 2011 21:03:17 +0100
Wolfgang Denk <wd@denx.de> wrote:
> > +/*
> > + * Environment Configuration
> > + */
> > +#define CONFIG_HOSTNAME p1021mds
> > +#define CONFIG_ROOTPATH /nfsroot
> > +#define CONFIG_BOOTFILE your.uImage
>
> Please rather omit the setting instead of using fillers that are of no
> practical value.
Well, they do make it easier for a user to quickly see what the names
are that U-Boot expects for such commonly used things, rather than
having to scan the manual.
> > +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
> > +
> > +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
> > +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
> > +
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > + "netdev=eth0\0" \
> > + "consoledev=ttyS0\0" \
> > + "ramdiskaddr=2000000\0" \
> > + "ramdiskfile=your.ramdisk.u-boot\0" \
>
> Ditto. [BTW: why "....ramdisk.u-boot"? U-Boot does not use ramdisks.
> The ramdisk is only used for some OS, so that should probably be
> "...ramdisk.linux" instead?]
We often use the ".u-boot" suffix on ramdisks that have been wrapped
with a uImage header.
-Scott
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
2011-01-31 18:41 ` [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash Haiying.Wang at freescale.com
@ 2011-01-31 20:08 ` Wolfgang Denk
2011-01-31 21:02 ` Haiying Wang
0 siblings, 1 reply; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 20:08 UTC (permalink / raw)
To: u-boot
Dear Haiying.Wang at freescale.com,
In message <1296499317-26616-6-git-send-email-Haiying.Wang@freescale.com> you wrote:
> From: Haiying Wang <Haiying.Wang@freescale.com>
>
> For some board which doesn't have NOR flash and the QE's firmware(ucode) is
> saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will
> call it later after nand is initialized.
Is there a pressing reason to do this so early for other boards? Can
not all boards initialize this later?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"I didn't know it was impossible when I did it."
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-01-31 18:41 ` [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support Haiying.Wang at freescale.com
@ 2011-01-31 20:11 ` Wolfgang Denk
2011-01-31 20:50 ` Haiying Wang
0 siblings, 1 reply; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 20:11 UTC (permalink / raw)
To: u-boot
Dear Haiying.Wang at freescale.com,
In message <1296499317-26616-7-git-send-email-Haiying.Wang@freescale.com> you wrote:
> From: Haiying Wang <Haiying.Wang@freescale.com>
>
> P1021 has some QE pins which need to be set in pmuxcr register before using QE
> functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
> QE9 and QE12 are set for MII management. QE12 needs to be released after MII
> access because QE12 pin is muxed with LBCTL signal.
>
> P1021MDS has to load the microcode from NAND flash, this patch defines
> misc_init_r() for loading ucode and initializing qe.
...
> diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
> index 282ab23..04d7987 100644
> --- a/drivers/qe/uec.c
> +++ b/drivers/qe/uec.c
...
> +#ifdef CONFIG_P1021
> +#define BCSR11_ENET_MICRST 0x20
> +#endif
>
> /* Default UTBIPAR SMI address */
> #ifndef CONFIG_UTBIPAR_INIT_TBIPA
> @@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev)
> {
> uec_private_t *uec = (uec_private_t *)dev->priv;
>
> +#ifdef CONFIG_P1021
> + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +
> + /* QE9 and QE12 need to be set for enabling QE MII managment signals */
> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
> +#endif
...
Can we please avoid having board specific code in common files?
If this is really necessary, it shoud be a feature-specific #define,
not a board specific one.
> @@ -425,6 +469,8 @@
> #define CONFIG_PCI_PNP /* do pci plug-and-play */
> #endif
>
> +#define CONFIG_E1000
In which way is this change related to this commit?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is better to marry than to burn.
- Bible ``I Corinthians'' ch. 7, v. 9
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 19:39 ` [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Wolfgang Denk
@ 2011-01-31 20:13 ` Scott Wood
2011-01-31 20:22 ` Wolfgang Denk
0 siblings, 1 reply; 46+ messages in thread
From: Scott Wood @ 2011-01-31 20:13 UTC (permalink / raw)
To: u-boot
On Mon, 31 Jan 2011 20:39:51 +0100
Wolfgang Denk <wd@denx.de> wrote:
> Dear Haiying.Wang at freescale.com,
>
> In message <1296499317-26616-1-git-send-email-Haiying.Wang@freescale.com> you wrote:
> > This patchset adds support for TPL(Tertiary Program Loader) and P1021MDS board.
> > It is a rework of patchset at
> > http://lists.denx.de/pipermail/u-boot/2010-December/082881.html,
> > addresses the comments from the list and is based on the top of the tree.
> > It needs to be applied after patch
> > http://lists.denx.de/pipermail/u-boot/2011-January/086346.html and patch
> > http://lists.denx.de/pipermail/u-boot/2011-January/086524.html
>
> I think these patches are incorrectly split.
I think the intent was to split the arch-neutral stuff from the 85xx
stuff from the board stuff -- you'd rather they be all bunched together?
> [PATCH 1/6] Introduce the Tertiary Program loader
>
> This patch adds stuff to the Makefile, which would result in
> errors if used, as the referenced directories don't exist yet.
Lots of patches add features, disabled by default, that require CPU or
board code to provide things, that would cause errors if the feature
were enabled on a board otherwise.
I don't think it's even possible to add an empty directory with git.
> [PATCH 2/6] powerpc/85xx: add TPL support
>
> This patch creates unused files, like
> arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
It gets used in later in the patchset, when a board with tpl is added.
-Scott
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 20:08 ` Scott Wood
@ 2011-01-31 20:18 ` Wolfgang Denk
2011-01-31 20:23 ` Scott Wood
0 siblings, 1 reply; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 20:18 UTC (permalink / raw)
To: u-boot
Dear Scott Wood,
In message <20110131140801.33609642@udp111988uds.am.freescale.net> you wrote:
>
> > Please rather omit the setting instead of using fillers that are of no
> > practical value.
>
> Well, they do make it easier for a user to quickly see what the names
> are that U-Boot expects for such commonly used things, rather than
> having to scan the manual.
I doubt both the "quicly see" part (in such a long list of settings)
and the "rather than having to scan the manual" part.
> > > + "ramdiskfile=your.ramdisk.u-boot\0" \
> >
> > Ditto. [BTW: why "....ramdisk.u-boot"? U-Boot does not use ramdisks.
> > The ramdisk is only used for some OS, so that should probably be
> > "...ramdisk.linux" instead?]
>
> We often use the ".u-boot" suffix on ramdisks that have been wrapped
> with a uImage header.
That would be a "uRamdisk" then (similar to uImage).
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It usually takes more than three weeks to prepare a good impromptu
speech. - Mark Twain
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 20:13 ` Scott Wood
@ 2011-01-31 20:22 ` Wolfgang Denk
2011-01-31 20:31 ` Scott Wood
0 siblings, 1 reply; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 20:22 UTC (permalink / raw)
To: u-boot
Dear Scott Wood,
In message <20110131141332.5a4a297d@udp111988uds.am.freescale.net> you wrote:
>
> > I think these patches are incorrectly split.
>
> I think the intent was to split the arch-neutral stuff from the 85xx
> stuff from the board stuff -- you'd rather they be all bunched together?
No, of course not all together.
> > This patch adds stuff to the Makefile, which would result in
> > errors if used, as the referenced directories don't exist yet.
>
> Lots of patches add features, disabled by default, that require CPU or
> board code to provide things, that would cause errors if the feature
> were enabled on a board otherwise.
But here nothing is disabled. It's added to the top level Makefile.
It's dead code if unused, and causes errors if used. WHy not add the
tpl target when you actually add the tpl code?
> I don't think it's even possible to add an empty directory with git.
True. Butt that would not fix anythign, it would still not work.
> > [PATCH 2/6] powerpc/85xx: add TPL support
> >
> > This patch creates unused files, like
> > arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
>
> It gets used in later in the patchset, when a board with tpl is added.
Then this is where that file belongs to.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Eureka! -- Archimedes
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 20:18 ` Wolfgang Denk
@ 2011-01-31 20:23 ` Scott Wood
0 siblings, 0 replies; 46+ messages in thread
From: Scott Wood @ 2011-01-31 20:23 UTC (permalink / raw)
To: u-boot
On Mon, 31 Jan 2011 21:18:35 +0100
Wolfgang Denk <wd@denx.de> wrote:
> Dear Scott Wood,
>
> In message <20110131140801.33609642@udp111988uds.am.freescale.net> you wrote:
> >
> > > Please rather omit the setting instead of using fillers that are of no
> > > practical value.
> >
> > Well, they do make it easier for a user to quickly see what the names
> > are that U-Boot expects for such commonly used things, rather than
> > having to scan the manual.
>
> I doubt both the "quicly see" part (in such a long list of settings)
> and the "rather than having to scan the manual" part.
I've found it convenient, along with the more meaningful error
messages if I forget to replace one of them. YMMV.
> > > > + "ramdiskfile=your.ramdisk.u-boot\0" \
> > >
> > > Ditto. [BTW: why "....ramdisk.u-boot"? U-Boot does not use ramdisks.
> > > The ramdisk is only used for some OS, so that should probably be
> > > "...ramdisk.linux" instead?]
> >
> > We often use the ".u-boot" suffix on ramdisks that have been wrapped
> > with a uImage header.
>
> That would be a "uRamdisk" then (similar to uImage).
Is anyone actually calling it that? What if I have multiple ramdisk
images that I want to call different names?
FWIW, for non-Linux OS images we sometimes use .uImage as a suffix.
-Scott
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 20:22 ` Wolfgang Denk
@ 2011-01-31 20:31 ` Scott Wood
2011-01-31 20:39 ` Kumar Gala
2011-01-31 20:50 ` Wolfgang Denk
0 siblings, 2 replies; 46+ messages in thread
From: Scott Wood @ 2011-01-31 20:31 UTC (permalink / raw)
To: u-boot
On Mon, 31 Jan 2011 21:22:04 +0100
Wolfgang Denk <wd@denx.de> wrote:
> Dear Scott Wood,
>
> In message <20110131141332.5a4a297d@udp111988uds.am.freescale.net> you wrote:
> >
> > > I think these patches are incorrectly split.
> >
> > I think the intent was to split the arch-neutral stuff from the 85xx
> > stuff from the board stuff -- you'd rather they be all bunched together?
>
> No, of course not all together.
>
> > > This patch adds stuff to the Makefile, which would result in
> > > errors if used, as the referenced directories don't exist yet.
> >
> > Lots of patches add features, disabled by default, that require CPU or
> > board code to provide things, that would cause errors if the feature
> > were enabled on a board otherwise.
>
> But here nothing is disabled. It's added to the top level Makefile.
> It's dead code if unused, and causes errors if used. WHy not add the
> tpl target when you actually add the tpl code?
>
> > I don't think it's even possible to add an empty directory with git.
>
> True. Butt that would not fix anythign, it would still not work.
>
> > > [PATCH 2/6] powerpc/85xx: add TPL support
> > >
> > > This patch creates unused files, like
> > > arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
> >
> > It gets used in later in the patchset, when a board with tpl is added.
>
> Then this is where that file belongs to.
I'm confused. You say "of course not all together", but the first one
you say to include with the second, and the second you say to include
with the third.
If you're suggesting keeping them mostly separate, but just moving some
bits into the subsequent patch, that makes no sense to me. They
logically belong where they are -- e.g.
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds is part of 85xx TPL support, it
is not p1021mds-specific. And every bit of the first two patches is
technically dead until a board is added that uses it.
Has your aversion to "dead" code grown so strong it can't exist even in
a transitory state between members of a patchset, even when necessary
to avoid mixing users of a facility with the facility itself in the
same patch? I think that would do significant harm to reviewability.
-Scott
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 20:31 ` Scott Wood
@ 2011-01-31 20:39 ` Kumar Gala
2011-01-31 20:50 ` Wolfgang Denk
2011-01-31 20:50 ` Wolfgang Denk
1 sibling, 1 reply; 46+ messages in thread
From: Kumar Gala @ 2011-01-31 20:39 UTC (permalink / raw)
To: u-boot
On Jan 31, 2011, at 2:31 PM, Scott Wood wrote:
> On Mon, 31 Jan 2011 21:22:04 +0100
> Wolfgang Denk <wd@denx.de> wrote:
>
>> Dear Scott Wood,
>>
>> In message <20110131141332.5a4a297d@udp111988uds.am.freescale.net> you wrote:
>>>
>>>> I think these patches are incorrectly split.
>>>
>>> I think the intent was to split the arch-neutral stuff from the 85xx
>>> stuff from the board stuff -- you'd rather they be all bunched together?
>>
>> No, of course not all together.
>>
>>>> This patch adds stuff to the Makefile, which would result in
>>>> errors if used, as the referenced directories don't exist yet.
>>>
>>> Lots of patches add features, disabled by default, that require CPU or
>>> board code to provide things, that would cause errors if the feature
>>> were enabled on a board otherwise.
>>
>> But here nothing is disabled. It's added to the top level Makefile.
>> It's dead code if unused, and causes errors if used. WHy not add the
>> tpl target when you actually add the tpl code?
>>
>>> I don't think it's even possible to add an empty directory with git.
>>
>> True. Butt that would not fix anythign, it would still not work.
>>
>>>> [PATCH 2/6] powerpc/85xx: add TPL support
>>>>
>>>> This patch creates unused files, like
>>>> arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
>>>
>>> It gets used in later in the patchset, when a board with tpl is added.
>>
>> Then this is where that file belongs to.
>
> I'm confused. You say "of course not all together", but the first one
> you say to include with the second, and the second you say to include
> with the third.
>
> If you're suggesting keeping them mostly separate, but just moving some
> bits into the subsequent patch, that makes no sense to me. They
> logically belong where they are -- e.g.
> arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds is part of 85xx TPL support, it
> is not p1021mds-specific. And every bit of the first two patches is
> technically dead until a board is added that uses it.
>
> Has your aversion to "dead" code grown so strong it can't exist even in
> a transitory state between members of a patchset, even when necessary
> to avoid mixing users of a facility with the facility itself in the
> same patch? I think that would do significant harm to reviewability.
>
> -Scott
I'm in agreement with Scott on this. I believe we've taken this a bit too far about "dead code". It should be reasonable in a patch series to have code that will be used in a subsequent patch.
- k
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-01-31 20:11 ` Wolfgang Denk
@ 2011-01-31 20:50 ` Haiying Wang
2011-01-31 21:28 ` Kumar Gala
0 siblings, 1 reply; 46+ messages in thread
From: Haiying Wang @ 2011-01-31 20:50 UTC (permalink / raw)
To: u-boot
On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote:
> >
> > +#ifdef CONFIG_P1021
> > + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > +
> > + /* QE9 and QE12 need to be set for enabling QE MII managment signals */
> > + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
> > + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
> > +#endif
> ...
>
> Can we please avoid having board specific code in common files?
I wish I could, but only P1021 has such pin mux problems.
> If this is really necessary, it shoud be a feature-specific #define,
> not a board specific one.
I don't know whether this *feature* will show up on other SoC. But if
you insist, I can use CONFIG_QE_PIN_MUX.
Thanks.
Haiying
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 20:31 ` Scott Wood
2011-01-31 20:39 ` Kumar Gala
@ 2011-01-31 20:50 ` Wolfgang Denk
2011-01-31 21:15 ` Scott Wood
1 sibling, 1 reply; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 20:50 UTC (permalink / raw)
To: u-boot
Dear Scott Wood,
In message <20110131143141.2959da63@udp111988uds.am.freescale.net> you wrote:
>
> I'm confused. You say "of course not all together", but the first one
> you say to include with the second, and the second you say to include
> with the third.
I did not say this.
> If you're suggesting keeping them mostly separate, but just moving some
> bits into the subsequent patch, that makes no sense to me. They
> logically belong where they are -- e.g.
Come on. Read what I wrote.
> Has your aversion to "dead" code grown so strong it can't exist even in
> a transitory state between members of a patchset, even when necessary
> to avoid mixing users of a facility with the facility itself in the
> same patch? I think that would do significant harm to reviewability.
Calm down, and re-read what I wrote.
For example, why must we add the Makefile changes in the first step,
when all the code it references is still missing? Should this not be
the last step?
And what is the benefit of adding documentation to the README here?
To me it makes more sense to add this when CONFIG_HAS_TPL and
CONFIG_IN_TPL get used first.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Plans break down. You cannot plan the future. Only presumptuous fools
plan. The wise man _steers_. - Terry Pratchett, _Making_Money_
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 20:39 ` Kumar Gala
@ 2011-01-31 20:50 ` Wolfgang Denk
0 siblings, 0 replies; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 20:50 UTC (permalink / raw)
To: u-boot
Dear Kumar Gala,
In message <C6334D93-A826-4C68-9477-2BAEEE681EF1@kernel.crashing.org> you wrote:
>
...
> I'm in agreement with Scott on this. I believe we've taken this a bit
> too far about "dead code". It should be reasonable in a patch series to
> have code that will be used in a subsequent patch.
Yes, but you should not enable it or add it to Makefiles before it's
even there.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
You go slow, be gentle. It's no one-way street -- you know how you
feel and that's all. It's how the girl feels too. Don't press. If the
girl feels anything for you at all, you'll know.
-- Kirk, "Charlie X", stardate 1535.8
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
2011-01-31 20:08 ` Wolfgang Denk
@ 2011-01-31 21:02 ` Haiying Wang
2011-01-31 21:37 ` Wolfgang Denk
0 siblings, 1 reply; 46+ messages in thread
From: Haiying Wang @ 2011-01-31 21:02 UTC (permalink / raw)
To: u-boot
On Mon, 2011-01-31 at 21:08 +0100, Wolfgang Denk wrote:
> Dear Haiying.Wang at freescale.com,
>
> In message <1296499317-26616-6-git-send-email-Haiying.Wang@freescale.com> you wrote:
> > From: Haiying Wang <Haiying.Wang@freescale.com>
> >
> > For some board which doesn't have NOR flash and the QE's firmware(ucode) is
> > saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will
> > call it later after nand is initialized.
>
> Is there a pressing reason to do this so early for other boards? Can
> not all boards initialize this later?
>
My understanding is that QE is a cpu feature, so it is called early in
cpu_init_r. As Kumar recommended before, I can move qe_init from
cpu_init_r to misc_init_r for every 85xx boards with qe support. Is it
acceptable to you?
Haiying
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines.
2011-01-31 18:41 ` [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines Haiying.Wang at freescale.com
2011-01-31 20:07 ` Wolfgang Denk
@ 2011-01-31 21:08 ` Kumar Gala
2011-01-31 23:36 ` Timur Tabi
1 sibling, 1 reply; 46+ messages in thread
From: Kumar Gala @ 2011-01-31 21:08 UTC (permalink / raw)
To: u-boot
On Jan 31, 2011, at 12:41 PM, <Haiying.Wang@freescale.com> <Haiying.Wang@freescale.com> wrote:
> From: Haiying Wang <Haiying.Wang@freescale.com>
>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> ---
> arch/powerpc/include/asm/immap_85xx.h | 6 ++++++
> arch/powerpc/include/asm/immap_qe.h | 9 +++++++--
> 2 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
> index 6bd83ba..77e3629 100644
> --- a/arch/powerpc/include/asm/immap_85xx.h
> +++ b/arch/powerpc/include/asm/immap_85xx.h
> @@ -1948,6 +1948,12 @@ typedef struct ccsr_gur {
> u8 res10b[76];
> par_io_t qe_par_io[7];
> u8 res10c[1600];
> +#elif defined(CONFIG_P1021)
> + u8 res10b1[12];
> + u32 iovselsr;
> + u8 res10b2[60];
> + par_io_t qe_par_io[3];
> + u8 res10c[1496];
> #else
> u8 res10b[1868];
> #endif
> diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
> index 531cfc8..0fffba2 100644
> --- a/arch/powerpc/include/asm/immap_qe.h
> +++ b/arch/powerpc/include/asm/immap_qe.h
> @@ -3,7 +3,7 @@
> * The Internal Memory Map for devices with QE on them. This
> * is the superset of all QE devices (8360, etc.).
> *
> - * Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
> + * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
> * Author: Shlomi Gridih <gridish@freescale.com>
> *
> * This program is free software; you can redistribute it and/or modify it
> @@ -588,6 +588,9 @@ typedef struct qe_immap {
> #elif defined(CONFIG_MPC8569)
> u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */
> u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */
> +#elif defined(CONFIG_P1021)
> + u8 muram[0x06000]; /* 0x1_0000 - 0x1_6000 Multi-user RAM */
> + u8 res17[0x1a000]; /* 0x1_6000 - 0x3_0000 */
> #else
> u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
> u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
Can we reduce this mess with using QE_MURAM_SIZE?
u8 muram[QE_MURAM_SIZE];
u8 res17[0xNNNN - QE_MURAM_SIZE];
> @@ -601,13 +604,15 @@ extern qe_map_t *qe_immr;
> #define QE_MURAM_SIZE 0x10000UL
> #elif defined(CONFIG_MPC8569)
> #define QE_MURAM_SIZE 0x20000UL
> +#elif defined(CONFIG_P1021)
> +#define QE_MURAM_SIZE 0x6000UL
> #elif defined(CONFIG_MPC8360)
> #define QE_MURAM_SIZE 0xc000UL
> #elif defined(CONFIG_MPC832x)
> #define QE_MURAM_SIZE 0x4000UL
> #endif
>
> -#if defined(CONFIG_MPC8323)
> +#if defined(CONFIG_MPC8323) || defined(CONFIG_P1021)
> #define MAX_QE_RISC 1
> #define QE_NUM_OF_SNUM 28
> #elif defined(CONFIG_MPC8569)
We can move some of these into include/config_mpc85xx.h
> --
> 1.7.3.1.50.g1e633
>
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 20:50 ` Wolfgang Denk
@ 2011-01-31 21:15 ` Scott Wood
2011-01-31 21:34 ` Wolfgang Denk
0 siblings, 1 reply; 46+ messages in thread
From: Scott Wood @ 2011-01-31 21:15 UTC (permalink / raw)
To: u-boot
On Mon, 31 Jan 2011 21:50:57 +0100
Wolfgang Denk <wd@denx.de> wrote:
> Dear Scott Wood,
>
> In message <20110131143141.2959da63@udp111988uds.am.freescale.net> you wrote:
> >
> > I'm confused. You say "of course not all together", but the first one
> > you say to include with the second, and the second you say to include
> > with the third.
>
> I did not say this.
"WHy not add the tpl target when you actually add the tpl code?"
"Then this is where that file belongs to."
> > Has your aversion to "dead" code grown so strong it can't exist even in
> > a transitory state between members of a patchset, even when necessary
> > to avoid mixing users of a facility with the facility itself in the
> > same patch? I think that would do significant harm to reviewability.
>
> Calm down, and re-read what I wrote.
I am calm, albeit confused and a bit frustrated.
I did re-read it and I'm still not sure exactly what you want.
> For example, why must we add the Makefile changes in the first step,
> when all the code it references is still missing? Should this not be
> the last step?
If you make it the last step, then the board will exist but not be
buildable in the previous step (unless you combine them, but you said
that's not what you're asking for). How is that better? And is this
really worth bickering about?
Please just say, clearly and specifically, what you want the patchset
to look like...
> And what is the benefit of adding documentation to the README here?
> To me it makes more sense to add this when CONFIG_HAS_TPL and
> CONFIG_IN_TPL get used first.
Because it's not specific to 85xx or p1021mds. The generic
infrastructure for TPL consists of the makefile changes and
documentation. It seems useful to me to separate that for review, but
if you want it squashed into a board-specific patch instead, fine.
Just tell us what you want to see.
-Scott
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-01-31 20:50 ` Haiying Wang
@ 2011-01-31 21:28 ` Kumar Gala
2011-02-01 3:14 ` Haiying Wang
0 siblings, 1 reply; 46+ messages in thread
From: Kumar Gala @ 2011-01-31 21:28 UTC (permalink / raw)
To: u-boot
On Jan 31, 2011, at 2:50 PM, Haiying Wang wrote:
> On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote:
>>>
>>> +#ifdef CONFIG_P1021
>>> + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
>>> +
>>> + /* QE9 and QE12 need to be set for enabling QE MII managment signals */
>>> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
>>> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
>>> +#endif
>> ...
>>
>> Can we please avoid having board specific code in common files?
> I wish I could, but only P1021 has such pin mux problems.
>
>> If this is really necessary, it shoud be a feature-specific #define,
>> not a board specific one.
> I don't know whether this *feature* will show up on other SoC. But if
> you insist, I can use CONFIG_QE_PIN_MUX.
>
> Thanks.
>
> Haiying
I think pin muxing is a board level decision so it seems like board code is the right place for it.
- k
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 21:15 ` Scott Wood
@ 2011-01-31 21:34 ` Wolfgang Denk
2011-01-31 22:07 ` Scott Wood
0 siblings, 1 reply; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 21:34 UTC (permalink / raw)
To: u-boot
Dear Scott Wood,
In message <20110131151506.700ddcd7@udp111988uds.am.freescale.net> you wrote:
>
> > For example, why must we add the Makefile changes in the first step,
> > when all the code it references is still missing? Should this not be
> > the last step?
>
> If you make it the last step, then the board will exist but not be
> buildable in the previous step (unless you combine them, but you said
> that's not what you're asking for). How is that better? And is this
> really worth bickering about?
Yes, this is better, and this is how we always do it: add the featurs,
but not enable them unless we have all together, then add the needed
#defines and make rules to actually use the code.
> Please just say, clearly and specifically, what you want the patchset
> to look like...
>
> > And what is the benefit of adding documentation to the README here?
> > To me it makes more sense to add this when CONFIG_HAS_TPL and
> > CONFIG_IN_TPL get used first.
>
> Because it's not specific to 85xx or p1021mds. The generic
> infrastructure for TPL consists of the makefile changes and
> documentation. It seems useful to me to separate that for review, but
A dead / broken make rule and dead documentation is what the generic
infrastructure for TPL consists of?
> if you want it squashed into a board-specific patch instead, fine.
> Just tell us what you want to see.
I already did, but here we go:
First, please do not add make rules before you have code they apply
to. After doing this, there is this rudimentary patch to the README.
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
2011-01-31 21:02 ` Haiying Wang
@ 2011-01-31 21:37 ` Wolfgang Denk
2011-02-02 4:29 ` Kumar Gala
0 siblings, 1 reply; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 21:37 UTC (permalink / raw)
To: u-boot
Dear Haiying Wang,
In message <1296507737.2049.518.camel@haiying-laptop> you wrote:
> On Mon, 2011-01-31 at 21:08 +0100, Wolfgang Denk wrote:
> > Dear Haiying.Wang at freescale.com,
> >
> > In message <1296499317-26616-6-git-send-email-Haiying.Wang@freescale.com> you wrote:
> > > From: Haiying Wang <Haiying.Wang@freescale.com>
> > >
> > > For some board which doesn't have NOR flash and the QE's firmware(ucode) is
> > > saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will
> > > call it later after nand is initialized.
> >
> > Is there a pressing reason to do this so early for other boards? Can
> > not all boards initialize this later?
> >
> My understanding is that QE is a cpu feature, so it is called early in
> cpu_init_r. As Kumar recommended before, I can move qe_init from
> cpu_init_r to misc_init_r for every 85xx boards with qe support. Is it
> acceptable to you?
Yes, if this way we can avoid to do the same thing at different
points in the initialization sequence.
Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Save yourself! Reboot in 5 seconds!
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 20:03 ` Wolfgang Denk
2011-01-31 20:08 ` Scott Wood
@ 2011-01-31 21:39 ` Haiying Wang
2011-01-31 22:05 ` Kumar Gala
2011-01-31 22:14 ` Wolfgang Denk
2011-01-31 21:40 ` Kumar Gala
2 siblings, 2 replies; 46+ messages in thread
From: Haiying Wang @ 2011-01-31 21:39 UTC (permalink / raw)
To: u-boot
On Mon, 2011-01-31 at 21:03 +0100, Wolfgang Denk wrote:
> Dear Haiying.Wang at freescale.com,
> > diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk
> > new file mode 100644
> > index 0000000..3888f61
> > --- /dev/null
> > +++ b/board/freescale/p1021mds/config.mk
> ...
> > +ifndef NAND_SPL
> > +ifndef IN_TPL
> > +ifeq ($(CONFIG_NAND), y)
> > +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
> > +endif
> > +endif
> > +endif
>
> Why is this config.mk needed? Can you not do all this in the board
> config file instead?
Do you mean the board header file or arch/powerpc/config.mk? I did not see any LDSCRIPT defined in Freescale board header file.
> > diff --git a/board/freescale/p1021mds/ddr.c b/board/freescale/p1021mds/ddr.c
> > new file mode 100644
> > index 0000000..594a4a8
> > --- /dev/null
> > +++ b/board/freescale/p1021mds/ddr.c
>
> It seems there are a number of functions here which ar actually shared
> with other files, for example board/freescale/p1022ds/ddr.c.
Every boards has its board specific ddr parameters which are defined the its own board ddr.c. The common code for ddr has been defined in arch/powerpc/cpu/mpc8xxx/ddr/.
> I wonder if it is not possible to use more common code here - especially
> given the fact that we already have a nice collection of such files:
>
> board/freescale/corenet_ds/ddr.c
> board/freescale/mpc8536ds/ddr.c
> board/freescale/mpc8540ads/ddr.c
> board/freescale/mpc8541cds/ddr.c
> board/freescale/mpc8544ds/ddr.c
> board/freescale/mpc8548cds/ddr.c
> board/freescale/mpc8555cds/ddr.c
> board/freescale/mpc8560ads/ddr.c
> board/freescale/mpc8568mds/ddr.c
> board/freescale/mpc8569mds/ddr.c
> board/freescale/mpc8572ds/ddr.c
> board/freescale/mpc8610hpcd/ddr.c
> board/freescale/mpc8641hpcn/ddr.c
> board/freescale/p1022ds/ddr.c
> board/freescale/p1_p2_rdb/ddr.c
> board/freescale/p2020ds/ddr.c
If you go to see each ddr.c, you can find there is
fsl_ddr_board_options() which defines the different values for each
board. Also fsl_ddr_get_spd() is also highly dependent on board, like
ddr type(ddr2 or ddr3), i2c spd eeprom address, ddr controller# etc.
Only fsl_ddr_get_mem_data_rate()might be moved to common code.
> > +void board_lmb_reserve(struct lmb *lmb)
> > +{
> > + cpu_mp_lmb_reserve(lmb);
> > +}
>
> How many board/freescale/<name>/<name>.c file share this same code?
There are some, but I don't know whether there will be difference coming in later.
>
> > diff --git a/board/freescale/p1021mds/tlb.c b/board/freescale/p1021mds/tlb.c
> > new file mode 100644
> > index 0000000..30af6dd
> > --- /dev/null
> > +++ b/board/freescale/p1021mds/tlb.c
>
> How much of this is actually different from - say -
> board/freescale/p1022ds/tlb.c ?
The tlb.c is also a highly board dependent file. Different boards have different supported peripherals. If you look at p1021 and p1022's tlb.c files, you can see p1022ds has 3 PCIE, P1021 has 2, P1022ds has NOR flash, P1021MDS only has NAND flash... etc.
Haiying
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 20:03 ` Wolfgang Denk
2011-01-31 20:08 ` Scott Wood
2011-01-31 21:39 ` Haiying Wang
@ 2011-01-31 21:40 ` Kumar Gala
2 siblings, 0 replies; 46+ messages in thread
From: Kumar Gala @ 2011-01-31 21:40 UTC (permalink / raw)
To: u-boot
> It seems there are a number of functions here which ar actually shared
> with other files, for example board/freescale/p1022ds/ddr.c.
>
> I wonder if it is not possible to use more common code here - especially
> given the fact that we already have a nice collection of such files:
>
> board/freescale/corenet_ds/ddr.c
> board/freescale/mpc8536ds/ddr.c
> board/freescale/mpc8540ads/ddr.c
> board/freescale/mpc8541cds/ddr.c
> board/freescale/mpc8544ds/ddr.c
> board/freescale/mpc8548cds/ddr.c
> board/freescale/mpc8555cds/ddr.c
> board/freescale/mpc8560ads/ddr.c
> board/freescale/mpc8568mds/ddr.c
> board/freescale/mpc8569mds/ddr.c
> board/freescale/mpc8572ds/ddr.c
> board/freescale/mpc8610hpcd/ddr.c
> board/freescale/mpc8641hpcn/ddr.c
> board/freescale/p1022ds/ddr.c
> board/freescale/p1_p2_rdb/ddr.c
> board/freescale/p2020ds/ddr.c
We've already done that, the code in these files is board specific params/tuning of DDR params.
>
>> diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c
>> new file mode 100644
>> index 0000000..c7a7e57
>> --- /dev/null
>> +++ b/board/freescale/p1021mds/p1021mds.c
> ...
>> +extern void cpu_mp_lmb_reserve(struct lmb *lmb);
We have this in <asm/mp.h> already.
Will cleanup the other guys
> Please move prototypes to header file.
>
>> +void board_lmb_reserve(struct lmb *lmb)
>> +{
>> + cpu_mp_lmb_reserve(lmb);
>> +}
>
> How many board/freescale/<name>/<name>.c file share this same code?
All of our multicore parts do this, we could move this into other places like arch_lmb_reserve().
>> diff --git a/board/freescale/p1021mds/tlb.c b/board/freescale/p1021mds/tlb.c
>> new file mode 100644
>> index 0000000..30af6dd
>> --- /dev/null
>> +++ b/board/freescale/p1021mds/tlb.c
>
> How much of this is actually different from - say -
> board/freescale/p1022ds/tlb.c ?
Its mostly board specific.
- k
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 21:39 ` Haiying Wang
@ 2011-01-31 22:05 ` Kumar Gala
2011-01-31 22:16 ` Wolfgang Denk
2011-01-31 22:14 ` Wolfgang Denk
1 sibling, 1 reply; 46+ messages in thread
From: Kumar Gala @ 2011-01-31 22:05 UTC (permalink / raw)
To: u-boot
On Jan 31, 2011, at 3:39 PM, Haiying Wang wrote:
> On Mon, 2011-01-31 at 21:03 +0100, Wolfgang Denk wrote:
>> Dear Haiying.Wang at freescale.com,
>>> diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk
>>> new file mode 100644
>>> index 0000000..3888f61
>>> --- /dev/null
>>> +++ b/board/freescale/p1021mds/config.mk
>> ...
>>> +ifndef NAND_SPL
>>> +ifndef IN_TPL
>>> +ifeq ($(CONFIG_NAND), y)
>>> +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
>>> +endif
>>> +endif
>>> +endif
>>
>> Why is this config.mk needed? Can you not do all this in the board
>> config file instead?
> Do you mean the board header file or arch/powerpc/config.mk? I did not see any LDSCRIPT defined in Freescale board header file.
I think something like:
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index e6b60cf..f2d6cdb 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -37,6 +37,7 @@
#define CONFIG_NAND_U_BOOT
#define CONFIG_RAMBOOT_NAND
#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of mon
- k
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 21:34 ` Wolfgang Denk
@ 2011-01-31 22:07 ` Scott Wood
2011-01-31 22:40 ` Wolfgang Denk
0 siblings, 1 reply; 46+ messages in thread
From: Scott Wood @ 2011-01-31 22:07 UTC (permalink / raw)
To: u-boot
On Mon, 31 Jan 2011 22:34:34 +0100
Wolfgang Denk <wd@denx.de> wrote:
> Dear Scott Wood,
>
> In message <20110131151506.700ddcd7@udp111988uds.am.freescale.net> you wrote:
> >
> > > For example, why must we add the Makefile changes in the first step,
> > > when all the code it references is still missing? Should this not be
> > > the last step?
> >
> > If you make it the last step, then the board will exist but not be
> > buildable in the previous step (unless you combine them, but you said
> > that's not what you're asking for). How is that better? And is this
> > really worth bickering about?
>
> Yes, this is better, and this is how we always do it: add the featurs,
> but not enable them unless we have all together, then add the needed
> #defines and make rules to actually use the code.
Those two "this"es don't match.
The latter is what we did do. We added TPL, but it wasn't enabled
until a board actually turns on CONFIG_HAS_TPL.
The former, what I was asking above if it was what you meant, would be
to have the board be added, enabling CONFIG_HAS_TPL because that's the
only way this board can be built, with a commit that is broken until
the subsequent commit adding TPL to the toplevel makefile is added. Or
to have the toplevel makefile changes squashed into the board patch.
It's not as if this is a make rule pointing at a specific file (with no
$(BOARDDIR)) that is absent.
> > Because it's not specific to 85xx or p1021mds. The generic
> > infrastructure for TPL consists of the makefile changes and
> > documentation. It seems useful to me to separate that for review, but
>
> A dead / broken make rule and dead documentation is what the generic
> infrastructure for TPL consists of?
What is broken about it?
Yes, the makefile change and documentation are what the generic
infrastructure for TPL consists of. Yes, it's inactive until a board
enables the feature ("when we have all together"), at which point the
board is required to provide tpl/board/$(BOARDDIR)/Makefile. Code
which is not board-specific is pulled from nand_spl and main U-Boot via
this board-specific makefile.
BTW, CONFIG_HAS_TPL is actually used in the toplevel makefile changes.
> > if you want it squashed into a board-specific patch instead, fine.
> > Just tell us what you want to see.
>
> I already did, but here we go:
No, you made some vague statements of general principle, of which your
interpretation apparently differs from mine. I was hoping for
specifics about this patch set.
> First, please do not add make rules before you have code they apply
> to.
So squash the makefile changes into the board patch?
Which seems to be how nand_spl got added a while back (patch title
"Add support for AMCC Sequoia PPC440EPx eval board"). Maybe the
makefile construct you recently objected to (possibly-empty variable
rule target) would have been more visible if it had been separated out. :-)
What about the division between the mpc85xx portion and the p1021mds
portion?
> After doing this, there is this rudimentary patch to the README.
> From a strictly technical point of view it should be split nto two
> parts: the first one (documenting the existing NAND_SPL variables) is
> independent of the TPL stuff and could be handles separately. The
> second part should be mergeed into the patch that first uses these
> variables. Note that I do not insist on splitting the README changes.
> It's OK with me to keep this together.
Yes, the NAND_SPL bits were lumped in there for convenience, and to
demonstrate the correspondence.
Do you want the README changes to be a separate patch from the
board/makefile changes?
-Scott
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 21:39 ` Haiying Wang
2011-01-31 22:05 ` Kumar Gala
@ 2011-01-31 22:14 ` Wolfgang Denk
1 sibling, 0 replies; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 22:14 UTC (permalink / raw)
To: u-boot
Dear Haiying Wang,
In message <1296509955.2049.543.camel@haiying-laptop> you wrote:
>
> > Why is this config.mk needed? Can you not do all this in the board
> > config file instead?
> Do you mean the board header file or arch/powerpc/config.mk? I did not see any LDSCRIPT defined in Freescale board header file.
I mean the board config header file, include/configs/<name>.h
> > > diff --git a/board/freescale/p1021mds/ddr.c b/board/freescale/p1021mds/ddr.c
> > > new file mode 100644
> > > index 0000000..594a4a8
> > > --- /dev/null
> > > +++ b/board/freescale/p1021mds/ddr.c
> >
> > It seems there are a number of functions here which ar actually shared
> > with other files, for example board/freescale/p1022ds/ddr.c.
> Every boards has its board specific ddr parameters which are defined the its own board ddr.c. The common code for ddr has been defined in arch/powerpc/cpu/mpc8xxx/ddr/.
Well, but there is tons of common code. For example, all of
board/freescale/corenet_ds/ddr.c
board/freescale/mpc8536ds/ddr.c
board/freescale/mpc8540ads/ddr.c
board/freescale/mpc8541cds/ddr.c
board/freescale/mpc8544ds/ddr.c
board/freescale/mpc8548cds/ddr.c
board/freescale/mpc8555cds/ddr.c
board/freescale/mpc8560ads/ddr.c
board/freescale/mpc8568mds/ddr.c
board/freescale/mpc8569mds/ddr.c
board/freescale/mpc8572ds/ddr.c
board/freescale/mpc8610hpcd/ddr.c
board/freescale/mpc8641hpcn/ddr.c
board/freescale/p1021mds/ddr.c
board/freescale/p1022ds/ddr.c
board/freescale/p2020ds/ddr.c
share the same function
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
And
board/freescale/p1021mds/ddr.c
board/freescale/p1022ds/ddr.c
share (except for the comment) the same
void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
while
board/freescale/corenet_ds/ddr.c
board/freescale/mpc8569mds/ddr.c
use another variant, but again both boards the same one.
> If you go to see each ddr.c, you can find there is
> fsl_ddr_board_options() which defines the different values for each
> board. Also fsl_ddr_get_spd() is also highly dependent on board, like
> ddr type(ddr2 or ddr3), i2c spd eeprom address, ddr controller# etc.
Actually this is not quite true. See examples above.
> > > +void board_lmb_reserve(struct lmb *lmb)
> > > +{
> > > + cpu_mp_lmb_reserve(lmb);
> > > +}
> >
> > How many board/freescale/<name>/<name>.c file share this same code?
> There are some, but I don't know whether there will be difference coming in later.
Then we can use a common implementation for all where it fits, and
use board specific code only where needed.
> > > diff --git a/board/freescale/p1021mds/tlb.c b/board/freescale/p1021mds/tlb.c
> > > new file mode 100644
> > > index 0000000..30af6dd
> > > --- /dev/null
> > > +++ b/board/freescale/p1021mds/tlb.c
> >
> > How much of this is actually different from - say -
> > board/freescale/p1022ds/tlb.c ?
> The tlb.c is also a highly board dependent file. Different boards have different supported peripherals. If you look at p1021 and p1022's tlb.c files, you can see p1022ds has 3 PCIE, P1021 has 2, P1022ds has NOR flash, P1021MDS only has NAND flash... etc
Yes, there are differences. But it seems there is more common code
than differing one?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A penny saved is a penny to squander.
- Ambrose Bierce
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
2011-01-31 22:05 ` Kumar Gala
@ 2011-01-31 22:16 ` Wolfgang Denk
0 siblings, 0 replies; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 22:16 UTC (permalink / raw)
To: u-boot
Dear Kumar Gala,
In message <AE2E740C-25BB-48DB-BB6F-A92B91D57938@kernel.crashing.org> you wrote:
>
> >>> +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
> >>> +endif
> >>> +endif
> >>> +endif
> >>
> >> Why is this config.mk needed? Can you not do all this in the board
> >> config file instead?
> > Do you mean the board header file or arch/powerpc/config.mk? I did not
> see any LDSCRIPT defined in Freescale board header file.
>
> I think something like:
>
> diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
> index e6b60cf..f2d6cdb 100644
> --- a/include/configs/MPC8572DS.h
> +++ b/include/configs/MPC8572DS.h
> @@ -37,6 +37,7 @@
> #define CONFIG_NAND_U_BOOT
> #define CONFIG_RAMBOOT_NAND
> #ifdef CONFIG_NAND_SPL
> +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
This will eventually break with out of tree builds.
Rather use
#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There's a way out of any cage.
-- Captain Christopher Pike, "The Menagerie" ("The Cage"),
stardate unknown.
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 22:07 ` Scott Wood
@ 2011-01-31 22:40 ` Wolfgang Denk
2011-01-31 22:55 ` Scott Wood
0 siblings, 1 reply; 46+ messages in thread
From: Wolfgang Denk @ 2011-01-31 22:40 UTC (permalink / raw)
To: u-boot
Dear Scott Wood,
In message <20110131160713.0b78ccf2@udp111988uds.am.freescale.net> you wrote:
>
> Do you want the README changes to be a separate patch from the
> board/makefile changes?
Did you not just explain that this would make no sense?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The Wright Bothers weren't the first to fly. They were just the first
not to crash.
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 22:40 ` Wolfgang Denk
@ 2011-01-31 22:55 ` Scott Wood
0 siblings, 0 replies; 46+ messages in thread
From: Scott Wood @ 2011-01-31 22:55 UTC (permalink / raw)
To: u-boot
On Mon, 31 Jan 2011 23:40:41 +0100
Wolfgang Denk <wd@denx.de> wrote:
> Dear Scott Wood,
>
> In message <20110131160713.0b78ccf2@udp111988uds.am.freescale.net> you wrote:
> >
> > Do you want the README changes to be a separate patch from the
> > board/makefile changes?
>
> Did you not just explain that this would make no sense?
I don't think so, though it makes sense to me that it should go with
the makefile changes.
But I'm trying to figure out precisely what you want done with this
patchset, rather than what makes sense to me.
I'll take that as a "squash it in with the board and makefile changes".
-Scott
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines.
2011-01-31 21:08 ` Kumar Gala
@ 2011-01-31 23:36 ` Timur Tabi
2011-02-01 4:04 ` Kumar Gala
0 siblings, 1 reply; 46+ messages in thread
From: Timur Tabi @ 2011-01-31 23:36 UTC (permalink / raw)
To: u-boot
On Mon, Jan 31, 2011 at 3:08 PM, Kumar Gala <galak@kernel.crashing.org> wrote:
>> @@ -588,6 +588,9 @@ typedef struct qe_immap {
>> #elif defined(CONFIG_MPC8569)
>> ? ? ? u8 muram[0x20000]; ? ? ?/* 0x1_0000 - ?0x3_0000 Multi-user RAM */
>> ? ? ? u8 res17[0x10000]; ? ? ?/* 0x3_0000 - ?0x4_0000 */
>> +#elif defined(CONFIG_P1021)
>> + ? ? u8 muram[0x06000]; ? ? ?/* 0x1_0000 - ?0x1_6000 Multi-user RAM */
>> + ? ? u8 res17[0x1a000]; ? ? ?/* 0x1_6000 - ?0x3_0000 */
>> #else
>> ? ? ? u8 muram[0xC000]; ? ? ? /* 0x110000 - ?0x11C000 Multi-user RAM */
>> ? ? ? u8 res17[0x24000]; ? ? ?/* 0x11C000 - ?0x140000 */
>
> Can we reduce this mess with using QE_MURAM_SIZE?
>
> ? ? ? ?u8 muram[QE_MURAM_SIZE];
> ? ? ? ?u8 res17[0xNNNN - QE_MURAM_SIZE];
I don't think we need res17, because nothing references it. That will
simplify it even more.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-01-31 21:28 ` Kumar Gala
@ 2011-02-01 3:14 ` Haiying Wang
2011-02-01 16:50 ` Scott Wood
0 siblings, 1 reply; 46+ messages in thread
From: Haiying Wang @ 2011-02-01 3:14 UTC (permalink / raw)
To: u-boot
On Mon, 2011-01-31 at 15:28 -0600, Kumar Gala wrote:
> On Jan 31, 2011, at 2:50 PM, Haiying Wang wrote:
>
> > On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote:
> >>>
> >>> +#ifdef CONFIG_P1021
> >>> + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> >>> +
> >>> + /* QE9 and QE12 need to be set for enabling QE MII managment signals */
> >>> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
> >>> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
> >>> +#endif
> >> ...
> >>
> >> Can we please avoid having board specific code in common files?
> > I wish I could, but only P1021 has such pin mux problems.
> >
> >> If this is really necessary, it shoud be a feature-specific #define,
> >> not a board specific one.
> > I don't know whether this *feature* will show up on other SoC. But if
> > you insist, I can use CONFIG_QE_PIN_MUX.
> >
> > Thanks.
> >
> > Haiying
>
> I think pin muxing is a board level decision so it seems like board code is the right place for it.
>
If it is a one time setting, there should be no problem to put it into
board code. But these pin settings need to be done before any usage of
phy read/write (accessing MDIO/MDC), and need to be released after the
usage of phy, thus the devices connected to eLBC like NAND flash/BCSR
can be accessed. If we use board code to set/release the pin, we don't
know when the phy access and nand flash access will happen.
Haiying
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines.
2011-01-31 23:36 ` Timur Tabi
@ 2011-02-01 4:04 ` Kumar Gala
0 siblings, 0 replies; 46+ messages in thread
From: Kumar Gala @ 2011-02-01 4:04 UTC (permalink / raw)
To: u-boot
On Jan 31, 2011, at 5:36 PM, Timur Tabi wrote:
> On Mon, Jan 31, 2011 at 3:08 PM, Kumar Gala <galak@kernel.crashing.org> wrote:
>
>>> @@ -588,6 +588,9 @@ typedef struct qe_immap {
>>> #elif defined(CONFIG_MPC8569)
>>> u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */
>>> u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */
>>> +#elif defined(CONFIG_P1021)
>>> + u8 muram[0x06000]; /* 0x1_0000 - 0x1_6000 Multi-user RAM */
>>> + u8 res17[0x1a000]; /* 0x1_6000 - 0x3_0000 */
>>> #else
>>> u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
>>> u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
>>
>> Can we reduce this mess with using QE_MURAM_SIZE?
>>
>> u8 muram[QE_MURAM_SIZE];
>> u8 res17[0xNNNN - QE_MURAM_SIZE];
>
> I don't think we need res17, because nothing references it. That will
> simplify it even more.
Looks like qe_immap isn't embedded anywhere so should be ok (was concerned if the struct is expected to be a given size.
- k
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
2011-01-31 18:41 [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Haiying.Wang at freescale.com
` (6 preceding siblings ...)
2011-01-31 19:39 ` [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Wolfgang Denk
@ 2011-02-01 5:26 ` Kumar Gala
7 siblings, 0 replies; 46+ messages in thread
From: Kumar Gala @ 2011-02-01 5:26 UTC (permalink / raw)
To: u-boot
I've published some related cleanup patches and push those patches into u-boot-85xx.git 'dev' branch.
You should be able to:
* drop board_lmb_reserve()
* remove config.mk and CONFIG_SYS_LDSCRIPT in config.h
* remove fsl_ddr_get_mem_data_rate(), fsl_ddr_get_spd() [need to rename SPD_EEPROM_ADDRESS1 to SPD_EEPROM_ADDRESS]
* just set P1021 related defines rather than touch immap_qe.h
- k
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-02-01 3:14 ` Haiying Wang
@ 2011-02-01 16:50 ` Scott Wood
2011-02-01 17:01 ` Haiying Wang
0 siblings, 1 reply; 46+ messages in thread
From: Scott Wood @ 2011-02-01 16:50 UTC (permalink / raw)
To: u-boot
On Mon, 31 Jan 2011 22:14:45 -0500
Haiying Wang <Haiying.Wang@freescale.com> wrote:
> On Mon, 2011-01-31 at 15:28 -0600, Kumar Gala wrote:
> > On Jan 31, 2011, at 2:50 PM, Haiying Wang wrote:
> >
> > > On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote:
> > >>>
> > >>> +#ifdef CONFIG_P1021
> > >>> + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > >>> +
> > >>> + /* QE9 and QE12 need to be set for enabling QE MII managment signals */
> > >>> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
> > >>> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
> > >>> +#endif
> > >> ...
> > >>
> > >> Can we please avoid having board specific code in common files?
> > > I wish I could, but only P1021 has such pin mux problems.
> > >
> > >> If this is really necessary, it shoud be a feature-specific #define,
> > >> not a board specific one.
> > > I don't know whether this *feature* will show up on other SoC. But if
> > > you insist, I can use CONFIG_QE_PIN_MUX.
> > >
> > > Thanks.
> > >
> > > Haiying
> >
> > I think pin muxing is a board level decision so it seems like board code is the right place for it.
> >
> If it is a one time setting, there should be no problem to put it into
> board code. But these pin settings need to be done before any usage of
> phy read/write (accessing MDIO/MDC), and need to be released after the
> usage of phy, thus the devices connected to eLBC like NAND flash/BCSR
> can be accessed. If we use board code to set/release the pin, we don't
> know when the phy access and nand flash access will happen.
Is this actually a board issue or an SoC issue?
-Scott
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-02-01 16:50 ` Scott Wood
@ 2011-02-01 17:01 ` Haiying Wang
2011-02-01 19:15 ` Kumar Gala
0 siblings, 1 reply; 46+ messages in thread
From: Haiying Wang @ 2011-02-01 17:01 UTC (permalink / raw)
To: u-boot
On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote:
> > >
> > If it is a one time setting, there should be no problem to put it into
> > board code. But these pin settings need to be done before any usage of
> > phy read/write (accessing MDIO/MDC), and need to be released after the
> > usage of phy, thus the devices connected to eLBC like NAND flash/BCSR
> > can be accessed. If we use board code to set/release the pin, we don't
> > know when the phy access and nand flash access will happen.
>
> Is this actually a board issue or an SoC issue?
>
It is not a board issue. It is a SoC *feature*. Too many pins are muxed
on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20]
which is used for MDIO signal.
Haiying
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-02-01 17:01 ` Haiying Wang
@ 2011-02-01 19:15 ` Kumar Gala
2011-02-01 19:46 ` Haiying Wang
0 siblings, 1 reply; 46+ messages in thread
From: Kumar Gala @ 2011-02-01 19:15 UTC (permalink / raw)
To: u-boot
On Feb 1, 2011, at 11:01 AM, Haiying Wang wrote:
> On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote:
>>>>
>>> If it is a one time setting, there should be no problem to put it into
>>> board code. But these pin settings need to be done before any usage of
>>> phy read/write (accessing MDIO/MDC), and need to be released after the
>>> usage of phy, thus the devices connected to eLBC like NAND flash/BCSR
>>> can be accessed. If we use board code to set/release the pin, we don't
>>> know when the phy access and nand flash access will happen.
>>
>> Is this actually a board issue or an SoC issue?
>>
> It is not a board issue. It is a SoC *feature*. Too many pins are muxed
> on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20]
> which is used for MDIO signal.
>
> Haiying
>
But its a board decision on how they want to utilize those pins and for what feature.
- k
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-02-01 19:15 ` Kumar Gala
@ 2011-02-01 19:46 ` Haiying Wang
2011-02-02 4:25 ` Kumar Gala
0 siblings, 1 reply; 46+ messages in thread
From: Haiying Wang @ 2011-02-01 19:46 UTC (permalink / raw)
To: u-boot
On Tue, 2011-02-01 at 13:15 -0600, Kumar Gala wrote:
> On Feb 1, 2011, at 11:01 AM, Haiying Wang wrote:
>
> > On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote:
> >>>>
> >>> If it is a one time setting, there should be no problem to put it into
> >>> board code. But these pin settings need to be done before any usage of
> >>> phy read/write (accessing MDIO/MDC), and need to be released after the
> >>> usage of phy, thus the devices connected to eLBC like NAND flash/BCSR
> >>> can be accessed. If we use board code to set/release the pin, we don't
> >>> know when the phy access and nand flash access will happen.
> >>
> >> Is this actually a board issue or an SoC issue?
> >>
> > It is not a board issue. It is a SoC *feature*. Too many pins are muxed
> > on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20]
> > which is used for MDIO signal.
> >
> > Haiying
> >
>
> But its a board decision on how they want to utilize those pins and for what feature.
Yes, you can say that. If the board doesn't have QE UCC ETH support at
all, we won't have to add such code in QE driver. But if there is QE UCC
ETH on board, we have no choice to decide which pins to use. We
definitely need to use CE_PB[20] for MDIO signal, there is no other GPIO
pins to use for QE's MDIO.
Haiying
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
2011-02-01 19:46 ` Haiying Wang
@ 2011-02-02 4:25 ` Kumar Gala
0 siblings, 0 replies; 46+ messages in thread
From: Kumar Gala @ 2011-02-02 4:25 UTC (permalink / raw)
To: u-boot
On Feb 1, 2011, at 1:46 PM, Haiying Wang wrote:
> On Tue, 2011-02-01 at 13:15 -0600, Kumar Gala wrote:
>> On Feb 1, 2011, at 11:01 AM, Haiying Wang wrote:
>>
>>> On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote:
>>>>>>
>>>>> If it is a one time setting, there should be no problem to put it into
>>>>> board code. But these pin settings need to be done before any usage of
>>>>> phy read/write (accessing MDIO/MDC), and need to be released after the
>>>>> usage of phy, thus the devices connected to eLBC like NAND flash/BCSR
>>>>> can be accessed. If we use board code to set/release the pin, we don't
>>>>> know when the phy access and nand flash access will happen.
>>>>
>>>> Is this actually a board issue or an SoC issue?
>>>>
>>> It is not a board issue. It is a SoC *feature*. Too many pins are muxed
>>> on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20]
>>> which is used for MDIO signal.
>>>
>>> Haiying
>>>
>>
>> But its a board decision on how they want to utilize those pins and for what feature.
>
> Yes, you can say that. If the board doesn't have QE UCC ETH support at
> all, we won't have to add such code in QE driver. But if there is QE UCC
> ETH on board, we have no choice to decide which pins to use. We
> definitely need to use CE_PB[20] for MDIO signal, there is no other GPIO
> pins to use for QE's MDIO.
>
> Haiying
If that case and controlled by some CONFIG_QE_* define than we clearly can make the choice in non-board specific code.
- k
^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
2011-01-31 21:37 ` Wolfgang Denk
@ 2011-02-02 4:29 ` Kumar Gala
0 siblings, 0 replies; 46+ messages in thread
From: Kumar Gala @ 2011-02-02 4:29 UTC (permalink / raw)
To: u-boot
On Jan 31, 2011, at 3:37 PM, Wolfgang Denk wrote:
> Dear Haiying Wang,
>
> In message <1296507737.2049.518.camel@haiying-laptop> you wrote:
>> On Mon, 2011-01-31 at 21:08 +0100, Wolfgang Denk wrote:
>>> Dear Haiying.Wang at freescale.com,
>>>
>>> In message <1296499317-26616-6-git-send-email-Haiying.Wang@freescale.com> you wrote:
>>>> From: Haiying Wang <Haiying.Wang@freescale.com>
>>>>
>>>> For some board which doesn't have NOR flash and the QE's firmware(ucode) is
>>>> saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will
>>>> call it later after nand is initialized.
>>>
>>> Is there a pressing reason to do this so early for other boards? Can
>>> not all boards initialize this later?
>>>
>> My understanding is that QE is a cpu feature, so it is called early in
>> cpu_init_r. As Kumar recommended before, I can move qe_init from
>> cpu_init_r to misc_init_r for every 85xx boards with qe support. Is it
>> acceptable to you?
>
> Yes, if this way we can avoid to do the same thing at different
> points in the initialization sequence.
Doing this in misc_init_r() isn't right either.
We've had this argument before, can we just add a cpu_init_late_r() that is post env_relocate() ?
Why should we duplicate cpu generic code in board code?
- k
^ permalink raw reply [flat|nested] 46+ messages in thread
end of thread, other threads:[~2011-02-02 4:29 UTC | newest]
Thread overview: 46+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-01-31 18:41 [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Haiying.Wang at freescale.com
2011-01-31 18:41 ` [U-Boot] [PATCH 1/6] Introduce the Tertiary Program loader Haiying.Wang at freescale.com
2011-01-31 18:41 ` [U-Boot] [PATCH 2/6] powerpc/85xx: add TPL support Haiying.Wang at freescale.com
2011-01-31 18:41 ` [U-Boot] [PATCH 3/6] P1021: add P1021MDS board support Haiying.Wang at freescale.com
2011-01-31 20:03 ` Wolfgang Denk
2011-01-31 20:08 ` Scott Wood
2011-01-31 20:18 ` Wolfgang Denk
2011-01-31 20:23 ` Scott Wood
2011-01-31 21:39 ` Haiying Wang
2011-01-31 22:05 ` Kumar Gala
2011-01-31 22:16 ` Wolfgang Denk
2011-01-31 22:14 ` Wolfgang Denk
2011-01-31 21:40 ` Kumar Gala
2011-01-31 18:41 ` [U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines Haiying.Wang at freescale.com
2011-01-31 20:07 ` Wolfgang Denk
2011-01-31 21:08 ` Kumar Gala
2011-01-31 23:36 ` Timur Tabi
2011-02-01 4:04 ` Kumar Gala
2011-01-31 18:41 ` [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash Haiying.Wang at freescale.com
2011-01-31 20:08 ` Wolfgang Denk
2011-01-31 21:02 ` Haiying Wang
2011-01-31 21:37 ` Wolfgang Denk
2011-02-02 4:29 ` Kumar Gala
2011-01-31 18:41 ` [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support Haiying.Wang at freescale.com
2011-01-31 20:11 ` Wolfgang Denk
2011-01-31 20:50 ` Haiying Wang
2011-01-31 21:28 ` Kumar Gala
2011-02-01 3:14 ` Haiying Wang
2011-02-01 16:50 ` Scott Wood
2011-02-01 17:01 ` Haiying Wang
2011-02-01 19:15 ` Kumar Gala
2011-02-01 19:46 ` Haiying Wang
2011-02-02 4:25 ` Kumar Gala
2011-01-31 19:39 ` [U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board Wolfgang Denk
2011-01-31 20:13 ` Scott Wood
2011-01-31 20:22 ` Wolfgang Denk
2011-01-31 20:31 ` Scott Wood
2011-01-31 20:39 ` Kumar Gala
2011-01-31 20:50 ` Wolfgang Denk
2011-01-31 20:50 ` Wolfgang Denk
2011-01-31 21:15 ` Scott Wood
2011-01-31 21:34 ` Wolfgang Denk
2011-01-31 22:07 ` Scott Wood
2011-01-31 22:40 ` Wolfgang Denk
2011-01-31 22:55 ` Scott Wood
2011-02-01 5:26 ` Kumar Gala
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