From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: =?utf-8?q?_=5BPATCH_1/8=5D_drm/i915/context=3A_basic_?= =?utf-8?q?implementation_context_ioctls?= Date: Wed, 2 Feb 2011 15:00:13 -0800 Message-ID: <1296687620-27019-2-git-send-email-bwidawsk@gmail.com> References: <1296687620-27019-1-git-send-email-bwidawsk@gmail.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0389455060==" Return-path: Received: from mail-yx0-f177.google.com (mail-yx0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 03FE89E9C3 for ; Wed, 2 Feb 2011 15:00:38 -0800 (PST) Received: by yxd30 with SMTP id 30so242900yxd.36 for ; Wed, 02 Feb 2011 15:00:38 -0800 (PST) In-Reply-To: <1296687620-27019-1-git-send-email-bwidawsk@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0389455060== Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Added the minimal amount of code to enable the two ioctls used for creating and destroying contexts. Also added neccessary information in the structures to implement some basic operations the ioctls will have to perform. A small whitespace fixup in the Makefile also made it in here. --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_context.c | 113 +++++++++++++++++++++++++++++= ++++++ drivers/gpu/drm/i915/i915_dma.c | 2 + drivers/gpu/drm/i915/i915_drv.h | 34 +++++++++++ include/drm/i915_drm.h | 15 +++++ 5 files changed, 166 insertions(+), 1 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_context.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefil= e index 0ae6a7c..244536a 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -5,13 +5,14 @@ ccflags-y :=3D -Iinclude/drm i915-y :=3D i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ i915_debugfs.o \ - i915_suspend.o \ + i915_suspend.o \ i915_gem.o \ i915_gem_debug.o \ i915_gem_evict.o \ i915_gem_execbuffer.o \ i915_gem_gtt.o \ i915_gem_tiling.o \ + i915_context.o \ i915_trace_points.o \ intel_display.o \ intel_crt.o \ diff --git a/drivers/gpu/drm/i915/i915_context.c b/drivers/gpu/drm/i915/i= 915_context.c new file mode 100644 index 0000000..0d140b8 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_context.c @@ -0,0 +1,113 @@ +/* + * Copyright =A9 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining= a + * copy of this software and associated documentation files (the "Softwa= re"), + * to deal in the Software without restriction, including without limita= tion + * the rights to use, copy, modify, merge, publish, distribute, sublicen= se, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the = next + * paragraph) shall be included in all copies or substantial portions of= the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRE= SS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILI= TY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SH= ALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR = OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISI= NG + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER D= EALINGS + * IN THE SOFTWARE. + * + * Authors: + * + */ + +#include "drmP.h" +#include "drm.h" +#include "i915_drm.h" +#include "intel_drv.h" + +static struct drm_i915_gem_context * +i915_gem_lookup_ctx_id(struct drm_device *dev, + uint32_t id) +{ + struct drm_i915_private *dev_priv =3D dev->dev_private; + return idr_find(&dev_priv->i915_ctx_idr, id); +} + +static void +i915_gem_del_ctx_id(struct drm_device *dev, + struct drm_i915_gem_context *ctx) +{ + struct drm_i915_private *dev_priv =3D dev->dev_private; + idr_remove(&dev_priv->i915_ctx_idr, ctx->ctx_id); +} + +int +i915_gem_alloc_hw_context(struct drm_device *dev, + uint64_t aperture_size, + struct drm_i915_gem_context **ctx_out) +{ + return -ENOMEM; +} + +int +i915_gem_ctx_create_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_i915_gem_ctx_create *args =3D data; + struct drm_i915_gem_context *ctx =3D NULL; + struct drm_i915_file_private *file_priv =3D file->driver_priv; + int slots =3D args->slot_count; + int i, ret =3D 0; + + /* TODO: sanitize aperture_size*/ + ret =3D i915_gem_alloc_hw_context(dev, args->aperture_size, &ctx); + if (ret) { + goto out; + } + + ctx->bufs =3D drm_malloc_ab(slots + 1, sizeof(struct drm_gem_object*)); + if (ctx->bufs =3D=3D NULL) { + kfree(ctx); + drm_free_large(ctx->bufs); + ret =3D -ENOMEM; + goto out; + } + ctx->slot_count =3D slots; + for(i =3D 0; i < slots + 1; i++) { + ctx->bufs[i] =3D NULL; + } + + list_add(&ctx->file_list, &file_priv->context.context_list); + + args->ctx_id =3D ctx->ctx_id; +out: + return ret; +} + +int +i915_gem_ctx_destroy_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_i915_gem_ctx_destroy *args =3D data; + struct drm_i915_gem_context *ctx, *ctx_temp; + struct list_head *pos, *n; + struct drm_i915_file_private *file_priv =3D file->driver_priv; + + ctx =3D i915_gem_lookup_ctx_id(dev, args->ctx_id); + if (ctx =3D=3D NULL) { + return -EINVAL; + } + + list_for_each_safe(pos, n, &file_priv->context.context_list) { + ctx_temp =3D list_entry(pos, struct drm_i915_gem_context, context_list= ); + } + i915_gem_del_ctx_id(dev, ctx); + kfree(ctx); + + /* TODO: ring switch may be needed */ + return 0; +} diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_= dma.c index 17bd766..91f062e 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -2249,6 +2249,8 @@ struct drm_ioctl_desc i915_ioctls[] =3D { DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKE= D), DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_= MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|D= RM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(I915_GEM_CTX_CREATE, i915_gem_ctx_create_ioctl, DRM_U= NLOCKED), + DRM_IOCTL_DEF_DRV(I915_GEM_CTX_DESTROY, i915_gem_ctx_destroy_ioctl, DRM= _UNLOCKED), }; =20 int i915_max_ioctl =3D DRM_ARRAY_SIZE(i915_ioctls); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h index a0149c6..28affdd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -280,6 +280,13 @@ typedef struct drm_i915_private { struct drm_i915_gem_object *pwrctx; struct drm_i915_gem_object *renderctx; =20 + /** Device specific context info */ + uint32_t ctx_size; + struct drm_i915_gem_context *default_ctx; + struct spinlock i915_ctx_lock; + struct idr i915_ctx_idr; + bool ctx_disable; + struct resource mch_res; =20 unsigned int cpp; @@ -848,6 +855,25 @@ struct drm_i915_gem_object { =20 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) =20 +struct drm_i915_gem_context { + int ctx_id; + /** Pinned buffer for the HW context */ + struct drm_gem_object *ctx_obj; + uint32_t aperture_size_mb; + + /** TODO: rw lock? */ + struct mutex slot_mtx; + struct drm_gem_object **bufs; + int slot_count; + + /** This object's place on the per bo context list */ + struct list_head context_list; + + /** This object's place no the per file context list */ + struct list_head file_list; +}; + + /** * Request queue structure. * @@ -881,6 +907,10 @@ struct drm_i915_file_private { struct spinlock lock; struct list_head request_list; } mm; + struct { + struct mutex mtx; + struct list_head context_list; + } context; }; =20 enum intel_chip_family { @@ -1090,6 +1120,10 @@ int i915_gem_get_tiling(struct drm_device *dev, vo= id *data, struct drm_file *file_priv); int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); +int i915_gem_ctx_create_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); +int i915_gem_ctx_destroy_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); void i915_gem_load(struct drm_device *dev); int i915_gem_init_object(struct drm_gem_object *obj); int __must_check i915_gem_flush_ring(struct drm_device *dev, diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 0039f1f..692de60 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -198,6 +198,8 @@ typedef struct _drm_i915_sarea { #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 #define DRM_I915_OVERLAY_ATTRS 0x28 #define DRM_I915_GEM_EXECBUFFER2 0x29 +#define DRM_I915_GEM_CTX_CREATE 0x2a +#define DRM_I915_GEM_CTX_DESTROY 0x2b =20 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, = drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH= ) @@ -239,6 +241,9 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_= GEM_MADVISE, struct drm_i915_gem_madvise) #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_= IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image) #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I91= 5_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) +#define DRM_IOCTL_I915_GEM_CTX_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I= 915_GEM_CTX_CREATE, struct drm_i915_gem_ctx_create) +#define DRM_IOCTL_I915_GEM_CTX_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I= 915_GEM_CTX_DESTROY, struct drm_i915_gem_ctx_destroy) + =20 /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -843,4 +848,14 @@ struct drm_intel_overlay_attrs { __u32 gamma5; }; =20 +struct drm_i915_gem_ctx_create { + __s32 slot_count; + __u64 aperture_size; + __u32 ctx_id; +}; + +struct drm_i915_gem_ctx_destroy { + __u32 ctx_id; +}; + #endif /* _I915_DRM_H_ */ --=20 1.7.3.4 --===============0389455060== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0389455060==--