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Subject: Re: [PATCH] perf events, x86: Implement Sandybridge last-level
 cache events
From: Lin Ming <ming.m.lin@intel.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
        linux-kernel <linux-kernel@vger.kernel.org>,
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        Arnaldo Carvalho de Melo <acme@redhat.com>,
        =?ISO-8859-1?Q?Fr=E9d=E9ric?= Weisbecker <fweisbec@gmail.com>,
        Steven Rostedt <rostedt@goodmis.org>
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Date: Mon, 09 May 2011 16:45:11 +0800
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On Fri, 2011-05-06 at 21:47 +0800, Lin Ming wrote:
> On Fri, 2011-05-06 at 17:19 +0800, Ingo Molnar wrote:
> > Btw., there's another missing Intel SandyBridge related perf events feature as 
> > well which was not implemented with the Intel offcore bits.
> > 
> > Peter did a raw first cut - entirely untested, see it below. Would you be 
> > interested in testing it on Intel SandyBridge hw and sending (the working 
> > version) to lkml with your Signed-off-by if the events looks good to you in 
> > some real tests (i.e. are counting real LL cache events)?
> 
> OK, but I can't access SandyBridge machine at home now.
> Will try it next Monday.

The updated and tested patch at:
http://lkml.org/lkml/2011/5/9/80

Please help to review the definitions for SNB_L3_HIT/_MISS_/ACCESS.
I'm really unsure for that.

Thanks,
Lin Ming

> 
> > 
> > Thanks,
> > 
> > 	Ingo
>