From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:50658) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSpv-0006gi-Sq for qemu-devel@nongnu.org; Tue, 17 May 2011 18:33:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QMSpu-0000RD-Kq for qemu-devel@nongnu.org; Tue, 17 May 2011 18:33:55 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:53774) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSpu-0000MT-DP for qemu-devel@nongnu.org; Tue, 17 May 2011 18:33:54 -0400 Received: by mail-ey0-f173.google.com with SMTP id 6so338540eyb.4 for ; Tue, 17 May 2011 15:33:54 -0700 (PDT) From: Max Filippov Date: Wed, 18 May 2011 02:32:39 +0400 Message-Id: <1305671572-5899-14-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> References: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 13/26] target-xtensa: mark reserved and TBD opcodes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov Reserved opcodes must generate illegal instruction exception. Usually they signal emulation quality problems. Not implemented opcodes are good to see. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 110 ++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 109 insertions(+), 1 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index a2a1e78..6a45bb0 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -258,6 +258,14 @@ static void disas_xtensa_insn(DisasContext *dc) } \ } while (0) +#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__) +#define RESERVED() do { \ + qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \ + dc->pc, _b0, _b1, _b2, __FILE__, __LINE__); \ + goto invalid_opcode; \ + } while (0) + + #ifdef TARGET_WORDS_BIGENDIAN #define _OP0 (((_b0) & 0xf0) >> 4) #define _OP1 (((_b2) & 0xf0) >> 4) @@ -358,9 +366,11 @@ static void disas_xtensa_insn(DisasContext *dc) case 0: /*SNM0*/ switch (CALLX_M) { case 0: /*ILL*/ + TBD(); break; case 1: /*reserved*/ + RESERVED(); break; case 2: /*JR*/ @@ -372,9 +382,11 @@ static void disas_xtensa_insn(DisasContext *dc) case 1: /*RETWw*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 3: /*reserved*/ + RESERVED(); break; } break; @@ -395,6 +407,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 2: /*CALLX8w*/ case 3: /*CALLX12w*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; } break; @@ -403,12 +416,59 @@ static void disas_xtensa_insn(DisasContext *dc) case 1: /*MOVSPw*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 2: /*SYNC*/ + TBD(); + break; + + case 3: /*RFEIx*/ + TBD(); + break; + + case 4: /*BREAKx*/ + HAS_OPTION(XTENSA_OPTION_EXCEPTION); + TBD(); + break; + + case 5: /*SYSCALLx*/ + HAS_OPTION(XTENSA_OPTION_EXCEPTION); + TBD(); + break; + + case 6: /*RSILx*/ + HAS_OPTION(XTENSA_OPTION_INTERRUPT); + TBD(); + break; + + case 7: /*WAITIx*/ + HAS_OPTION(XTENSA_OPTION_INTERRUPT); + TBD(); + break; + + case 8: /*ANY4p*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); + break; + + case 9: /*ALL4p*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; - case 3: + case 10: /*ANY8p*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); + break; + + case 11: /*ALL8p*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); + break; + + default: /*reserved*/ + RESERVED(); break; } @@ -464,13 +524,16 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 6: /*RER*/ + TBD(); break; case 7: /*WER*/ + TBD(); break; case 8: /*ROTWw*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 14: /*NSAu*/ @@ -484,11 +547,13 @@ static void disas_xtensa_insn(DisasContext *dc) break; default: /*reserved*/ + RESERVED(); break; } break; case 5: /*TLB*/ + TBD(); break; case 6: /*RT0*/ @@ -509,11 +574,13 @@ static void disas_xtensa_insn(DisasContext *dc) break; default: /*reserved*/ + RESERVED(); break; } break; case 7: /*reserved*/ + RESERVED(); break; case 8: /*ADD*/ @@ -573,6 +640,9 @@ static void disas_xtensa_insn(DisasContext *dc) gen_rsr(dc, cpu_R[RRR_T], RSR_SR); gen_wsr(dc, RSR_SR, tmp); tcg_temp_free(tmp); + if (!sregnames[RSR_SR]) { + TBD(); + } } break; @@ -662,21 +732,29 @@ static void disas_xtensa_insn(DisasContext *dc) break; default: /*reserved*/ + RESERVED(); break; } break; case 2: /*RST2*/ + TBD(); break; case 3: /*RST3*/ switch (_OP2) { case 0: /*RSR*/ gen_rsr(dc, cpu_R[RRR_T], RSR_SR); + if (!sregnames[RSR_SR]) { + TBD(); + } break; case 1: /*WSR*/ gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); + if (!sregnames[RSR_SR]) { + TBD(); + } break; case 2: /*SEXTu*/ @@ -769,10 +847,12 @@ static void disas_xtensa_insn(DisasContext *dc) case 12: /*MOVFp*/ HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; case 13: /*MOVTp*/ HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; case 14: /*RUR*/ @@ -782,6 +862,7 @@ static void disas_xtensa_insn(DisasContext *dc) tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); } else { qemu_log("RUR %d not implemented, ", st); + TBD(); } } break; @@ -792,6 +873,7 @@ static void disas_xtensa_insn(DisasContext *dc) tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]); } else { qemu_log("WUR %d not implemented, ", RSR_SR); + TBD(); } } break; @@ -813,27 +895,34 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 6: /*CUST0*/ + RESERVED(); break; case 7: /*CUST1*/ + RESERVED(); break; case 8: /*LSCXp*/ HAS_OPTION(XTENSA_OPTION_COPROCESSOR); + TBD(); break; case 9: /*LSC4*/ + TBD(); break; case 10: /*FP0*/ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); + TBD(); break; case 11: /*FP1*/ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); + TBD(); break; default: /*reserved*/ + RESERVED(); break; } break; @@ -885,6 +974,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 7: /*CACHEc*/ + TBD(); break; case 9: /*L16SI*/ @@ -936,6 +1026,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; default: /*reserved*/ + RESERVED(); break; } break; @@ -943,10 +1034,12 @@ static void disas_xtensa_insn(DisasContext *dc) case 3: /*LSCIp*/ HAS_OPTION(XTENSA_OPTION_COPROCESSOR); + TBD(); break; case 4: /*MAC16d*/ HAS_OPTION(XTENSA_OPTION_MAC16); + TBD(); break; case 5: /*CALLN*/ @@ -960,6 +1053,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 2: /*CALL8w*/ case 3: /*CALL12w*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; } break; @@ -1002,28 +1096,35 @@ static void disas_xtensa_insn(DisasContext *dc) switch (BRI8_M) { case 0: /*ENTRYw*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 1: /*B1*/ switch (BRI8_R) { case 0: /*BFp*/ HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; case 1: /*BTp*/ HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; case 8: /*LOOP*/ + TBD(); break; case 9: /*LOOPNEZ*/ + TBD(); break; case 10: /*LOOPGTZ*/ + TBD(); break; default: /*reserved*/ + RESERVED(); break; } @@ -1159,28 +1260,35 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 1: /*RETW.Nn*/ + HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 2: /*BREAK.Nn*/ + TBD(); break; case 3: /*NOP.Nn*/ break; case 6: /*ILL.Nn*/ + TBD(); break; default: /*reserved*/ + RESERVED(); break; } break; default: /*reserved*/ + RESERVED(); break; } break; default: /*reserved*/ + RESERVED(); break; } -- 1.7.3.4