From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Fri, 27 May 2011 07:25:48 +0800 Subject: [U-Boot] [PATCH 2/7] powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram width In-Reply-To: <1306452353-11611-1-git-send-email-yorksun@freescale.com> References: <1306452353-11611-1-git-send-email-yorksun@freescale.com> Message-ID: <1306452353-11611-2-git-send-email-yorksun@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: york If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 24 ++++++++++++++++++++---- 1 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 6ccc3b0..80c7046 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -418,8 +418,19 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Choose dynamic power management mode. */ popts->dynamic_power = 0; - /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ - popts->data_bus_width = 0; + /* + * check first dimm for primary sdram width + * presuming all dimms are similar + * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit + */ + if (pdimm[0].primary_sdram_width == 64) + popts->data_bus_width = 0; + else if (pdimm[0].primary_sdram_width == 32) + popts->data_bus_width = 1; + else if (pdimm[0].primary_sdram_width == 16) + popts->data_bus_width = 2; + else + panic("Error: invalid primary sdram width!\n"); /* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) @@ -427,8 +438,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ #else - popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ - popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ + if (popts->data_bus_width == 1) { /* 32-bit bus */ + popts->OTF_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + } else { + popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ + popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ + } #endif #else popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ -- 1.7.0.4