From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:58671) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QTcZo-0002cz-Vc for qemu-devel@nongnu.org; Mon, 06 Jun 2011 12:22:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QTcZg-00037Q-R6 for qemu-devel@nongnu.org; Mon, 06 Jun 2011 12:22:51 -0400 Received: from fmmailgate03.web.de ([217.72.192.234]:41165) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QTcZf-00036n-Ku for qemu-devel@nongnu.org; Mon, 06 Jun 2011 12:22:44 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 6 Jun 2011 18:20:59 +0200 Message-Id: <1307377259-41434-11-git-send-email-andreas.faerber@web.de> In-Reply-To: <1307377259-41434-10-git-send-email-andreas.faerber@web.de> References: <1307377259-41434-1-git-send-email-andreas.faerber@web.de> <1307377259-41434-2-git-send-email-andreas.faerber@web.de> <1307377259-41434-3-git-send-email-andreas.faerber@web.de> <1307377259-41434-4-git-send-email-andreas.faerber@web.de> <1307377259-41434-5-git-send-email-andreas.faerber@web.de> <1307377259-41434-6-git-send-email-andreas.faerber@web.de> <1307377259-41434-7-git-send-email-andreas.faerber@web.de> <1307377259-41434-8-git-send-email-andreas.faerber@web.de> <1307377259-41434-9-git-send-email-andreas.faerber@web.de> <1307377259-41434-10-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: andreas.faerber@web.de Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC 10/10] prep: Add pc87312 Super I/O emulation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , hpoussin@reactos.org, kraxel@redhat.com Signed-off-by: Herv=C3=A9 Poussineau Avoid unplugging ISA devices (not hotpluggable). Signed-off-by: Andreas F=C3=A4rber --- Makefile.objs | 1 + default-configs/ppc-softmmu.mak | 2 + hw/pc87312.c | 435 +++++++++++++++++++++++++++++++++= ++++++ 3 files changed, 438 insertions(+), 0 deletions(-) create mode 100644 hw/pc87312.c diff --git a/Makefile.objs b/Makefile.objs index 90838f6..4729063 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -206,6 +206,7 @@ hw-obj-$(CONFIG_SMARTCARD_NSS) +=3D ccid-card-emulate= d.o # PPC devices hw-obj-$(CONFIG_OPENPIC) +=3D openpic.o hw-obj-$(CONFIG_PREP_PCI) +=3D prep_pci.o +hw-obj-$(CONFIG_PC87312) +=3D pc87312.o # Mac shared devices hw-obj-$(CONFIG_MACIO) +=3D macio.o hw-obj-$(CONFIG_CUDA) +=3D cuda.o diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmm= u.mak index 4563742..4b3ebec 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -7,12 +7,14 @@ CONFIG_ESCC=3Dy CONFIG_M48T59=3Dy CONFIG_VGA_PCI=3Dy CONFIG_SERIAL=3Dy +CONFIG_PARALLEL=3Dy CONFIG_I8254=3Dy CONFIG_PCKBD=3Dy CONFIG_FDC=3Dy CONFIG_DMA=3Dy CONFIG_OPENPIC=3Dy CONFIG_PREP_PCI=3Dy +CONFIG_PC87312=3Dy CONFIG_MACIO=3Dy CONFIG_CUDA=3Dy CONFIG_ADB=3Dy diff --git a/hw/pc87312.c b/hw/pc87312.c new file mode 100644 index 0000000..5147619 --- /dev/null +++ b/hw/pc87312.c @@ -0,0 +1,435 @@ +/* + * QEMU National Semiconductor PC87312 (Super I/O) + * + * Copyright (c) 2010 Herve Poussineau + * + * Permission is hereby granted, free of charge, to any person obtaining= a copy + * of this software and associated documentation files (the "Software"),= to deal + * in the Software without restriction, including without limitation the= rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or = sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be includ= ed in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRE= SS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILI= TY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHA= LL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR = OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISI= NG FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALING= S IN + * THE SOFTWARE. + */ + +#include "isa.h" +#include "fdc.h" +#include "ide.h" + +//#define DEBUG_PC87312 + +#ifdef DEBUG_PC87312 +#define DPRINTF(fmt, ...) \ +do { fprintf(stderr, "pc87312: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) \ +do {} while (0) +#endif + +#define BADF(fmt, ...) \ +do { fprintf(stderr, "pc87312 ERROR: " fmt , ## __VA_ARGS__); } while (0= ) + +#define REG_FER 0 +#define REG_FAR 1 +#define REG_PTR 2 + +#define FER regs[REG_FER] +#define FAR regs[REG_FAR] +#define PTR regs[REG_PTR] + +#define FER_PARALLEL_EN 0x01 +#define FER_UART1_EN 0x02 +#define FER_UART2_EN 0x04 +#define FER_FDC_EN 0x08 +#define FER_FDC_4 0x10 +#define FER_FDC_ADDR 0x20 +#define FER_IDE_EN 0x40 +#define FER_IDE_ADDR 0x80 + +#define FAR_PARALLEL_ADDR 0x03 +#define FAR_UART1_ADDR 0x0C +#define FAR_UART2_ADDR 0x30 +#define FAR_UART_3_4 0xC0 + +#define PTR_POWER_DOWN 0x01 +#define PTR_CLOCK_DOWN 0x02 +#define PTR_PWDN 0x04 +#define PTR_IRQ_5_7 0x08 +#define PTR_UART1_TEST 0x10 +#define PTR_UART2_TEST 0x20 +#define PTR_LOCK_CONF 0x40 +#define PTR_EPP_MODE 0x80 + +typedef struct PC87312State { + uint8_t config; /* initial configuration */ + + struct { + DeviceState *dev; + CharDriverState *chr; + } parallel; + + struct { + DeviceState *dev; + CharDriverState *chr; + } uart[2]; + + struct { + DeviceState *dev; + BlockDriverState *drive[2]; + uint32_t base; + } fdc; + + struct { + DeviceState *dev; + uint32_t base; + } ide; + + uint8_t read_id_step; + uint8_t selected_index; + + uint8_t regs[3]; +} PC87312State; + +static inline bool is_parallel_enabled(PC87312State *s) +{ + return s->FER & FER_PARALLEL_EN; +} + +static inline uint32_t get_parallel_iobase(PC87312State *s) +{ + static const uint32_t parallel_base[] =3D { 0x378, 0x3bc, 0x278, 0x0= 0 }; + + return parallel_base[s->FAR & FAR_PARALLEL_ADDR]; +} + +static inline uint32_t get_parallel_irq(PC87312State *s) +{ + static const uint32_t parallel_irq[] =3D { 5, 7, 5, 0 }; + + int idx; + idx =3D (s->FAR & FAR_PARALLEL_ADDR); + if (idx =3D=3D 0) { + return (s->PTR & PTR_IRQ_5_7) ? 7 : 5; + } else { + return parallel_irq[idx]; + } +} + +static inline bool is_parallel_epp(PC87312State *s) +{ + return (s->PTR & PTR_EPP_MODE); +} + +/* Parallel port */ +static void update_parallel(PC87312State *s) +{ + ISADevice *isa; + + if (s->parallel.dev =3D=3D NULL) { + if (is_parallel_enabled(s) && s->parallel.chr !=3D NULL) { + isa =3D isa_create("isa-parallel"); + qdev_prop_set_uint32(&isa->qdev, "index", 0); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_parallel_ioba= se(s)); + qdev_prop_set_uint32(&isa->qdev, "irq", get_parallel_irq(s))= ; + qdev_prop_set_chr(&isa->qdev, "chardev", s->parallel.chr); + qdev_init_nofail(&isa->qdev); + s->parallel.dev =3D &isa->qdev; + } + } else { + isa =3D DO_UPCAST(ISADevice, qdev, s->parallel.dev); + parallel_isa_reconfigure_iobase(isa, get_parallel_iobase(s)); + parallel_isa_reconfigure_irq(isa, get_parallel_irq(s)); + if (!is_parallel_enabled(s)) { + /* TODO can't deactivate qdev */ + } + } +} + +static const uint32_t uart_base[2][4] =3D { + { 0x3e8, 0x338, 0x2e8, 0x220 }, + { 0x2e8, 0x238, 0x2e0, 0x228 } +}; + +static inline uint32_t get_uart_iobase(PC87312State *s, int i) +{ + int idx; + idx =3D (s->FAR >> (2 * i + 2)) & 0x3; + if (idx =3D=3D 0) { + return 0x3f8; + } else if (idx =3D=3D 1) { + return 0x2f8; + } else { + return uart_base[idx & 1][(s->FAR & FAR_UART_3_4) >> 6]; + } +} + +static inline uint32_t get_uart_irq(PC87312State *s, int i) +{ + int idx; + idx =3D (s->FAR >> (2 * i + 2)) & 0x3; + return (idx & 1) ? 3 : 4; +} + +static inline bool is_uart_enabled(PC87312State *s, int i) +{ + return s->FER & (FER_UART1_EN << i); +} + +/* UARTs */ +static void update_uarts(PC87312State *s) +{ + ISADevice *isa; + int i; + + for (i =3D 0; i < 2; i++) { + if (s->uart[i].dev =3D=3D NULL) { + if (is_uart_enabled(s, i) && s->uart[i].chr !=3D NULL) { + isa =3D isa_create("isa-serial"); + qdev_prop_set_uint32(&isa->qdev, "index", i); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_uart_ioba= se(s, i)); + qdev_prop_set_uint32(&isa->qdev, "irq", get_uart_irq(s, = i)); + qdev_prop_set_chr(&isa->qdev, "chardev", s->uart[i].chr)= ; + qdev_init_nofail(&isa->qdev); + s->uart[i].dev =3D &isa->qdev; + } + } else { + isa =3D DO_UPCAST(ISADevice, qdev, s->parallel.dev); + serial_isa_reconfigure_iobase(isa, get_uart_iobase(s, i)); + serial_isa_reconfigure_irq(isa, get_uart_irq(s, i)); + if (!is_uart_enabled(s, i)) { + // TODO can't deactivate + } + } + } +} + + +/* Floppy controller */ + +static inline bool is_fdc_enabled(PC87312State *s) +{ + return (s->FER & FER_FDC_EN); +} + +static inline uint32_t get_fdc_iobase(PC87312State *s) +{ + return (s->FER & FER_FDC_ADDR) ? 0x370 : 0x3f0; +} + +static void update_fdc(PC87312State *s) +{ + ISADevice *isa; + + if (s->fdc.dev =3D=3D NULL) { + if (is_fdc_enabled(s)) { + isa =3D isa_create("isa-fdc"); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_fdc_iobase(s)= ); + qdev_prop_set_uint32(&isa->qdev, "irq", 6); + if (s->fdc.drive[0] !=3D NULL) { + qdev_prop_set_drive_nofail(&isa->qdev, "driveA", s->fdc.= drive[0]); + } + if (s->fdc.drive[1] !=3D NULL) { + qdev_prop_set_drive_nofail(&isa->qdev, "driveB", s->fdc.= drive[1]); + } + qdev_init_nofail(&isa->qdev); + s->fdc.dev =3D &isa->qdev; + } + } else { + isa =3D DO_UPCAST(ISADevice, qdev, s->fdc.dev); + fdctrl_isa_reconfigure_iobase(isa, get_fdc_iobase(s)); + if (!is_fdc_enabled(s)) { + // TODO can't deactivate + } + } +} + + +/* IDE controller */ + +static inline bool is_ide_enabled(PC87312State *s) +{ + return (s->FER & FER_IDE_EN); +} + +static inline uint32_t get_ide_iobase(PC87312State *s) +{ + return (s->FER & FER_IDE_ADDR) ? 0x170 : 0x1f0; +} + +static void update_ide(PC87312State *s) +{ + ISADevice *isa; + + if (s->ide.dev =3D=3D NULL) { + if (is_ide_enabled(s)) { + isa =3D isa_create("isa-ide"); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_ide_iobase(s)= ); + qdev_prop_set_uint32(&isa->qdev, "iobase2", get_ide_iobase(s= ) + 0x206); + qdev_prop_set_uint32(&isa->qdev, "irq", 14); + qdev_init_nofail(&isa->qdev); + s->ide.dev =3D &isa->qdev; + } + } else { + isa =3D DO_UPCAST(ISADevice, qdev, s->ide.dev); + isa_ide_reconfigure_iobase(isa, get_ide_iobase(s), + get_ide_iobase(s) + 0x206); + if (!is_ide_enabled(s)) { + // TODO can't deactivate + } + } +} + + +static void update_mappings(PC87312State *s) +{ + update_parallel(s); + update_uarts(s); + update_fdc(s); + update_ide(s); +} + +static void pc87312_soft_reset(PC87312State *s) +{ + static const uint8_t fer_init[] =3D { + 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b, + 0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f, + 0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07, + 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00, + }; + static const uint8_t far_init[] =3D { + 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01, + 0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24, + 0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24, + 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10, + }; + static const uint8_t ptr_init[] =3D { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + }; + + s->read_id_step =3D 0; + s->selected_index =3D REG_FER; + + s->FER =3D fer_init[s->config & 0x1f]; + s->FAR =3D far_init[s->config & 0x1f]; + s->PTR =3D ptr_init[s->config & 0x1f]; +} + +static void pc87312_hard_reset(PC87312State *s) +{ + pc87312_soft_reset(s); +} + +static void pc87312_ioport_write(void *opaque, uint32_t addr, uint32_t v= al) +{ + PC87312State *s =3D opaque; + + DPRINTF("%s: write %x at %x\n", __func__, val, addr); + + if ((addr & 1) =3D=3D 0) { + /* Index register */ + s->read_id_step =3D 2; + s->selected_index =3D val; + } else { + /* Data register */ + if (s->selected_index < 3) { + s->regs[s->selected_index] =3D val; + update_mappings(s); + } + } +} + +static uint32_t pc87312_ioport_read(void *opaque, uint32_t addr) +{ + PC87312State *s =3D opaque; + uint32_t val; + + if ((addr & 1) =3D=3D 0) { + /* Index register */ + if (s->read_id_step++ =3D=3D 0) { + val =3D 0x88; + } else if (s->read_id_step++ =3D=3D 1) { + val =3D 0; + } else { + val =3D s->selected_index; + } + } else { + /* Data register */ + if (s->selected_index < 3) { + val =3D s->regs[s->selected_index]; + } else { + /* Invalid selected index */ + val =3D 0; + } + } + + DPRINTF("%s: read %x at %x\n", __func__, val, addr); + return val; +} + +static void pc87312_init_core(PC87312State *s) +{ + pc87312_hard_reset(s); + + update_mappings(s); +} + +typedef struct ISAPC87312State { + ISADevice dev; + uint32_t iobase; + PC87312State state; +} ISAPC87312State; + +static void isa_pc87312_reset(DeviceState *d) +{ + PC87312State *s =3D &container_of(d, ISAPC87312State, dev.qdev)->sta= te; + pc87312_soft_reset(s); +} + +static int isa_pc87312_init(ISADevice *dev) +{ + ISAPC87312State *isa =3D DO_UPCAST(ISAPC87312State, dev, dev); + PC87312State *s =3D &isa->state; + + pc87312_init_core(s); + + register_ioport_write(isa->iobase, 2, 1, pc87312_ioport_write, s); + register_ioport_read(isa->iobase, 2, 1, pc87312_ioport_read, s); + return 0; +} + +static ISADeviceInfo pc87312_isa_info =3D { + .qdev.name =3D "isa-pc87312", + .qdev.size =3D sizeof(ISAPC87312State), + .qdev.reset =3D isa_pc87312_reset, + .init =3D isa_pc87312_init, + .qdev.props =3D (Property[]) { + DEFINE_PROP_HEX32("iobase", ISAPC87312State, iobase, 0x398), + DEFINE_PROP_UINT8("config", ISAPC87312State, state.config, 1), + DEFINE_PROP_CHR("parallel", ISAPC87312State, state.parallel.chr)= , + DEFINE_PROP_CHR("uart1", ISAPC87312State, state.uart[0].chr), + DEFINE_PROP_CHR("uart2", ISAPC87312State, state.uart[1].chr), + DEFINE_PROP_DRIVE("floppyA", ISAPC87312State, state.fdc.drive[0]= ), + DEFINE_PROP_DRIVE("floppyB", ISAPC87312State, state.fdc.drive[1]= ), + DEFINE_PROP_END_OF_LIST() + }, +}; + +static void pc87312_register_devices(void) +{ + isa_qdev_register(&pc87312_isa_info); +} + +device_init(pc87312_register_devices) --=20 1.7.5.3