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Subject: Re: [PATCH 2/4] perf, x86: Add Intel Nhm/Wsm/Snb load latency
 support
From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Lin Ming <ming.m.lin@intel.com>
Cc: Ingo Molnar <mingo@elte.hu>, Andi Kleen <andi@firstfloor.org>,
        Stephane Eranian <eranian@google.com>,
        Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
        linux-kernel <linux-kernel@vger.kernel.org>
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Date: Tue, 05 Jul 2011 15:17:48 +0200
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On Mon, 2011-07-04 at 08:02 +0000, Lin Ming wrote:
> +#define INTEL_EVENT_EXTRA_REG2(event, msr, vm)    \
> +       EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
> +                       ARCH_PERFMON_EVENTSEL_UMASK, vm) 

That's inconsistent wrt the normal constraints, INTEL_UEVENT_EXTRA_REG
would be the consistent name.

#define INTEL_UEVENT_EXTRA_REG(event, msr, vm)	\
	EVENT_EXTRA_REG(event, msr, INTEL_ARCH_EVENT_MASK, vm)