From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: [RFC v5 67/86] arm_timer: convert to memory API Date: Wed, 20 Jul 2011 19:50:17 +0300 Message-ID: <1311180636-17012-68-git-send-email-avi@redhat.com> References: <1311180636-17012-1-git-send-email-avi@redhat.com> Cc: kvm@vger.kernel.org To: qemu-devel@nongnu.org Return-path: Received: from mx1.redhat.com ([209.132.183.28]:40515 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752546Ab1GTQu7 (ORCPT ); Wed, 20 Jul 2011 12:50:59 -0400 In-Reply-To: <1311180636-17012-1-git-send-email-avi@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: Signed-off-by: Avi Kivity --- hw/arm_timer.c | 55 ++++++++++++++++++++----------------------------------- 1 files changed, 20 insertions(+), 35 deletions(-) diff --git a/hw/arm_timer.c b/hw/arm_timer.c index dac9e70..ee15ca5 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -176,6 +176,7 @@ static arm_timer_state *arm_timer_init(uint32_t freq) typedef struct { SysBusDevice busdev; + MemoryRegion iomem; arm_timer_state *timer[2]; int level[2]; qemu_irq irq; @@ -190,7 +191,8 @@ static void sp804_set_irq(void *opaque, int irq, int level) qemu_set_irq(s->irq, s->level[0] || s->level[1]); } -static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) +static uint64_t sp804_read(void *opaque, target_phys_addr_t offset, + unsigned size) { sp804_state *s = (sp804_state *)opaque; @@ -203,7 +205,7 @@ static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) } static void sp804_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { sp804_state *s = (sp804_state *)opaque; @@ -214,19 +216,12 @@ static void sp804_write(void *opaque, target_phys_addr_t offset, } } -static CPUReadMemoryFunc * const sp804_readfn[] = { - sp804_read, - sp804_read, - sp804_read +static const MemoryRegionOps sp804_ops = { + .read = sp804_read, + .write = sp804_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const sp804_writefn[] = { - sp804_write, - sp804_write, - sp804_write -}; - - static const VMStateDescription vmstate_sp804 = { .name = "sp804", .version_id = 1, @@ -240,7 +235,6 @@ static const VMStateDescription vmstate_sp804 = { static int sp804_init(SysBusDevice *dev) { - int iomemtype; sp804_state *s = FROM_SYSBUS(sp804_state, dev); qemu_irq *qi; @@ -252,9 +246,8 @@ static int sp804_init(SysBusDevice *dev) s->timer[1] = arm_timer_init(1000000); s->timer[0]->irq = qi[0]; s->timer[1]->irq = qi[1]; - iomemtype = cpu_register_io_memory(sp804_readfn, - sp804_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); vmstate_register(&dev->qdev, -1, &vmstate_sp804, s); return 0; } @@ -264,10 +257,12 @@ static int sp804_init(SysBusDevice *dev) typedef struct { SysBusDevice busdev; + MemoryRegion iomem; arm_timer_state *timer[3]; } icp_pit_state; -static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) +static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset, + unsigned size) { icp_pit_state *s = (icp_pit_state *)opaque; int n; @@ -282,7 +277,7 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) } static void icp_pit_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { icp_pit_state *s = (icp_pit_state *)opaque; int n; @@ -295,22 +290,14 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset, arm_timer_write(s->timer[n], offset & 0xff, value); } - -static CPUReadMemoryFunc * const icp_pit_readfn[] = { - icp_pit_read, - icp_pit_read, - icp_pit_read -}; - -static CPUWriteMemoryFunc * const icp_pit_writefn[] = { - icp_pit_write, - icp_pit_write, - icp_pit_write +static const MemoryRegionOps icp_pit_ops = { + .read = icp_pit_read, + .write = icp_pit_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int icp_pit_init(SysBusDevice *dev) { - int iomemtype; icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); /* Timer 0 runs at the system clock speed (40MHz). */ @@ -323,10 +310,8 @@ static int icp_pit_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->timer[1]->irq); sysbus_init_irq(dev, &s->timer[2]->irq); - iomemtype = cpu_register_io_memory(icp_pit_readfn, - icp_pit_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); /* This device has no state to save/restore. The component timers will save themselves. */ return 0; -- 1.7.5.3 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:60228) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qja9P-0007l1-MX for qemu-devel@nongnu.org; Wed, 20 Jul 2011 13:01:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qja9N-0007BA-Nv for qemu-devel@nongnu.org; Wed, 20 Jul 2011 13:01:35 -0400 Received: from mx1.redhat.com ([209.132.183.28]:11660) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QjZz2-0004wu-Df for qemu-devel@nongnu.org; Wed, 20 Jul 2011 12:50:57 -0400 From: Avi Kivity Date: Wed, 20 Jul 2011 19:50:17 +0300 Message-Id: <1311180636-17012-68-git-send-email-avi@redhat.com> In-Reply-To: <1311180636-17012-1-git-send-email-avi@redhat.com> References: <1311180636-17012-1-git-send-email-avi@redhat.com> Subject: [Qemu-devel] [RFC v5 67/86] arm_timer: convert to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org Signed-off-by: Avi Kivity --- hw/arm_timer.c | 55 ++++++++++++++++++++----------------------------------- 1 files changed, 20 insertions(+), 35 deletions(-) diff --git a/hw/arm_timer.c b/hw/arm_timer.c index dac9e70..ee15ca5 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -176,6 +176,7 @@ static arm_timer_state *arm_timer_init(uint32_t freq) typedef struct { SysBusDevice busdev; + MemoryRegion iomem; arm_timer_state *timer[2]; int level[2]; qemu_irq irq; @@ -190,7 +191,8 @@ static void sp804_set_irq(void *opaque, int irq, int level) qemu_set_irq(s->irq, s->level[0] || s->level[1]); } -static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) +static uint64_t sp804_read(void *opaque, target_phys_addr_t offset, + unsigned size) { sp804_state *s = (sp804_state *)opaque; @@ -203,7 +205,7 @@ static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) } static void sp804_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { sp804_state *s = (sp804_state *)opaque; @@ -214,19 +216,12 @@ static void sp804_write(void *opaque, target_phys_addr_t offset, } } -static CPUReadMemoryFunc * const sp804_readfn[] = { - sp804_read, - sp804_read, - sp804_read +static const MemoryRegionOps sp804_ops = { + .read = sp804_read, + .write = sp804_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const sp804_writefn[] = { - sp804_write, - sp804_write, - sp804_write -}; - - static const VMStateDescription vmstate_sp804 = { .name = "sp804", .version_id = 1, @@ -240,7 +235,6 @@ static const VMStateDescription vmstate_sp804 = { static int sp804_init(SysBusDevice *dev) { - int iomemtype; sp804_state *s = FROM_SYSBUS(sp804_state, dev); qemu_irq *qi; @@ -252,9 +246,8 @@ static int sp804_init(SysBusDevice *dev) s->timer[1] = arm_timer_init(1000000); s->timer[0]->irq = qi[0]; s->timer[1]->irq = qi[1]; - iomemtype = cpu_register_io_memory(sp804_readfn, - sp804_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); vmstate_register(&dev->qdev, -1, &vmstate_sp804, s); return 0; } @@ -264,10 +257,12 @@ static int sp804_init(SysBusDevice *dev) typedef struct { SysBusDevice busdev; + MemoryRegion iomem; arm_timer_state *timer[3]; } icp_pit_state; -static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) +static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset, + unsigned size) { icp_pit_state *s = (icp_pit_state *)opaque; int n; @@ -282,7 +277,7 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) } static void icp_pit_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { icp_pit_state *s = (icp_pit_state *)opaque; int n; @@ -295,22 +290,14 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset, arm_timer_write(s->timer[n], offset & 0xff, value); } - -static CPUReadMemoryFunc * const icp_pit_readfn[] = { - icp_pit_read, - icp_pit_read, - icp_pit_read -}; - -static CPUWriteMemoryFunc * const icp_pit_writefn[] = { - icp_pit_write, - icp_pit_write, - icp_pit_write +static const MemoryRegionOps icp_pit_ops = { + .read = icp_pit_read, + .write = icp_pit_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int icp_pit_init(SysBusDevice *dev) { - int iomemtype; icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); /* Timer 0 runs at the system clock speed (40MHz). */ @@ -323,10 +310,8 @@ static int icp_pit_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->timer[1]->irq); sysbus_init_irq(dev, &s->timer[2]->irq); - iomemtype = cpu_register_io_memory(icp_pit_readfn, - icp_pit_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); /* This device has no state to save/restore. The component timers will save themselves. */ return 0; -- 1.7.5.3