From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: [RFC v5 73/86] pcie_host: convert to memory API Date: Wed, 20 Jul 2011 19:50:23 +0300 Message-ID: <1311180636-17012-74-git-send-email-avi@redhat.com> References: <1311180636-17012-1-git-send-email-avi@redhat.com> Cc: kvm@vger.kernel.org To: qemu-devel@nongnu.org Return-path: Received: from mx1.redhat.com ([209.132.183.28]:18138 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752333Ab1GTQuz (ORCPT ); Wed, 20 Jul 2011 12:50:55 -0400 In-Reply-To: <1311180636-17012-1-git-send-email-avi@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: Assuming that mmcfg size cannot change at runtime. Signed-off-by: Avi Kivity --- hw/pcie_host.c | 98 ++++++++++++++----------------------------------------- hw/pcie_host.h | 12 +++--- 2 files changed, 31 insertions(+), 79 deletions(-) diff --git a/hw/pcie_host.c b/hw/pcie_host.c index b749865..d352ac9 100644 --- a/hw/pcie_host.c +++ b/hw/pcie_host.c @@ -52,9 +52,11 @@ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s, PCIE_MMCFG_DEVFN(mmcfg_addr)); } -static void pcie_mmcfg_data_write(PCIBus *s, - uint32_t mmcfg_addr, uint32_t val, int len) +static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr, + uint64_t val, unsigned len) { + PCIExpressHost *e = opaque; + PCIBus *s = e->pci.bus; PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); if (!pci_dev) @@ -64,8 +66,11 @@ static void pcie_mmcfg_data_write(PCIBus *s, PCIE_MMCFG_CONFOFFSET(mmcfg_addr), val, len); } -static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t addr, int len) +static uint64_t pcie_mmcfg_data_read(void *opaque, target_phys_addr_t addr, + unsigned len) { + PCIExpressHost *e = opaque; + PCIBus *s = e->pci.bus; PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, addr); assert(len == 1 || len == 2 || len == 4); @@ -75,102 +80,49 @@ static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t addr, int len) return pci_dev->config_read(pci_dev, PCIE_MMCFG_CONFOFFSET(addr), len); } -static void pcie_mmcfg_data_writeb(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - PCIExpressHost *e = opaque; - pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1); -} - -static void pcie_mmcfg_data_writew(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - PCIExpressHost *e = opaque; - pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2); -} - -static void pcie_mmcfg_data_writel(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - PCIExpressHost *e = opaque; - pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4); -} - -static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr) -{ - PCIExpressHost *e = opaque; - return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1); -} - -static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr) -{ - PCIExpressHost *e = opaque; - return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2); -} - -static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr) -{ - PCIExpressHost *e = opaque; - return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4); -} - - -static CPUWriteMemoryFunc * const pcie_mmcfg_write[] = -{ - pcie_mmcfg_data_writeb, - pcie_mmcfg_data_writew, - pcie_mmcfg_data_writel, -}; - -static CPUReadMemoryFunc * const pcie_mmcfg_read[] = -{ - pcie_mmcfg_data_readb, - pcie_mmcfg_data_readw, - pcie_mmcfg_data_readl, +static const MemoryRegionOps pcie_mmcfg_ops = { + .read = pcie_mmcfg_data_read, + .write = pcie_mmcfg_data_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */ #define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL) -int pcie_host_init(PCIExpressHost *e) +int pcie_host_init(PCIExpressHost *e, uint32_t size) { + assert(!(size & (size - 1))); /* power of 2 */ + assert(size >= PCIE_MMCFG_SIZE_MIN); + assert(size <= PCIE_MMCFG_SIZE_MAX); e->base_addr = PCIE_BASE_ADDR_UNMAPPED; - e->mmio_index = - cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e, - DEVICE_NATIVE_ENDIAN); - if (e->mmio_index < 0) { - return -1; - } + e->size = size; + memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size); return 0; } +#include "exec-memory.h" + void pcie_host_mmcfg_unmap(PCIExpressHost *e) { if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) { - cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), &e->mmio); e->base_addr = PCIE_BASE_ADDR_UNMAPPED; } } -void pcie_host_mmcfg_map(PCIExpressHost *e, - target_phys_addr_t addr, uint32_t size) +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr) { - assert(!(size & (size - 1))); /* power of 2 */ - assert(size >= PCIE_MMCFG_SIZE_MIN); - assert(size <= PCIE_MMCFG_SIZE_MAX); - e->base_addr = addr; - e->size = size; - cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index); + memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio); } void pcie_host_mmcfg_update(PCIExpressHost *e, int enable, - target_phys_addr_t addr, uint32_t size) + target_phys_addr_t addr) { pcie_host_mmcfg_unmap(e); if (enable) { - pcie_host_mmcfg_map(e, addr, size); + pcie_host_mmcfg_map(e, addr); } } diff --git a/hw/pcie_host.h b/hw/pcie_host.h index a202661..0074508 100644 --- a/hw/pcie_host.h +++ b/hw/pcie_host.h @@ -22,6 +22,7 @@ #define PCIE_HOST_H #include "pci_host.h" +#include "memory.h" struct PCIExpressHost { PCIHostState pci; @@ -34,16 +35,15 @@ struct PCIExpressHost { /* the size of MMCONFIG area. It's host bridge dependent */ target_phys_addr_t size; - /* result of cpu_register_io_memory() to map MMCONFIG area */ - int mmio_index; + /* MMCONFIG mmio area */ + MemoryRegion mmio; }; -int pcie_host_init(PCIExpressHost *e); +int pcie_host_init(PCIExpressHost *e, uint32_t size); void pcie_host_mmcfg_unmap(PCIExpressHost *e); -void pcie_host_mmcfg_map(PCIExpressHost *e, - target_phys_addr_t addr, uint32_t size); +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr); void pcie_host_mmcfg_update(PCIExpressHost *e, int enable, - target_phys_addr_t addr, uint32_t size); + target_phys_addr_t addr); #endif /* PCIE_HOST_H */ -- 1.7.5.3 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:60335) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qja9e-0007q2-Aq for qemu-devel@nongnu.org; Wed, 20 Jul 2011 13:01:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qja9c-0007Ei-6I for qemu-devel@nongnu.org; Wed, 20 Jul 2011 13:01:49 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50876) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QjZyx-0004xM-1Y for qemu-devel@nongnu.org; Wed, 20 Jul 2011 12:50:49 -0400 From: Avi Kivity Date: Wed, 20 Jul 2011 19:50:23 +0300 Message-Id: <1311180636-17012-74-git-send-email-avi@redhat.com> In-Reply-To: <1311180636-17012-1-git-send-email-avi@redhat.com> References: <1311180636-17012-1-git-send-email-avi@redhat.com> Subject: [Qemu-devel] [RFC v5 73/86] pcie_host: convert to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org Assuming that mmcfg size cannot change at runtime. Signed-off-by: Avi Kivity --- hw/pcie_host.c | 98 ++++++++++++++----------------------------------------- hw/pcie_host.h | 12 +++--- 2 files changed, 31 insertions(+), 79 deletions(-) diff --git a/hw/pcie_host.c b/hw/pcie_host.c index b749865..d352ac9 100644 --- a/hw/pcie_host.c +++ b/hw/pcie_host.c @@ -52,9 +52,11 @@ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s, PCIE_MMCFG_DEVFN(mmcfg_addr)); } -static void pcie_mmcfg_data_write(PCIBus *s, - uint32_t mmcfg_addr, uint32_t val, int len) +static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr, + uint64_t val, unsigned len) { + PCIExpressHost *e = opaque; + PCIBus *s = e->pci.bus; PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); if (!pci_dev) @@ -64,8 +66,11 @@ static void pcie_mmcfg_data_write(PCIBus *s, PCIE_MMCFG_CONFOFFSET(mmcfg_addr), val, len); } -static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t addr, int len) +static uint64_t pcie_mmcfg_data_read(void *opaque, target_phys_addr_t addr, + unsigned len) { + PCIExpressHost *e = opaque; + PCIBus *s = e->pci.bus; PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, addr); assert(len == 1 || len == 2 || len == 4); @@ -75,102 +80,49 @@ static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t addr, int len) return pci_dev->config_read(pci_dev, PCIE_MMCFG_CONFOFFSET(addr), len); } -static void pcie_mmcfg_data_writeb(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - PCIExpressHost *e = opaque; - pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1); -} - -static void pcie_mmcfg_data_writew(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - PCIExpressHost *e = opaque; - pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2); -} - -static void pcie_mmcfg_data_writel(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - PCIExpressHost *e = opaque; - pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4); -} - -static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr) -{ - PCIExpressHost *e = opaque; - return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1); -} - -static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr) -{ - PCIExpressHost *e = opaque; - return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2); -} - -static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr) -{ - PCIExpressHost *e = opaque; - return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4); -} - - -static CPUWriteMemoryFunc * const pcie_mmcfg_write[] = -{ - pcie_mmcfg_data_writeb, - pcie_mmcfg_data_writew, - pcie_mmcfg_data_writel, -}; - -static CPUReadMemoryFunc * const pcie_mmcfg_read[] = -{ - pcie_mmcfg_data_readb, - pcie_mmcfg_data_readw, - pcie_mmcfg_data_readl, +static const MemoryRegionOps pcie_mmcfg_ops = { + .read = pcie_mmcfg_data_read, + .write = pcie_mmcfg_data_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */ #define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL) -int pcie_host_init(PCIExpressHost *e) +int pcie_host_init(PCIExpressHost *e, uint32_t size) { + assert(!(size & (size - 1))); /* power of 2 */ + assert(size >= PCIE_MMCFG_SIZE_MIN); + assert(size <= PCIE_MMCFG_SIZE_MAX); e->base_addr = PCIE_BASE_ADDR_UNMAPPED; - e->mmio_index = - cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e, - DEVICE_NATIVE_ENDIAN); - if (e->mmio_index < 0) { - return -1; - } + e->size = size; + memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size); return 0; } +#include "exec-memory.h" + void pcie_host_mmcfg_unmap(PCIExpressHost *e) { if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) { - cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), &e->mmio); e->base_addr = PCIE_BASE_ADDR_UNMAPPED; } } -void pcie_host_mmcfg_map(PCIExpressHost *e, - target_phys_addr_t addr, uint32_t size) +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr) { - assert(!(size & (size - 1))); /* power of 2 */ - assert(size >= PCIE_MMCFG_SIZE_MIN); - assert(size <= PCIE_MMCFG_SIZE_MAX); - e->base_addr = addr; - e->size = size; - cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index); + memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio); } void pcie_host_mmcfg_update(PCIExpressHost *e, int enable, - target_phys_addr_t addr, uint32_t size) + target_phys_addr_t addr) { pcie_host_mmcfg_unmap(e); if (enable) { - pcie_host_mmcfg_map(e, addr, size); + pcie_host_mmcfg_map(e, addr); } } diff --git a/hw/pcie_host.h b/hw/pcie_host.h index a202661..0074508 100644 --- a/hw/pcie_host.h +++ b/hw/pcie_host.h @@ -22,6 +22,7 @@ #define PCIE_HOST_H #include "pci_host.h" +#include "memory.h" struct PCIExpressHost { PCIHostState pci; @@ -34,16 +35,15 @@ struct PCIExpressHost { /* the size of MMCONFIG area. It's host bridge dependent */ target_phys_addr_t size; - /* result of cpu_register_io_memory() to map MMCONFIG area */ - int mmio_index; + /* MMCONFIG mmio area */ + MemoryRegion mmio; }; -int pcie_host_init(PCIExpressHost *e); +int pcie_host_init(PCIExpressHost *e, uint32_t size); void pcie_host_mmcfg_unmap(PCIExpressHost *e); -void pcie_host_mmcfg_map(PCIExpressHost *e, - target_phys_addr_t addr, uint32_t size); +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr); void pcie_host_mmcfg_update(PCIExpressHost *e, int enable, - target_phys_addr_t addr, uint32_t size); + target_phys_addr_t addr); #endif /* PCIE_HOST_H */ -- 1.7.5.3