Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Anton Vorontsov]

On Fri, Jul 22, 2011 at 06:15:17PM +0800, Roy Zang wrote:
[...]
>  	if (host->version >= SDHCI_SPEC_200) {
> -		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> -		ctrl &= ~SDHCI_CTRL_DMA_MASK;
> -		if ((host->flags & SDHCI_REQ_USE_DMA) &&
> -			(host->flags & SDHCI_USE_ADMA))
> -			ctrl |= SDHCI_CTRL_ADMA32;
> -		else
> -			ctrl |= SDHCI_CTRL_SDMA;
> -		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> +		if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
> +#define ESDHCI_PROCTL_DMAS_MASK		0x00000300
> +#define ESDHCI_PROCTL_ADMA32		0x00000200
> +#define ESDHCI_PROCTL_SDMA		0x00000000
> +			ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
> +			ctrl &= ~ESDHCI_PROCTL_DMAS_MASK;
> +			if ((host->flags & SDHCI_REQ_USE_DMA) &&
> +				(host->flags & SDHCI_USE_ADMA))
> +				ctrl |= ESDHCI_PROCTL_ADMA32;
> +			else
> +				ctrl |= ESDHCI_PROCTL_SDMA;
> +			sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
> +		} else {
> +			ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> +			ctrl &= ~SDHCI_CTRL_DMA_MASK;
> +			if ((host->flags & SDHCI_REQ_USE_DMA) &&
> +				(host->flags & SDHCI_USE_ADMA))
> +				ctrl |= SDHCI_CTRL_ADMA32;
> +			else
> +				ctrl |= SDHCI_CTRL_SDMA;
> +			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);

We try to not pollute generic sdhci.c driver with chip-specific
quirks.

Maybe you can do the fixups via IO accessors? Or by introducing
some additional sdhci op?

[...]
>  	if (power != (unsigned short)-1) {
>  		switch (1 << power) {
> +#define	ESDHCI_FSL_POWER_MASK	0x40
> +#define	ESDHCI_FSL_POWER_180	0x00
> +#define	ESDHCI_FSL_POWER_300	0x40

Same here. The driver will rot quickly if everyone would start
putting chip-specific quirks into sdhci.c. Please don't.

Thanks,

-- 
Anton Vorontsov
Email: cbouatmailru@gmail.com

Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Anton Vorontsov]

On Fri, Jul 22, 2011 at 06:15:17PM +0800, Roy Zang wrote:
[...]
>  	if (host->version >= SDHCI_SPEC_200) {
> -		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> -		ctrl &= ~SDHCI_CTRL_DMA_MASK;
> -		if ((host->flags & SDHCI_REQ_USE_DMA) &&
> -			(host->flags & SDHCI_USE_ADMA))
> -			ctrl |= SDHCI_CTRL_ADMA32;
> -		else
> -			ctrl |= SDHCI_CTRL_SDMA;
> -		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> +		if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
> +#define ESDHCI_PROCTL_DMAS_MASK		0x00000300
> +#define ESDHCI_PROCTL_ADMA32		0x00000200
> +#define ESDHCI_PROCTL_SDMA		0x00000000
> +			ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
> +			ctrl &= ~ESDHCI_PROCTL_DMAS_MASK;
> +			if ((host->flags & SDHCI_REQ_USE_DMA) &&
> +				(host->flags & SDHCI_USE_ADMA))
> +				ctrl |= ESDHCI_PROCTL_ADMA32;
> +			else
> +				ctrl |= ESDHCI_PROCTL_SDMA;
> +			sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
> +		} else {
> +			ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> +			ctrl &= ~SDHCI_CTRL_DMA_MASK;
> +			if ((host->flags & SDHCI_REQ_USE_DMA) &&
> +				(host->flags & SDHCI_USE_ADMA))
> +				ctrl |= SDHCI_CTRL_ADMA32;
> +			else
> +				ctrl |= SDHCI_CTRL_SDMA;
> +			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);

We try to not pollute generic sdhci.c driver with chip-specific
quirks.

Maybe you can do the fixups via IO accessors? Or by introducing
some additional sdhci op?

[...]
>  	if (power != (unsigned short)-1) {
>  		switch (1 << power) {
> +#define	ESDHCI_FSL_POWER_MASK	0x40
> +#define	ESDHCI_FSL_POWER_180	0x00
> +#define	ESDHCI_FSL_POWER_300	0x40

Same here. The driver will rot quickly if everyone would start
putting chip-specific quirks into sdhci.c. Please don't.

Thanks,

-- 
Anton Vorontsov
Email: cbouatmailru@gmail.com

[PATCH 1/2 v2] eSDHC: Access Freescale eSDHC registers by 32-bit

[Roy Zang]

From: Xu lei <B33228@freescale.com>

For Freescale eSDHC registers only support 32-bit accesses,
this patch ensure that all Freescale eSDHC register accesses
are 32-bit.

Signed-off-by: Xu lei <B33228@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
this patch set replaces previous patches:
https://patchwork.kernel.org/patch/943332/
https://patchwork.kernel.org/patch/943342/
https://patchwork.kernel.org/patch/943322/

The last one is discarded according to the comment from Anton.


just resend with the new patch set. no change for this patch comparing
to previous version.

 drivers/mmc/host/sdhci-of-esdhc.c |   18 ++++++++++++++----
 1 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index ba40d6d..c9a8519 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -1,7 +1,7 @@
 /*
  * Freescale eSDHC controller driver.
  *
- * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2007, 2010 Freescale Semiconductor, Inc.
  * Copyright (c) 2009 MontaVista Software, Inc.
  *
  * Authors: Xiaobo Xie <X.Xie@freescale.com>
@@ -23,11 +23,21 @@
 static u16 esdhc_readw(struct sdhci_host *host, int reg)
 {
 	u16 ret;
+	int base = reg & ~0x3;
+	int shift = (reg & 0x2) * 8;
 
 	if (unlikely(reg == SDHCI_HOST_VERSION))
-		ret = in_be16(host->ioaddr + reg);
+		ret = in_be32(host->ioaddr + base) & 0xffff;
 	else
-		ret = sdhci_be32bs_readw(host, reg);
+		ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
+	return ret;
+}
+
+static u8 esdhc_readb(struct sdhci_host *host, int reg)
+{
+	int base = reg & ~0x3;
+	int shift = (reg & 0x3) * 8;
+	u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
 	return ret;
 }
 
@@ -79,7 +89,7 @@ struct sdhci_of_data sdhci_esdhc = {
 	.ops = {
 		.read_l = sdhci_be32bs_readl,
 		.read_w = esdhc_readw,
-		.read_b = sdhci_be32bs_readb,
+		.read_b = esdhc_readb,
 		.write_l = sdhci_be32bs_writel,
 		.write_w = esdhc_writew,
 		.write_b = esdhc_writeb,
-- 
1.6.0.6

[PATCH 1/2 v2] eSDHC: Access Freescale eSDHC registers by 32-bit

[Roy Zang]

From: Xu lei <B33228@freescale.com>

For Freescale eSDHC registers only support 32-bit accesses,
this patch ensure that all Freescale eSDHC register accesses
are 32-bit.

Signed-off-by: Xu lei <B33228@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
this patch set replaces previous patches:
https://patchwork.kernel.org/patch/943332/
https://patchwork.kernel.org/patch/943342/
https://patchwork.kernel.org/patch/943322/

The last one is discarded according to the comment from Anton.


just resend with the new patch set. no change for this patch comparing
to previous version.

 drivers/mmc/host/sdhci-of-esdhc.c |   18 ++++++++++++++----
 1 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index ba40d6d..c9a8519 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -1,7 +1,7 @@
 /*
  * Freescale eSDHC controller driver.
  *
- * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2007, 2010 Freescale Semiconductor, Inc.
  * Copyright (c) 2009 MontaVista Software, Inc.
  *
  * Authors: Xiaobo Xie <X.Xie@freescale.com>
@@ -23,11 +23,21 @@
 static u16 esdhc_readw(struct sdhci_host *host, int reg)
 {
 	u16 ret;
+	int base = reg & ~0x3;
+	int shift = (reg & 0x2) * 8;
 
 	if (unlikely(reg == SDHCI_HOST_VERSION))
-		ret = in_be16(host->ioaddr + reg);
+		ret = in_be32(host->ioaddr + base) & 0xffff;
 	else
-		ret = sdhci_be32bs_readw(host, reg);
+		ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
+	return ret;
+}
+
+static u8 esdhc_readb(struct sdhci_host *host, int reg)
+{
+	int base = reg & ~0x3;
+	int shift = (reg & 0x3) * 8;
+	u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
 	return ret;
 }
 
@@ -79,7 +89,7 @@ struct sdhci_of_data sdhci_esdhc = {
 	.ops = {
 		.read_l = sdhci_be32bs_readl,
 		.read_w = esdhc_readw,
-		.read_b = sdhci_be32bs_readb,
+		.read_b = esdhc_readb,
 		.write_l = sdhci_be32bs_writel,
 		.write_w = esdhc_writew,
 		.write_b = esdhc_writeb,
-- 
1.6.0.6

[PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Roy Zang]

From: Xu lei <B33228@freescale.com>

When esdhc module was enabled in p5020, there were following errors:

mmc0: Timeout waiting for hardware interrupt.
mmc0: error -110 whilst initialising SD card
mmc0: Unexpected interrupt 0x02000000.
mmc0: Timeout waiting for hardware interrupt.
mmc0: error -110 whilst initialising SD card
mmc0: Unexpected interrupt 0x02000000.

It is because ESDHC controller has different bit setting for PROCTL
register, when kernel sets Power Control Register by method for standard
SD Host Specification, it would overwritten FSL ESDHC PROCTL[DMAS];
when it set Host Control Registers[DMAS], it sets PROCTL[EMODE] and
PROCTL[D3CD]. These operations will set bad bits for PROCTL Register
on FSL ESDHC Controller and cause errors, so this patch will make esdhc
driver access FSL PROCTL Register according to block guide instead of
standard SD Host Specification.

For some FSL chips, such as MPC8536/P2020, PROCTL[VOLT_SEL] and PROCTL[DMAS]
bits are reserved and even if they are set to wrong bits there is no error.
But considering that all FSL ESDHC Controller register map is not fully
compliant to standard SD Host Specification, we put the patch to all of
FSL ESDHC Controllers.

Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
v2:v1 some minor code style fix according to Venkatraman's comment.

 drivers/mmc/host/sdhci-of-core.c |    3 ++
 drivers/mmc/host/sdhci.c         |   64 ++++++++++++++++++++++++++++++-------
 include/linux/mmc/sdhci.h        |    6 ++-
 3 files changed, 59 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index 60e4186..fede43d 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -179,6 +179,9 @@ static int __devinit sdhci_of_probe(struct platform_device *ofdev)
 	if (sdhci_of_wp_inverted(np))
 		host->quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
 
+	if (of_device_is_compatible(np, "fsl,esdhc"))
+		host->quirks |= SDHCI_QUIRK_QORIQ_PROCTL_WEIRD;
+
 	clk = of_get_property(np, "clock-frequency", &size);
 	if (clk && size == sizeof(*clk) && *clk)
 		of_host->clock = be32_to_cpup(clk);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 58d5436..855fbe8 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -674,7 +674,7 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 {
 	u8 count;
-	u8 ctrl;
+	u32 ctrl;
 	struct mmc_data *data = cmd->data;
 	int ret;
 
@@ -807,14 +807,28 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 	 * is ADMA.
 	 */
 	if (host->version >= SDHCI_SPEC_200) {
-		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
-		ctrl &= ~SDHCI_CTRL_DMA_MASK;
-		if ((host->flags & SDHCI_REQ_USE_DMA) &&
-			(host->flags & SDHCI_USE_ADMA))
-			ctrl |= SDHCI_CTRL_ADMA32;
-		else
-			ctrl |= SDHCI_CTRL_SDMA;
-		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+		if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
+#define ESDHCI_PROCTL_DMAS_MASK		0x00000300
+#define ESDHCI_PROCTL_ADMA32		0x00000200
+#define ESDHCI_PROCTL_SDMA		0x00000000
+			ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
+			ctrl &= ~ESDHCI_PROCTL_DMAS_MASK;
+			if ((host->flags & SDHCI_REQ_USE_DMA) &&
+				(host->flags & SDHCI_USE_ADMA))
+				ctrl |= ESDHCI_PROCTL_ADMA32;
+			else
+				ctrl |= ESDHCI_PROCTL_SDMA;
+			sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
+		} else {
+			ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+			ctrl &= ~SDHCI_CTRL_DMA_MASK;
+			if ((host->flags & SDHCI_REQ_USE_DMA) &&
+				(host->flags & SDHCI_USE_ADMA))
+				ctrl |= SDHCI_CTRL_ADMA32;
+			else
+				ctrl |= SDHCI_CTRL_SDMA;
+			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+		}
 	}
 
 	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
@@ -1138,19 +1152,32 @@ out:
 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 {
 	u8 pwr = 0;
+	u8 volt = 0;
 
 	if (power != (unsigned short)-1) {
 		switch (1 << power) {
+#define	ESDHCI_FSL_POWER_MASK	0x40
+#define	ESDHCI_FSL_POWER_180	0x00
+#define	ESDHCI_FSL_POWER_300	0x40
 		case MMC_VDD_165_195:
-			pwr = SDHCI_POWER_180;
+			if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD)
+				pwr = ESDHCI_FSL_POWER_180;
+			else
+				pwr = SDHCI_POWER_180;
 			break;
 		case MMC_VDD_29_30:
 		case MMC_VDD_30_31:
-			pwr = SDHCI_POWER_300;
+			if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD)
+				pwr = ESDHCI_FSL_POWER_300;
+			else
+				pwr = SDHCI_POWER_300;
 			break;
 		case MMC_VDD_32_33:
 		case MMC_VDD_33_34:
-			pwr = SDHCI_POWER_330;
+			if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD)
+				pwr = ESDHCI_FSL_POWER_300;
+			else
+				pwr = SDHCI_POWER_330;
 			break;
 		default:
 			BUG();
@@ -1162,6 +1189,19 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 
 	host->pwr = pwr;
 
+	/* 
+	 * FSL ESDHC Controller has no Bus Power bit,
+	 * and PROCTL[21] bit is for voltage selection.
+	 */
+	if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
+		volt = sdhci_readb(host, SDHCI_POWER_CONTROL);
+		volt &= ~ESDHCI_FSL_POWER_MASK;
+		volt |= pwr;
+		sdhci_writeb(host, volt, SDHCI_POWER_CONTROL);
+
+		return;
+	}
+
 	if (pwr == 0) {
 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 		return;
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 6a68c4e..d87abc7 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -21,7 +21,7 @@ struct sdhci_host {
 	/* Data set by hardware interface driver */
 	const char *hw_name;	/* Hardware bus name */
 
-	unsigned int quirks;	/* Deviations from spec. */
+	u64 quirks;	/* Deviations from spec. */
 
 /* Controller doesn't honor resets unless we touch the clock register */
 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1<<0)
@@ -86,7 +86,9 @@ struct sdhci_host {
 /* Controller treats ADMA descriptors with length 0000h incorrectly */
 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC		(1<<30)
 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
-#define SDHCI_QUIRK_UNSTABLE_RO_DETECT			(1<<31)
+#define SDHCI_QUIRK_UNSTABLE_RO_DETECT			(1U<<31)
+/* Controller has weird bit setting for Protocol Control Register */
+#define SDHCI_QUIRK_QORIQ_PROCTL_WEIRD			(0x100000000U)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
1.6.0.6

[PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Roy Zang]

From: Xu lei <B33228@freescale.com>

When esdhc module was enabled in p5020, there were following errors:

mmc0: Timeout waiting for hardware interrupt.
mmc0: error -110 whilst initialising SD card
mmc0: Unexpected interrupt 0x02000000.
mmc0: Timeout waiting for hardware interrupt.
mmc0: error -110 whilst initialising SD card
mmc0: Unexpected interrupt 0x02000000.

It is because ESDHC controller has different bit setting for PROCTL
register, when kernel sets Power Control Register by method for standard
SD Host Specification, it would overwritten FSL ESDHC PROCTL[DMAS];
when it set Host Control Registers[DMAS], it sets PROCTL[EMODE] and
PROCTL[D3CD]. These operations will set bad bits for PROCTL Register
on FSL ESDHC Controller and cause errors, so this patch will make esdhc
driver access FSL PROCTL Register according to block guide instead of
standard SD Host Specification.

For some FSL chips, such as MPC8536/P2020, PROCTL[VOLT_SEL] and PROCTL[DMAS]
bits are reserved and even if they are set to wrong bits there is no error.
But considering that all FSL ESDHC Controller register map is not fully
compliant to standard SD Host Specification, we put the patch to all of
FSL ESDHC Controllers.

Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
v2:v1 some minor code style fix according to Venkatraman's comment.

 drivers/mmc/host/sdhci-of-core.c |    3 ++
 drivers/mmc/host/sdhci.c         |   64 ++++++++++++++++++++++++++++++-------
 include/linux/mmc/sdhci.h        |    6 ++-
 3 files changed, 59 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index 60e4186..fede43d 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -179,6 +179,9 @@ static int __devinit sdhci_of_probe(struct platform_device *ofdev)
 	if (sdhci_of_wp_inverted(np))
 		host->quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
 
+	if (of_device_is_compatible(np, "fsl,esdhc"))
+		host->quirks |= SDHCI_QUIRK_QORIQ_PROCTL_WEIRD;
+
 	clk = of_get_property(np, "clock-frequency", &size);
 	if (clk && size == sizeof(*clk) && *clk)
 		of_host->clock = be32_to_cpup(clk);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 58d5436..855fbe8 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -674,7 +674,7 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 {
 	u8 count;
-	u8 ctrl;
+	u32 ctrl;
 	struct mmc_data *data = cmd->data;
 	int ret;
 
@@ -807,14 +807,28 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 	 * is ADMA.
 	 */
 	if (host->version >= SDHCI_SPEC_200) {
-		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
-		ctrl &= ~SDHCI_CTRL_DMA_MASK;
-		if ((host->flags & SDHCI_REQ_USE_DMA) &&
-			(host->flags & SDHCI_USE_ADMA))
-			ctrl |= SDHCI_CTRL_ADMA32;
-		else
-			ctrl |= SDHCI_CTRL_SDMA;
-		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+		if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
+#define ESDHCI_PROCTL_DMAS_MASK		0x00000300
+#define ESDHCI_PROCTL_ADMA32		0x00000200
+#define ESDHCI_PROCTL_SDMA		0x00000000
+			ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
+			ctrl &= ~ESDHCI_PROCTL_DMAS_MASK;
+			if ((host->flags & SDHCI_REQ_USE_DMA) &&
+				(host->flags & SDHCI_USE_ADMA))
+				ctrl |= ESDHCI_PROCTL_ADMA32;
+			else
+				ctrl |= ESDHCI_PROCTL_SDMA;
+			sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
+		} else {
+			ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+			ctrl &= ~SDHCI_CTRL_DMA_MASK;
+			if ((host->flags & SDHCI_REQ_USE_DMA) &&
+				(host->flags & SDHCI_USE_ADMA))
+				ctrl |= SDHCI_CTRL_ADMA32;
+			else
+				ctrl |= SDHCI_CTRL_SDMA;
+			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+		}
 	}
 
 	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
@@ -1138,19 +1152,32 @@ out:
 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 {
 	u8 pwr = 0;
+	u8 volt = 0;
 
 	if (power != (unsigned short)-1) {
 		switch (1 << power) {
+#define	ESDHCI_FSL_POWER_MASK	0x40
+#define	ESDHCI_FSL_POWER_180	0x00
+#define	ESDHCI_FSL_POWER_300	0x40
 		case MMC_VDD_165_195:
-			pwr = SDHCI_POWER_180;
+			if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD)
+				pwr = ESDHCI_FSL_POWER_180;
+			else
+				pwr = SDHCI_POWER_180;
 			break;
 		case MMC_VDD_29_30:
 		case MMC_VDD_30_31:
-			pwr = SDHCI_POWER_300;
+			if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD)
+				pwr = ESDHCI_FSL_POWER_300;
+			else
+				pwr = SDHCI_POWER_300;
 			break;
 		case MMC_VDD_32_33:
 		case MMC_VDD_33_34:
-			pwr = SDHCI_POWER_330;
+			if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD)
+				pwr = ESDHCI_FSL_POWER_300;
+			else
+				pwr = SDHCI_POWER_330;
 			break;
 		default:
 			BUG();
@@ -1162,6 +1189,19 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 
 	host->pwr = pwr;
 
+	/* 
+	 * FSL ESDHC Controller has no Bus Power bit,
+	 * and PROCTL[21] bit is for voltage selection.
+	 */
+	if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
+		volt = sdhci_readb(host, SDHCI_POWER_CONTROL);
+		volt &= ~ESDHCI_FSL_POWER_MASK;
+		volt |= pwr;
+		sdhci_writeb(host, volt, SDHCI_POWER_CONTROL);
+
+		return;
+	}
+
 	if (pwr == 0) {
 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 		return;
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 6a68c4e..d87abc7 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -21,7 +21,7 @@ struct sdhci_host {
 	/* Data set by hardware interface driver */
 	const char *hw_name;	/* Hardware bus name */
 
-	unsigned int quirks;	/* Deviations from spec. */
+	u64 quirks;	/* Deviations from spec. */
 
 /* Controller doesn't honor resets unless we touch the clock register */
 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1<<0)
@@ -86,7 +86,9 @@ struct sdhci_host {
 /* Controller treats ADMA descriptors with length 0000h incorrectly */
 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC		(1<<30)
 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
-#define SDHCI_QUIRK_UNSTABLE_RO_DETECT			(1<<31)
+#define SDHCI_QUIRK_UNSTABLE_RO_DETECT			(1U<<31)
+/* Controller has weird bit setting for Protocol Control Register */
+#define SDHCI_QUIRK_QORIQ_PROCTL_WEIRD			(0x100000000U)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
1.6.0.6

RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

> -----Original Message-----
> From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-owner@vger.kernel.org]
> On Behalf Of Anton Vorontsov
> Sent: Friday, July 22, 2011 18:15 PM
> To: Zang Roy-R61911
> Cc: linux-mmc@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; akpm@linux-
> foundation.org; Xu Lei-B33228; Kumar Gala
> Subject: Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc
> 
> On Fri, Jul 22, 2011 at 06:15:17PM +0800, Roy Zang wrote:
> [...]
> >  	if (host->version >= SDHCI_SPEC_200) {
> > -		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> > -		ctrl &= ~SDHCI_CTRL_DMA_MASK;
> > -		if ((host->flags & SDHCI_REQ_USE_DMA) &&
> > -			(host->flags & SDHCI_USE_ADMA))
> > -			ctrl |= SDHCI_CTRL_ADMA32;
> > -		else
> > -			ctrl |= SDHCI_CTRL_SDMA;
> > -		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> > +		if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
> > +#define ESDHCI_PROCTL_DMAS_MASK		0x00000300
> > +#define ESDHCI_PROCTL_ADMA32		0x00000200
> > +#define ESDHCI_PROCTL_SDMA		0x00000000
> > +			ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
> > +			ctrl &= ~ESDHCI_PROCTL_DMAS_MASK;
> > +			if ((host->flags & SDHCI_REQ_USE_DMA) &&
> > +				(host->flags & SDHCI_USE_ADMA))
> > +				ctrl |= ESDHCI_PROCTL_ADMA32;
> > +			else
> > +				ctrl |= ESDHCI_PROCTL_SDMA;
> > +			sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
> > +		} else {
> > +			ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> > +			ctrl &= ~SDHCI_CTRL_DMA_MASK;
> > +			if ((host->flags & SDHCI_REQ_USE_DMA) &&
> > +				(host->flags & SDHCI_USE_ADMA))
> > +				ctrl |= SDHCI_CTRL_ADMA32;
> > +			else
> > +				ctrl |= SDHCI_CTRL_SDMA;
> > +			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> 
> We try to not pollute generic sdhci.c driver with chip-specific
> quirks.
> 
> Maybe you can do the fixups via IO accessors? Or by introducing
> some additional sdhci op?
> 
> [...]
> >  	if (power != (unsigned short)-1) {
> >  		switch (1 << power) {
> > +#define	ESDHCI_FSL_POWER_MASK	0x40
> > +#define	ESDHCI_FSL_POWER_180	0x00
> > +#define	ESDHCI_FSL_POWER_300	0x40
> 
> Same here. The driver will rot quickly if everyone would start
> putting chip-specific quirks into sdhci.c. Please don't.
IO accessors or sdhci op might work, but it will look ugly 
and less performance efficient for io access.

If you search sdhci.c, you will see other board specific quirks.
Thanks.
Roy

RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

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RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

> -----Original Message-----
> From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-owner@vger.kernel.org]
> On Behalf Of Anton Vorontsov
> Sent: Friday, July 22, 2011 18:15 PM
> To: Zang Roy-R61911
> Cc: linux-mmc@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; akpm@linux-
> foundation.org; Xu Lei-B33228; Kumar Gala
> Subject: Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc
> 
> On Fri, Jul 22, 2011 at 06:15:17PM +0800, Roy Zang wrote:
> [...]
> >  	if (host->version >= SDHCI_SPEC_200) {
> > -		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> > -		ctrl &= ~SDHCI_CTRL_DMA_MASK;
> > -		if ((host->flags & SDHCI_REQ_USE_DMA) &&
> > -			(host->flags & SDHCI_USE_ADMA))
> > -			ctrl |= SDHCI_CTRL_ADMA32;
> > -		else
> > -			ctrl |= SDHCI_CTRL_SDMA;
> > -		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> > +		if (host->quirks & SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
> > +#define ESDHCI_PROCTL_DMAS_MASK		0x00000300
> > +#define ESDHCI_PROCTL_ADMA32		0x00000200
> > +#define ESDHCI_PROCTL_SDMA		0x00000000
> > +			ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
> > +			ctrl &= ~ESDHCI_PROCTL_DMAS_MASK;
> > +			if ((host->flags & SDHCI_REQ_USE_DMA) &&
> > +				(host->flags & SDHCI_USE_ADMA))
> > +				ctrl |= ESDHCI_PROCTL_ADMA32;
> > +			else
> > +				ctrl |= ESDHCI_PROCTL_SDMA;
> > +			sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
> > +		} else {
> > +			ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> > +			ctrl &= ~SDHCI_CTRL_DMA_MASK;
> > +			if ((host->flags & SDHCI_REQ_USE_DMA) &&
> > +				(host->flags & SDHCI_USE_ADMA))
> > +				ctrl |= SDHCI_CTRL_ADMA32;
> > +			else
> > +				ctrl |= SDHCI_CTRL_SDMA;
> > +			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> 
> We try to not pollute generic sdhci.c driver with chip-specific
> quirks.
> 
> Maybe you can do the fixups via IO accessors? Or by introducing
> some additional sdhci op?
Anton,
thanks for the comment, as we discussed, the original code use 8 bit byte operation,
while in fact, on some powerpc platform, 32 bit operation is needed. 
should it be possible fixed by adding some wrapper in IO accessors or introduce additional sdhci op?
Please advice more. 
Thanks.
Roy

RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

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DQo=

Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Anton Vorontsov]

Hello,

On Fri, Aug 12, 2011 at 09:44:26AM +0000, Zang Roy-R61911 wrote:
[...]
> > We try to not pollute generic sdhci.c driver with chip-specific
> > quirks.
> > 
> > Maybe you can do the fixups via IO accessors? Or by introducing
> > some additional sdhci op?
> Anton,
> thanks for the comment, as we discussed, the original code use 8 bit byte operation,
> while in fact, on some powerpc platform, 32 bit operation is needed. 
> should it be possible fixed by adding some wrapper in IO accessors or introduce additional sdhci op?

I would do it in the IO accessors.

Thanks,

-- 
Anton Vorontsov
Email: cbouatmailru@gmail.com

Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Anton Vorontsov]

Hello,

On Fri, Aug 12, 2011 at 09:44:26AM +0000, Zang Roy-R61911 wrote:
[...]
> > We try to not pollute generic sdhci.c driver with chip-specific
> > quirks.
> > 
> > Maybe you can do the fixups via IO accessors? Or by introducing
> > some additional sdhci op?
> Anton,
> thanks for the comment, as we discussed, the original code use 8 bit byte operation,
> while in fact, on some powerpc platform, 32 bit operation is needed. 
> should it be possible fixed by adding some wrapper in IO accessors or introduce additional sdhci op?

I would do it in the IO accessors.

Thanks,

-- 
Anton Vorontsov
Email: cbouatmailru@gmail.com

RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

> -----Original Message-----
> From: Anton Vorontsov [mailto:cbouatmailru@gmail.com]
> Sent: Friday, August 12, 2011 18:05 PM
> To: Zang Roy-R61911
> Cc: linux-mmc@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; akpm@linux-
> foundation.org; Xu Lei-B33228; Kumar Gala; Wood Scott-B07421
> Subject: Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc
> 
> Hello,
> 
> On Fri, Aug 12, 2011 at 09:44:26AM +0000, Zang Roy-R61911 wrote:
> [...]
> > > We try to not pollute generic sdhci.c driver with chip-specific
> > > quirks.
> > >
> > > Maybe you can do the fixups via IO accessors? Or by introducing
> > > some additional sdhci op?
> > Anton,
> > thanks for the comment, as we discussed, the original code use 8 bit byte
> operation,
> > while in fact, on some powerpc platform, 32 bit operation is needed.
> > should it be possible fixed by adding some wrapper in IO accessors or
> introduce additional sdhci op?
> 
> I would do it in the IO accessors.
I am looking forward to your patch.
Roy

RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

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IHlvdXIgcGF0Y2guDQpSb3kNCg==

RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

> -----Original Message-----
> From: Anton Vorontsov [mailto:cbouatmailru@gmail.com]
> Sent: Friday, August 12, 2011 18:05 PM
> To: Zang Roy-R61911
> Cc: linux-mmc@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; akpm@linux-
> foundation.org; Xu Lei-B33228; Kumar Gala; Wood Scott-B07421
> Subject: Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc
> 
> Hello,
> 
> On Fri, Aug 12, 2011 at 09:44:26AM +0000, Zang Roy-R61911 wrote:
> [...]
> > > We try to not pollute generic sdhci.c driver with chip-specific
> > > quirks.
> > >
> > > Maybe you can do the fixups via IO accessors? Or by introducing
> > > some additional sdhci op?
> > Anton,
> > thanks for the comment, as we discussed, the original code use 8 bit byte
> operation,
> > while in fact, on some powerpc platform, 32 bit operation is needed.
> > should it be possible fixed by adding some wrapper in IO accessors or
> introduce additional sdhci op?
> 
> I would do it in the IO accessors.
I may miss your email. I never see your patch about " I would do it in the IO accessors ".
Thanks.
Roy

RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

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Y2Vzc29ycyAiLg0KVGhhbmtzLg0KUm95DQoNCg==

RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

> -----Original Message-----
> From: Anton Vorontsov [mailto:cbouatmailru@gmail.com]
> Sent: Friday, August 12, 2011 18:05 PM
> To: Zang Roy-R61911
> Cc: linux-mmc@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; akpm@linux-
> foundation.org; Xu Lei-B33228; Kumar Gala; Wood Scott-B07421
> Subject: Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc
> 
> Hello,
> 
> On Fri, Aug 12, 2011 at 09:44:26AM +0000, Zang Roy-R61911 wrote:
> [...]
> > > We try to not pollute generic sdhci.c driver with chip-specific
> > > quirks.
> > >
> > > Maybe you can do the fixups via IO accessors? Or by introducing
> > > some additional sdhci op?
> > Anton,
> > thanks for the comment, as we discussed, the original code use 8 bit byte
> operation,
> > while in fact, on some powerpc platform, 32 bit operation is needed.
> > should it be possible fixed by adding some wrapper in IO accessors or
> introduce additional sdhci op?
> 
> I would do it in the IO accessors.
> 
> Thanks,
Any update for your comment?
Roy

RE: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Zang Roy-R61911]

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dGUgZm9yIHlvdXIgY29tbWVudD8NClJveQ0K

Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 294 bytes --]

> > I would do it in the IO accessors.
> > 
> > Thanks,
> Any update for your comment?

It is still valid. You can go that road.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[-- Attachment #2: Digital signature --]
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Re: [PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 294 bytes --]

> > I would do it in the IO accessors.
> > 
> > Thanks,
> Any update for your comment?

It is still valid. You can go that road.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[-- Attachment #2: Digital signature --]
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