From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gw1.transmode.se (gw1.transmode.se [195.58.98.146]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4AD5AB73BF for ; Mon, 10 Oct 2011 22:30:40 +1100 (EST) From: Joakim Tjernlund To: linuxppc-dev , Scott Wood , Willy Tarreau , Dan Malek Subject: [PATCH 08/14] 8xx: Add missing Guarded setting in DTLB Error. Date: Mon, 10 Oct 2011 13:30:14 +0200 Message-Id: <1318246220-4839-9-git-send-email-Joakim.Tjernlund@transmode.se> In-Reply-To: <1318246220-4839-1-git-send-email-Joakim.Tjernlund@transmode.se> References: <1318246220-4839-1-git-send-email-Joakim.Tjernlund@transmode.se> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , only DTLB Miss did set this bit, DTLB Error needs too otherwise the setting is lost when the page becomes dirty. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S | 12 +++++++++--- 1 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 367fec0..86bc727 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -573,9 +573,15 @@ DARFixed: ori r21, r21, 1 /* Set valid bit in physical L2 page */ DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 /* Load pte table base address */ - mfspr r21, MD_TWC /* ....and get the pte address */ - lwz r20, 0(r21) /* Get the pte */ - + mfspr r20, MD_TWC /* ....and get the pte address */ + lwz r20, 0(r20) /* Get the pte */ + /* Insert the Guarded flag into the TWC from the Linux PTE. + * It is bit 27 of both the Linux PTE and the TWC + */ + rlwimi r21, r20, 0, 27, 27 + DO_8xx_CPU6(0x3b80, r3) + mtspr MD_TWC, r21 + mfspr r21, MD_TWC /* get the pte address again */ ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE stw r20, 0(r21) /* and update pte in table */ xori r20, r20, _PAGE_RW /* RW bit is inverted */ -- 1.7.3.4