From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Anholt Subject: [PATCH 02/13] intel: Make intel_chipset handle devid directly. Date: Wed, 21 Dec 2011 10:09:32 -0800 Message-ID: <1324490983-6975-3-git-send-email-eric@anholt.net> References: <1324490983-6975-1-git-send-email-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1324490983-6975-1-git-send-email-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This will make these macros reusable from intel_decode.c, which doesn't have a bufmgr_gem context, without faking the struct. We should generally only be using these macros from bufmgr_gem context setup anyway. --- intel/intel_bufmgr_gem.c | 17 ++++++---- intel/intel_chipset.h | 72 +++++++++++++++++++++++----------------------- 2 files changed, 46 insertions(+), 43 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index eb9dd32..2b4fab1 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -284,7 +284,8 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, return ALIGN(pitch, 64); if (*tiling_mode == I915_TILING_X - || (IS_915(bufmgr_gem) && *tiling_mode == I915_TILING_Y)) + || (IS_915(bufmgr_gem->pci_device) + && *tiling_mode == I915_TILING_Y)) tile_width = 512; else tile_width = 128; @@ -772,10 +773,11 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, aligned_y = y; height_alignment = 2; - if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE) + if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE) height_alignment = 16; else if (tiling == I915_TILING_X - || (IS_915(bufmgr_gem) && tiling == I915_TILING_Y)) + || (IS_915(bufmgr_gem->pci_device) + && tiling == I915_TILING_Y)) height_alignment = 8; else if (tiling == I915_TILING_Y) height_alignment = 32; @@ -2313,16 +2315,17 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); } - if (IS_GEN2(bufmgr_gem)) + if (IS_GEN2(bufmgr_gem->pci_device)) bufmgr_gem->gen = 2; - else if (IS_GEN3(bufmgr_gem)) + else if (IS_GEN3(bufmgr_gem->pci_device)) bufmgr_gem->gen = 3; - else if (IS_GEN4(bufmgr_gem)) + else if (IS_GEN4(bufmgr_gem->pci_device)) bufmgr_gem->gen = 4; else bufmgr_gem->gen = 6; - if (IS_GEN3(bufmgr_gem) && bufmgr_gem->gtt_size > 256*1024*1024) { + if (IS_GEN3(bufmgr_gem->pci_device) && + bufmgr_gem->gtt_size > 256*1024*1024) { /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't * be used for tiled blits. To simplify the accounting, just * substract the unmappable part (fixed to 256MB on all known diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index b4e0747..5d417da 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -28,22 +28,22 @@ #ifndef _INTEL_CHIPSET_H #define _INTEL_CHIPSET_H -#define IS_830(dev) ((dev)->pci_device == 0x3577) -#define IS_845(dev) ((dev)->pci_device == 0x2562) -#define IS_85X(dev) ((dev)->pci_device == 0x3582) -#define IS_865(dev) ((dev)->pci_device == 0x2572) +#define IS_830(dev) (dev == 0x3577) +#define IS_845(dev) (dev == 0x2562) +#define IS_85X(dev) (dev == 0x3582) +#define IS_865(dev) (dev == 0x2572) #define IS_GEN2(dev) (IS_830(dev) || \ IS_845(dev) || \ IS_85X(dev) || \ IS_865(dev)) -#define IS_915G(dev) ((dev)->pci_device == 0x2582 || \ - (dev)->pci_device == 0x258a) -#define IS_915GM(dev) ((dev)->pci_device == 0x2592) -#define IS_945G(dev) ((dev)->pci_device == 0x2772) -#define IS_945GM(dev) ((dev)->pci_device == 0x27A2 || \ - (dev)->pci_device == 0x27AE) +#define IS_915G(dev) (dev == 0x2582 || \ + dev == 0x258a) +#define IS_915GM(dev) (dev == 0x2592) +#define IS_945G(dev) (dev == 0x2772) +#define IS_945GM(dev) (dev == 0x27A2 || \ + dev == 0x27AE) #define IS_915(dev) (IS_915G(dev) || \ IS_915GM(dev)) @@ -53,44 +53,44 @@ IS_G33(dev) || \ IS_PINEVIEW(dev)) -#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ - (dev)->pci_device == 0x29B2 || \ - (dev)->pci_device == 0x29D2) +#define IS_G33(dev) (dev == 0x29C2 || \ + dev == 0x29B2 || \ + dev == 0x29D2) -#define IS_PINEVIEW(dev) ((dev)->pci_device == 0xa001 || \ - (dev)->pci_device == 0xa011) +#define IS_PINEVIEW(dev) (dev == 0xa001 || \ + dev == 0xa011) #define IS_GEN3(dev) (IS_915(dev) || \ IS_945(dev) || \ IS_G33(dev) || \ IS_PINEVIEW(dev)) -#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) +#define IS_I965GM(dev) (dev == 0x2A02) -#define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \ - (dev)->pci_device == 0x2982 || \ - (dev)->pci_device == 0x2992 || \ - (dev)->pci_device == 0x29A2 || \ - (dev)->pci_device == 0x2A02 || \ - (dev)->pci_device == 0x2A12 || \ - (dev)->pci_device == 0x2A42 || \ - (dev)->pci_device == 0x2E02 || \ - (dev)->pci_device == 0x2E12 || \ - (dev)->pci_device == 0x2E22 || \ - (dev)->pci_device == 0x2E32 || \ - (dev)->pci_device == 0x2E42 || \ - (dev)->pci_device == 0x0042 || \ - (dev)->pci_device == 0x0046 || \ +#define IS_GEN4(dev) (dev == 0x2972 || \ + dev == 0x2982 || \ + dev == 0x2992 || \ + dev == 0x29A2 || \ + dev == 0x2A02 || \ + dev == 0x2A12 || \ + dev == 0x2A42 || \ + dev == 0x2E02 || \ + dev == 0x2E12 || \ + dev == 0x2E22 || \ + dev == 0x2E32 || \ + dev == 0x2E42 || \ + dev == 0x0042 || \ + dev == 0x0046 || \ IS_I965GM(dev) || \ IS_G4X(dev)) -#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) +#define IS_GM45(dev) (dev == 0x2A42) -#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ - (dev)->pci_device == 0x2E12 || \ - (dev)->pci_device == 0x2E22 || \ - (dev)->pci_device == 0x2E32 || \ - (dev)->pci_device == 0x2E42 || \ +#define IS_G4X(dev) (dev == 0x2E02 || \ + dev == 0x2E12 || \ + dev == 0x2E22 || \ + dev == 0x2E32 || \ + dev == 0x2E42 || \ IS_GM45(dev)) #define IS_9XX(dev) (IS_GEN3(dev) || \ -- 1.7.7.3