From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:57623) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RdnFm-00046J-Ax for qemu-devel@nongnu.org; Thu, 22 Dec 2011 13:20:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RdnFf-0001FU-GC for qemu-devel@nongnu.org; Thu, 22 Dec 2011 13:20:29 -0500 Received: from smtp201.dfw.emailsrvr.com ([67.192.241.201]:42173) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RdnFf-0001FF-BL for qemu-devel@nongnu.org; Thu, 22 Dec 2011 13:20:23 -0500 From: Mark Langsdorf Date: Thu, 22 Dec 2011 12:20:08 -0600 Message-Id: <1324578014-24746-4-git-send-email-mark.langsdorf@calxeda.com> In-Reply-To: <1324578014-24746-1-git-send-email-mark.langsdorf@calxeda.com> References: <1324578014-24746-1-git-send-email-mark.langsdorf@calxeda.com> Subject: [Qemu-devel] [PATCH v2 3/9] arm: add dummy v7 cp15 config_base_register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kwolf@redhat.com, peter.maydell@linaro.org, paul@codesourcery.com, Mark Langsdorf Add a cp15 config_base_register that currently defaults to 0. After the QOM CPU support is added, the value will be properly set to the periphal base value. Signed-off-by: Mark Langsdorf --- Changes from v1 renamed the register added comments about how it will change when QOM CPUs are added target-arm/cpu.h | 1 + target-arm/helper.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c4d742f..449e620 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -149,6 +149,7 @@ typedef struct CPUARMState { uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ uint32_t c15_threadid; /* TI debugger thread-ID. */ + uint32_t c15_config_base_address; /* SCU base address. */ } cp15; struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index 65f4fbf..3899a43 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) * 0x200 << ($rn & 0xfff), when MMU is off. */ goto bad_reg; } + if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) { + switch (crm) { + case 0: + /* The config_base_address should hold the value of + * the peripheral base. ARM should get this from a CPU + * object property, but that support isn't available in + * December 2011. Default to 0 for now and board models + * that care can set it by a private hook */ + if (op1 == 4) { + return env->cp15.c15_config_base_address; + } + } + goto bad_reg; + } return 0; } bad_reg: -- 1.7.5.4