From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:36920) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RmgNY-0000g5-Kj for qemu-devel@nongnu.org; Mon, 16 Jan 2012 01:49:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RmgNW-00067J-Ia for qemu-devel@nongnu.org; Mon, 16 Jan 2012 01:49:16 -0500 Received: from mailout1.w1.samsung.com ([210.118.77.11]:36936) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RmgNW-000678-A1 for qemu-devel@nongnu.org; Mon, 16 Jan 2012 01:49:14 -0500 Received: from euspt1 (mailout1.w1.samsung.com [210.118.77.11]) by mailout1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTP id <0LXV008EVPLZII@mailout1.w1.samsung.com> for qemu-devel@nongnu.org; Mon, 16 Jan 2012 06:49:11 +0000 (GMT) Received: from evvoevodinPC.rnd.samsung.ru ([106.109.8.195]) by spt1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LXV001XLPL2W7@spt1.w1.samsung.com> for qemu-devel@nongnu.org; Mon, 16 Jan 2012 06:49:11 +0000 (GMT) Date: Mon, 16 Jan 2012 10:48:29 +0400 From: Evgeny Voevodin In-reply-to: <1326696515-6747-1-git-send-email-e.voevodin@samsung.com> Message-id: <1326696515-6747-5-git-send-email-e.voevodin@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: QUOTED-PRINTABLE References: <1326696515-6747-1-git-send-email-e.voevodin@samsung.com> Subject: [Qemu-devel] =?utf-8?q?=5BPATCH_v7_04/10=5D_ARM=3A_Samsung_exynos?= =?utf-8?q?4210-based_boards_emulation?= List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kyungmin.park@samsung.com, m.kozlov@samsung.com, jehyung.lee@samsung.com, d.solodkiy@samsung.com, Evgeny Voevodin Add initial support of NURI and SMDKC210 boards Signed-off-by: Evgeny Voevodin --- Makefile.target | 3 +- hw/exynos4210.c | 202 +++++++++++++++++++++++++++++++++++++++++= ++++++++++ hw/exynos4210.h | 37 +++++++++ hw/exynos4_boards.c | 143 ++++++++++++++++++++++++++++++++++++ 4 files changed, 384 insertions(+), 1 deletions(-) create mode 100644 hw/exynos4210.c create mode 100644 hw/exynos4_boards.c diff --git a/Makefile.target b/Makefile.target index 4ac257e..6199d44 100644 --- a/Makefile.target +++ b/Makefile.target @@ -339,7 +339,8 @@ obj-arm-y =3D integratorcp.o versatilepb.o arm_pi= c.o arm_timer.o obj-arm-y +=3D arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl= 181.o pl190.o obj-arm-y +=3D versatile_pci.o obj-arm-y +=3D realview_gic.o realview.o arm_sysctl.o arm11mpcore.o = a9mpcore.o -obj-arm-y +=3D exynos4210_gic.o exynos4210_combiner.o +obj-arm-y +=3D exynos4210_gic.o exynos4210_combiner.o exynos4210.o +obj-arm-y +=3D exynos4_boards.o obj-arm-y +=3D arm_l2x0.o obj-arm-y +=3D arm_mptimer.o obj-arm-y +=3D armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_= enet.o diff --git a/hw/exynos4210.c b/hw/exynos4210.c new file mode 100644 index 0000000..82755db --- /dev/null +++ b/hw/exynos4210.c @@ -0,0 +1,202 @@ +/* + * Samsung exynos4210 SoC emulation + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights rese= rved. + * Maksim Kozlov + * Evgeny Voevodin + * Igor Mitsyanko + * + * This program is free software; you can redistribute it and/or mo= dify it + * under the terms of the GNU General Public License as published b= y the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, = but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILI= TY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public Lic= ense + * for more details. + * + * You should have received a copy of the GNU General Public Licens= e along + * with this program; if not, see . + * + */ + +#include "boards.h" +#include "sysemu.h" +#include "sysbus.h" +#include "arm-misc.h" +#include "exynos4210.h" + +#define EXYNOS4210_CHIPID_ADDR 0x10000000 + +/* External GIC */ +#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 +#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 + +/* Combiner */ +#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 +#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 + +static uint8_t chipid_and_omr[] =3D { 0x11, 0x02, 0x21, 0x43, + 0x09, 0x00, 0x00, 0x00 }; + +Exynos4210State *exynos4210_init(MemoryRegion *system_mem, + unsigned long ram_size) +{ + qemu_irq cpu_irq[4]; + int n; + Exynos4210State *s =3D g_new(Exynos4210State, 1); + qemu_irq *irq_table; + qemu_irq *irqp; + qemu_irq gate_irq[EXYNOS4210_IRQ_GATE_NINPUTS]; + unsigned long mem_size; + DeviceState *dev; + SysBusDevice *busdev; + + for (n =3D 0; n < smp_cpus; n++) { + s->env[n] =3D cpu_init("cortex-a9"); + if (!s->env[n]) { + fprintf(stderr, "Unable to find CPU %d definition\n", n)= ; + exit(1); + } + /* Create PIC controller for each processor instance */ + irqp =3D arm_pic_init_cpu(s->env[n]); + + /* + * Get GICs gpio_in cpu_irq to connect a combiner to them la= ter. + * Use only IRQ for a while. + */ + cpu_irq[n] =3D irqp[ARM_PIC_CPU_IRQ]; + } + + /*** IRQs ***/ + + s->irq_table =3D exynos4210_init_irq(&s->irqs); + irq_table =3D s->irq_table; + + /* IRQ Gate */ + dev =3D qdev_create(NULL, "exynos4210.irq_gate"); + qdev_init_nofail(dev); + /* Get IRQ Gate input in gate_irq */ + for (n =3D 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { + gate_irq[n] =3D qdev_get_gpio_in(dev, n); + } + busdev =3D sysbus_from_qdev(dev); + /* Connect IRQ Gate output to cpu_irq */ + for (n =3D 0; n < smp_cpus; n++) { + sysbus_connect_irq(busdev, n, cpu_irq[n]); + } + + /* Private memory region and Internal GIC */ + dev =3D qdev_create(NULL, "a9mpcore_priv"); + qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_init_nofail(dev); + busdev =3D sysbus_from_qdev(dev); + sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); + for (n =3D 0; n < smp_cpus; n++) { + sysbus_connect_irq(busdev, n, gate_irq[n * 2]); + } + for (n =3D 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { + s->irqs.int_gic_irq[n] =3D qdev_get_gpio_in(dev, n); + } + + /* External GIC */ + dev =3D qdev_create(NULL, "exynos4210.gic"); + qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_init_nofail(dev); + busdev =3D sysbus_from_qdev(dev); + /* Map CPU interface */ + sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); + /* Map Distributer interface */ + sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); + for (n =3D 0; n < smp_cpus; n++) { + sysbus_connect_irq(busdev, n, gate_irq[n * 2 + 1]); + } + for (n =3D 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { + s->irqs.ext_gic_irq[n] =3D qdev_get_gpio_in(dev, n); + } + + /* Internal Interrupt Combiner */ + dev =3D qdev_create(NULL, "exynos4210.combiner"); + qdev_init_nofail(dev); + busdev =3D sysbus_from_qdev(dev); + for (n =3D 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { + sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); + } + exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); + sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); + + /* External Interrupt Combiner */ + dev =3D qdev_create(NULL, "exynos4210.combiner"); + qdev_init_nofail(dev); + busdev =3D sysbus_from_qdev(dev); + for (n =3D 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { + sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); + } + exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); + sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); + qdev_prop_set_uint32(dev, "external", 1); + + /* Initialize board IRQs. */ + exynos4210_init_board_irqs(&s->irqs); + + /*** Memory ***/ + + /* Chip-ID and OMR */ + memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid", + sizeof(chipid_and_omr), chipid_and_omr); + memory_region_set_readonly(&s->chipid_mem, true); + memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, + &s->chipid_mem); + + /* Internal ROM */ + memory_region_init_ram(&s->irom_mem, "exynos4210.irom", + EXYNOS4210_IROM_SIZE); + memory_region_set_readonly(&s->irom_mem, true); + memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADD= R, + &s->irom_mem); + /* mirror of 0x0 =E2=80=93 0x10000 */ + memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_al= ias", + &s->irom_mem, 0, EXYNOS4210_IROM_SIZE); + memory_region_set_readonly(&s->irom_alias_mem, true); + memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_B= ASE_ADDR, + &s->irom_alias_mem); + + /* Internal RAM */ + memory_region_init_ram(&s->iram_mem, "exynos4210.iram", + EXYNOS4210_IRAM_SIZE); + vmstate_register_ram_global(&s->iram_mem); + memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADD= R, + &s->iram_mem); + + /* DRAM */ + mem_size =3D ram_size; + if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { + memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1", + mem_size - EXYNOS4210_DRAM_MAX_SIZE); + vmstate_register_ram_global(&s->dram1_mem); + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BAS= E_ADDR, + &s->dram1_mem); + mem_size =3D EXYNOS4210_DRAM_MAX_SIZE; + } + memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_si= ze); + vmstate_register_ram_global(&s->dram0_mem); + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_AD= DR, + &s->dram0_mem); + + /* + * Secondary CPU startup code will be placed here. + */ + memory_region_init_ram(&s->hack_mem, "exynos4210.hack", 0x1000); + memory_region_add_subregion(system_mem, EXYNOS4210_SMP_BOOT_ADDR= , + &s->hack_mem); + + /* + * Hack: Map SECOND_CPU_BOOTREG, because it is in PMU USER5 regi= ster. + */ + memory_region_init_ram(&s->bootreg_mem, "exynos4210.bootreg", 0x= 4); + memory_region_add_subregion(system_mem, EXYNOS4210_SECOND_CPU_BO= OTREG, + &s->bootreg_mem); + + return s; +} diff --git a/hw/exynos4210.h b/hw/exynos4210.h index cef264b..a68900d 100644 --- a/hw/exynos4210.h +++ b/hw/exynos4210.h @@ -31,6 +31,25 @@ =20 #define EXYNOS4210_MAX_CPUS 2 =20 +#define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000 +#define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000 +#define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */ + +#define EXYNOS4210_IROM_BASE_ADDR 0x00000000 +#define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */ +#define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000 +#define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */ + +#define EXYNOS4210_IRAM_BASE_ADDR 0x02020000 +#define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */ + +/* Secondary CPU startup code is in IROM memory */ +#define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADD= R +#define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_AD= DR +/* Secondary CPU polling address to get loader start from */ +#define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814 +#define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000 + /* * exynos4210 IRQ subsystem stub definitions. */ @@ -60,6 +79,24 @@ typedef struct Exynos4210Irq { qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; } Exynos4210Irq; =20 +typedef struct Exynos4210State { + CPUState * env[EXYNOS4210_MAX_CPUS]; + Exynos4210Irq irqs; + qemu_irq *irq_table; + + MemoryRegion chipid_mem; + MemoryRegion iram_mem; + MemoryRegion irom_mem; + MemoryRegion irom_alias_mem; + MemoryRegion dram0_mem; + MemoryRegion dram1_mem; + MemoryRegion hack_mem; + MemoryRegion bootreg_mem; +} Exynos4210State; + +Exynos4210State *exynos4210_init(MemoryRegion *system_mem, + unsigned long ram_size); + /* Initialize exynos4210 IRQ subsystem stub */ qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); =20 diff --git a/hw/exynos4_boards.c b/hw/exynos4_boards.c new file mode 100644 index 0000000..b8fc5b6 --- /dev/null +++ b/hw/exynos4_boards.c @@ -0,0 +1,143 @@ +/* + * Samsung exynos4 SoC based boards emulation + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights rese= rved. + * Maksim Kozlov + * Evgeny Voevodin + * Igor Mitsyanko + * + * This program is free software; you can redistribute it and/or mo= dify it + * under the terms of the GNU General Public License as published b= y the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, = but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILI= TY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public Lic= ense + * for more details. + * + * You should have received a copy of the GNU General Public Licens= e along + * with this program; if not, see . + * + */ + +#include "sysemu.h" +#include "sysbus.h" +#include "arm-misc.h" +#include "exec-memory.h" +#include "exynos4210.h" +#include "boards.h" + +#undef DEBUG + +//#define DEBUG + +#ifdef DEBUG + #undef PRINT_DEBUG + #define PRINT_DEBUG(fmt, args...) \ + do { \ + fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, #= #args); \ + } while (0) +#else + #define PRINT_DEBUG(fmt, args...) do {} while (0) +#endif + +typedef enum exynos4_board_type { + EXYNOS4_BOARD_NURI, + EXYNOS4_BOARD_SMDKC210, + EXYNOS4_NUM_OF_BOARDS +} exynos4_board_type; + +static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] =3D { + [EXYNOS4_BOARD_NURI] =3D 0xD33, + [EXYNOS4_BOARD_SMDKC210] =3D 0xB16, +}; + +static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = =3D { + [EXYNOS4_BOARD_NURI] =3D EXYNOS4210_SECOND_CPU_BOOTREG, + [EXYNOS4_BOARD_SMDKC210] =3D EXYNOS4210_SECOND_CPU_BOOTREG, +}; + +static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = =3D { + [EXYNOS4_BOARD_NURI] =3D 0x40000000, + [EXYNOS4_BOARD_SMDKC210] =3D 0x40000000, +}; + +static struct arm_boot_info exynos4_board_binfo =3D { + .loader_start =3D EXYNOS4210_BASE_BOOT_ADDR, + .smp_loader_start =3D EXYNOS4210_SMP_BOOT_ADDR, +}; + +static Exynos4210State *exynos4_boards_init_common( + const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename, + exynos4_board_type board_type) +{ + exynos4_board_binfo.ram_size =3D exynos4_board_ram_size[board_ty= pe]; + exynos4_board_binfo.board_id =3D exynos4_board_id[board_type]; + exynos4_board_binfo.smp_bootreg_addr =3D + exynos4_board_smp_bootreg_addr[board_type]; + exynos4_board_binfo.nb_cpus =3D smp_cpus; + exynos4_board_binfo.kernel_filename =3D kernel_filename; + exynos4_board_binfo.initrd_filename =3D initrd_filename; + exynos4_board_binfo.kernel_cmdline =3D kernel_cmdline; + exynos4_board_binfo.smp_priv_base =3D EXYNOS4210_SMP_PRIVATE_BAS= E_ADDR; + + PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n" + " kernel_filename: %s\n" + " kernel_cmdline: %s\n" + " initrd_filename: %s\n", + exynos4_board_ram_size[board_type]/1048576, + exynos4_board_ram_size[board_type], + kernel_filename, + kernel_cmdline, + initrd_filename); + + return exynos4210_init(get_system_memory(), + exynos4_board_ram_size[board_type]); +} + +static void nuri_init(ram_addr_t ram_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + exynos4_boards_init_common(kernel_filename, kernel_cmdline, + initrd_filename, EXYNOS4_BOARD_NURI); + + arm_load_kernel(first_cpu, &exynos4_board_binfo); +} + +static void smdkc210_init(ram_addr_t ram_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + exynos4_boards_init_common(kernel_filename, kernel_cmdline, + initrd_filename, EXYNOS4_BOARD_SMDKC210); + + arm_load_kernel(first_cpu, &exynos4_board_binfo); +} + +static QEMUMachine nuri_machine =3D { + .name =3D "nuri", + .desc =3D "Samsung NURI board (Exynos4210)", + .init =3D nuri_init, + .max_cpus =3D EXYNOS4210_MAX_CPUS, +}; + +static QEMUMachine smdkc210_machine =3D { + .name =3D "smdkc210", + .desc =3D "Samsung SMDKC210 board (Exynos4210)", + .init =3D smdkc210_init, + .max_cpus =3D EXYNOS4210_MAX_CPUS, +}; + +static void exynos4_machine_init(void) +{ + qemu_register_machine(&nuri_machine); + qemu_register_machine(&smdkc210_machine); +} + +machine_init(exynos4_machine_init); --=20 1.7.4.1