From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:38864) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rt9QA-00007b-7F for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rt9Px-00062x-6l for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:42 -0500 Received: from cantor2.suse.de ([195.135.220.15]:55632 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rt9Pw-00062W-Mk for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:29 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 3 Feb 2012 03:59:41 +0100 Message-Id: <1328237992-14953-11-git-send-email-afaerber@suse.de> In-Reply-To: <1328237992-14953-1-git-send-email-afaerber@suse.de> References: <1328237992-14953-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v3 10/21] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= For now set them in the reset function. Signed-off-by: Andreas F=C3=A4rber Cc: Peter Maydell --- target-arm/cpu-core.h | 2 + target-arm/cpu.c | 64 +++++++++++++++++++++++++++++++++++++++++++= ++++++ target-arm/helper.c | 51 --------------------------------------- 3 files changed, 66 insertions(+), 51 deletions(-) diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h index 9f090a8..bb59f8d 100644 --- a/target-arm/cpu-core.h +++ b/target-arm/cpu-core.h @@ -43,6 +43,8 @@ typedef struct ARMCPUClass { =20 struct { uint32_t c0_cpuid; + uint32_t c0_c1[8]; + uint32_t c0_c2[8]; } cp15; =20 /* Internal CPU feature flags. */ diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 07cbfe6..909eb1a 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -27,6 +27,7 @@ static void arm_cpu_reset(CPU *c) { ARMCPU *cpu =3D ARM_CPU(c); + ARMCPUClass *cpu_class =3D ARM_CPU_GET_CLASS(cpu); CPUARMState *env =3D &cpu->env; uint32_t id; uint32_t tmp; @@ -44,6 +45,10 @@ static void arm_cpu_reset(CPU *c) env->cp15.c0_cpuid =3D id; env->cp15.c15_config_base_address =3D tmp; =20 + /* TODO Move these into arm_cpu_initfn() once no longer zeroed above= . */ + memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t))= ; + memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t))= ; + #if defined(CONFIG_USER_ONLY) env->uncached_cpsr =3D ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */ @@ -159,6 +164,8 @@ static inline void unset_class_feature(ARMCPUClass *k= lass, int feature) typedef struct ARMCPUInfo { const char *name; uint32_t id; + uint32_t cp15_c0_c1[8]; + uint32_t cp15_c0_c2[8]; uint32_t features; void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info= ); } ARMCPUInfo; @@ -171,6 +178,13 @@ static void arm1136_r0_class_init(ARMCPUClass *k, co= nst ARMCPUInfo *info) =20 k->features =3D r1_class->features; unset_class_feature(k, ARM_FEATURE_V6K); + + /* These ID register values are correct for 1136 but may be wrong + * for 1136_r2 (in particular r0p2 does not actually implement most + * of the ID registers). + */ + memcpy(k->cp15.c0_c1, r1_class->cp15.c0_c1, 8 * sizeof(uint32_t)); + memcpy(k->cp15.c0_c2, r1_class->cp15.c0_c2, 8 * sizeof(uint32_t)); } =20 static void ti925t_reset(CPU *c) @@ -240,12 +254,28 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm1136", .id =3D 0x4117b363, + .cp15_c0_c1 =3D { + 0x111, 0x1, 0x2, 0x3, + 0x01130003, 0x10030302, 0x01222110, 0 + }, + .cp15_c0_c2 =3D { + 0x00140011, 0x12002111, 0x11231111, 0x01102131, + 0x141, 0, 0, 0 + }, .features =3D ARM_FEATURE(V6) | ARM_FEATURE(VFP), }, { .name =3D "arm1176", .id =3D 0x410fb767, + .cp15_c0_c1 =3D { + 0x111, 0x11, 0x33, 0, + 0x01130003, 0x10030302, 0x01222100, 0 + }, + .cp15_c0_c2 =3D { + 0x0140011, 0x12002111, 0x11231121, 0x01102131, + 0x01141, 0, 0, 0 + }, .features =3D ARM_FEATURE(V6K) | ARM_FEATURE(VFP) | ARM_FEATURE(VAPA), @@ -253,6 +283,14 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm11mpcore", .id =3D 0x410fb022, + .cp15_c0_c1 =3D { + 0x111, 0x1, 0, 0x2, + 0x01100103, 0x10020302, 0x01222000, 0 + }, + .cp15_c0_c2 =3D { + 0x00100011, 0x12002111, 0x11221011, 0x01102131, + 0x141, 0, 0, 0 + }, .features =3D ARM_FEATURE(V6K) | ARM_FEATURE(VFP) | ARM_FEATURE(VAPA), @@ -266,6 +304,14 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "cortex-a8", .id =3D 0x410fc080, + .cp15_c0_c1 =3D { + 0x1031, 0x11, 0x400, 0, + 0x31100003, 0x20000000, 0x01202000, 0x11 + }, + .cp15_c0_c2 =3D { + 0x00101111, 0x12112111, 0x21232031, 0x11112131, + 0x00111142, 0, 0, 0 + }, .features =3D ARM_FEATURE(V7) | ARM_FEATURE(VFP3) | ARM_FEATURE(NEON) | @@ -274,6 +320,14 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "cortex-a9", .id =3D 0x410fc090, + .cp15_c0_c1 =3D { + 0x1031, 0x11, 0x000, 0, + 0x00100103, 0x20000000, 0x01230000, 0x00002111 + }, + .cp15_c0_c2 =3D { + 0x00101111, 0x13112111, 0x21232041, 0x11112131, + 0x00111142, 0, 0, 0 + }, .features =3D ARM_FEATURE(V7) | ARM_FEATURE(VFP3) | ARM_FEATURE(VFP_FP16) | @@ -288,6 +342,14 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "cortex-a15", .id =3D 0x412fc0f1, + .cp15_c0_c1 =3D { + 0x00001131, 0x00011011, 0x02010555, 0x00000000, + 0x10201105, 0x20000000, 0x01240000, 0x02102211 + }, + .cp15_c0_c2 =3D { + 0x02101110, 0x13112111, 0x21232041, 0x11112131, + 0x10011142, 0, 0, 0 + }, .features =3D ARM_FEATURE(V7) | ARM_FEATURE(VFP4) | ARM_FEATURE(VFP_FP16) | @@ -405,6 +467,8 @@ static void arm_cpu_class_init(ObjectClass *klass, vo= id *data) cpu_class->reset =3D arm_cpu_reset; =20 k->cp15.c0_cpuid =3D info->id; + memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t)); + memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t)); k->features =3D info->features; =20 if (info->class_init !=3D NULL) { diff --git a/target-arm/helper.c b/target-arm/helper.c index 67e18cc..2af8df4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -10,45 +10,6 @@ #include "sysemu.h" #include "cpu-core.h" =20 -static uint32_t cortexa15_cp15_c0_c1[8] =3D { - 0x00001131, 0x00011011, 0x02010555, 0x00000000, - 0x10201105, 0x20000000, 0x01240000, 0x02102211 -}; - -static uint32_t cortexa15_cp15_c0_c2[8] =3D { - 0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0 -}; - -static uint32_t cortexa9_cp15_c0_c1[8] =3D -{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111= }; - -static uint32_t cortexa9_cp15_c0_c2[8] =3D -{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 }; - -static uint32_t cortexa8_cp15_c0_c1[8] =3D -{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 }; - -static uint32_t cortexa8_cp15_c0_c2[8] =3D -{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 }; - -static uint32_t mpcore_cp15_c0_c1[8] =3D -{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 }; - -static uint32_t mpcore_cp15_c0_c2[8] =3D -{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 }; - -static uint32_t arm1136_cp15_c0_c1[8] =3D -{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 }; - -static uint32_t arm1136_cp15_c0_c2[8] =3D -{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 }; - -static uint32_t arm1176_cp15_c0_c1[8] =3D -{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 }; - -static uint32_t arm1176_cp15_c0_c2[8] =3D -{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 }; - static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { @@ -81,8 +42,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32= _t id) env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x00000000; - memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)= ); - memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)= ); env->cp15.c0_cachetype =3D 0x1dd20d2; env->cp15.c1_sys =3D 0x00050078; break; @@ -90,8 +49,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32= _t id) env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x00000000; - memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)= ); - memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)= ); env->cp15.c0_cachetype =3D 0x1dd20d2; env->cp15.c1_sys =3D 0x00050078; break; @@ -99,16 +56,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint= 32_t id) env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x00000000; - memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t))= ; - memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t))= ; env->cp15.c0_cachetype =3D 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410330c0; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x00011100; - memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t= )); - memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t= )); env->cp15.c0_cachetype =3D 0x82048004; env->cp15.c0_clid =3D (1 << 27) | (2 << 24) | 3; env->cp15.c0_ccsid[0] =3D 0xe007e01a; /* 16k L1 dcache. */ @@ -120,8 +73,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint3= 2_t id) env->vfp.xregs[ARM_VFP_FPSID] =3D 0x41034000; /* Guess */ env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x01111111; - memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t= )); - memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t= )); env->cp15.c0_cachetype =3D 0x80038003; env->cp15.c0_clid =3D (1 << 27) | (1 << 24) | 3; env->cp15.c0_ccsid[0] =3D 0xe00fe015; /* 16k L1 dcache. */ @@ -132,8 +83,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint3= 2_t id) env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410430f0; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x10110222; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x11111111; - memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_= t)); - memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_= t)); env->cp15.c0_cachetype =3D 0x8444c004; env->cp15.c0_clid =3D 0x0a200023; env->cp15.c0_ccsid[0] =3D 0x701fe00a; /* 32K L1 dcache */ --=20 1.7.7