From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:38772) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rt9Q4-0008GQ-6N for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rt9Py-00063V-G1 for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:35 -0500 Received: from cantor2.suse.de ([195.135.220.15]:55639 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rt9Py-00063C-4V for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:30 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 3 Feb 2012 03:59:44 +0100 Message-Id: <1328237992-14953-14-git-send-email-afaerber@suse.de> In-Reply-To: <1328237992-14953-1-git-send-email-afaerber@suse.de> References: <1328237992-14953-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= That way we can remove some more CPUID cases without losing info. Signed-off-by: Andreas F=C3=A4rber Cc: Peter Maydell Cc: Andrzej Zaborowski --- target-arm/cpu-core.h | 1 + target-arm/cpu.c | 2 ++ target-arm/cpu.h | 5 ----- target-arm/helper.c | 8 -------- 4 files changed, 3 insertions(+), 13 deletions(-) diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h index 3e7dfae..eac1a03 100644 --- a/target-arm/cpu-core.h +++ b/target-arm/cpu-core.h @@ -48,6 +48,7 @@ typedef struct ARMCPUClass { uint32_t c0_c2[8]; uint32_t c1_sys; } cp15; + uint64_t jtag_id; =20 /* Internal CPU feature flags. */ uint32_t features; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 2c1e1a6..7d4f0f6 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -223,6 +223,7 @@ static void pxa25x_class_init(ARMCPUClass *k, const A= RMCPUInfo *info) { k->cp15.c0_cachetype =3D 0xd172172; k->cp15.c1_sys =3D 0x00000078; + k->jtag_id =3D ((uint64_t)k->cp15.c0_cpuid << 28) | 0x09265013; =20 set_class_feature(k, ARM_FEATURE_V5); set_class_feature(k, ARM_FEATURE_XSCALE); @@ -232,6 +233,7 @@ static void pxa270_class_init(ARMCPUClass *k, const A= RMCPUInfo *info) { k->cp15.c0_cachetype =3D 0xd172172; k->cp15.c1_sys =3D 0x00000078; + k->jtag_id =3D ((uint64_t)k->cp15.c0_cpuid << 28) | 0x09265013; =20 set_class_feature(k, ARM_FEATURE_V5); set_class_feature(k, ARM_FEATURE_XSCALE); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e16befd..351b057 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -406,11 +406,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_ARM926 0x41069265 #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 -#define ARM_CPUID_PXA250 0x69052100 -#define ARM_CPUID_PXA255 0x69052d00 -#define ARM_CPUID_PXA260 0x69052903 -#define ARM_CPUID_PXA261 0x69052d05 -#define ARM_CPUID_PXA262 0x69052d06 #define ARM_CPUID_PXA270_A0 0x69054110 #define ARM_CPUID_PXA270_A1 0x69054111 #define ARM_CPUID_PXA270_B0 0x69054112 diff --git a/target-arm/helper.c b/target-arm/helper.c index 32319e4..bf28fea 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -76,20 +76,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint= 32_t id) env->cp15.c15_i_max =3D 0x000; env->cp15.c15_i_min =3D 0xff0; break; - case ARM_CPUID_PXA250: - case ARM_CPUID_PXA255: - case ARM_CPUID_PXA260: - case ARM_CPUID_PXA261: - case ARM_CPUID_PXA262: - /* JTAG_ID is ((id << 28) | 0x09265013) */ - break; case ARM_CPUID_PXA270_A0: case ARM_CPUID_PXA270_A1: case ARM_CPUID_PXA270_B0: case ARM_CPUID_PXA270_B1: case ARM_CPUID_PXA270_C0: case ARM_CPUID_PXA270_C5: - /* JTAG_ID is ((id << 28) | 0x09265013) */ env->iwmmxt.cregs[ARM_IWMMXT_wCID] =3D 0x69051000 | 'Q'; break; default: --=20 1.7.7