From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:38839) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rt9Q8-0008T4-AU for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rt9Q1-00064c-FX for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:40 -0500 Received: from cantor2.suse.de ([195.135.220.15]:55651 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rt9Q0-000643-Kk for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:32 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 3 Feb 2012 03:59:49 +0100 Message-Id: <1328237992-14953-19-git-send-email-afaerber@suse.de> In-Reply-To: <1328237992-14953-1-git-send-email-afaerber@suse.de> References: <1328237992-14953-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v3 18/21] target-arm: Store CCSIDRs in ARMCPUClass List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= Signed-off-by: Andreas F=C3=A4rber Cc: Peter Maydell --- target-arm/cpu-core.h | 1 + target-arm/cpu.c | 18 ++++++++++++++++++ target-arm/helper.c | 14 -------------- 3 files changed, 19 insertions(+), 14 deletions(-) diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h index 0ed92ce..a58e62b 100644 --- a/target-arm/cpu-core.h +++ b/target-arm/cpu-core.h @@ -44,6 +44,7 @@ typedef struct ARMCPUClass { struct { uint32_t c0_cpuid; uint32_t c0_cachetype; + uint32_t c0_ccsid[16]; uint32_t c0_clid; uint32_t c0_c1[8]; uint32_t c0_c2[8]; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8333ca4..8186a96 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -47,6 +47,8 @@ static void arm_cpu_reset(CPU *c) =20 /* TODO Move these into arm_cpu_initfn() once no longer zeroed above= . */ env->cp15.c0_cachetype =3D cpu_class->cp15.c0_cachetype; + memcpy(env->cp15.c0_ccsid, cpu_class->cp15.c0_ccsid, + 16 * sizeof(uint32_t)); env->cp15.c0_clid =3D cpu_class->cp15.c0_clid; memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t))= ; memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t))= ; @@ -173,6 +175,7 @@ typedef struct ARMCPUInfo { const char *name; uint32_t id; uint32_t cp15_c0_cachetype; + uint32_t cp15_c0_ccsid[16]; uint32_t cp15_c0_clid; uint32_t cp15_c0_c1[8]; uint32_t cp15_c0_c2[8]; @@ -363,6 +366,11 @@ static const ARMCPUInfo arm_cpus[] =3D { .name =3D "cortex-a8", .id =3D 0x410fc080, .cp15_c0_cachetype =3D 0x82048004, + .cp15_c0_ccsid =3D { + 0xe007e01a, /* 16k L1 dcache. */ + 0x2007e01a, /* 16k L1 icache. */ + 0xf0000000, /* No L2 icache. */ + }, .cp15_c0_clid =3D (1 << 27) | (2 << 24) | 3, .cp15_c0_c1 =3D { 0x1031, 0x11, 0x400, 0, @@ -384,6 +392,10 @@ static const ARMCPUInfo arm_cpus[] =3D { .name =3D "cortex-a9", .id =3D 0x410fc090, .cp15_c0_cachetype =3D 0x80038003, + .cp15_c0_ccsid =3D { + 0xe00fe015, /* 16k L1 dcache. */ + 0x200fe015, /* 16k L1 icache. */ + }, .cp15_c0_clid =3D (1 << 27) | (1 << 24) | 3, .cp15_c0_c1 =3D { 0x1031, 0x11, 0x000, 0, @@ -411,6 +423,11 @@ static const ARMCPUInfo arm_cpus[] =3D { .name =3D "cortex-a15", .id =3D 0x412fc0f1, .cp15_c0_cachetype =3D 0x8444c004, + .cp15_c0_ccsid =3D { + 0x701fe00a, /* 32K L1 dcache */ + 0x201fe00a, /* 32K L1 icache */ + 0x711fe07a, /* 4096K L2 unified cache */ + }, .cp15_c0_clid =3D 0x0a200023, .cp15_c0_c1 =3D { 0x00001131, 0x00011011, 0x02010555, 0x00000000, @@ -543,6 +560,7 @@ static void arm_cpu_class_init(ObjectClass *klass, vo= id *data) =20 k->cp15.c0_cpuid =3D info->id; k->cp15.c0_cachetype =3D info->cp15_c0_cachetype; + memcpy(k->cp15.c0_ccsid, info->cp15_c0_ccsid, 16 * sizeof(uint32_t))= ; k->cp15.c0_clid =3D info->cp15_c0_clid; memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t)); diff --git a/target-arm/helper.c b/target-arm/helper.c index 6f2c9a0..6ecae15 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -13,20 +13,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { - case ARM_CPUID_CORTEXA8: - env->cp15.c0_ccsid[0] =3D 0xe007e01a; /* 16k L1 dcache. */ - env->cp15.c0_ccsid[1] =3D 0x2007e01a; /* 16k L1 icache. */ - env->cp15.c0_ccsid[2] =3D 0xf0000000; /* No L2 icache. */ - break; - case ARM_CPUID_CORTEXA9: - env->cp15.c0_ccsid[0] =3D 0xe00fe015; /* 16k L1 dcache. */ - env->cp15.c0_ccsid[1] =3D 0x200fe015; /* 16k L1 icache. */ - break; - case ARM_CPUID_CORTEXA15: - env->cp15.c0_ccsid[0] =3D 0x701fe00a; /* 32K L1 dcache */ - env->cp15.c0_ccsid[1] =3D 0x201fe00a; /* 32K L1 icache */ - env->cp15.c0_ccsid[2] =3D 0x711fe07a; /* 4096K L2 unified cache = */ - break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: env->cp15.c15_i_max =3D 0x000; --=20 1.7.7