From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1033236AbdAEULj (ORCPT ); Thu, 5 Jan 2017 15:11:39 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:43564 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936673AbdAEULV (ORCPT ); Thu, 5 Jan 2017 15:11:21 -0500 From: Chris Packham To: Mark Rutland CC: "linux-arm-kernel@lists.infradead.org" , Rob Herring , Jason Cooper , Andrew Lunn , "Gregory Clement" , Sebastian Hesselbarth , Russell King , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCHv2 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs Thread-Topic: [PATCHv2 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs Thread-Index: AQHSZwU4HzqBikd6B0KfgJY+fjBS2w== Date: Thu, 5 Jan 2017 20:10:34 +0000 Message-ID: <13295ed8de3442daa373d1f39ea8b5a5@svr-chch-ex1.atlnz.lc> References: <20170105033641.6212-1-chris.packham@alliedtelesis.co.nz> <20170105033641.6212-5-chris.packham@alliedtelesis.co.nz> <20170105135837.GC25333@leverpostej> Accept-Language: en-NZ, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [2001:df5:b000:22:c9e4:18f2:c42d:16f] Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v05KBiFG022411 On 06/01/17 02:59, Mark Rutland wrote: > On Thu, Jan 05, 2017 at 04:36:40PM +1300, Chris Packham wrote: >> + internal-regs { >> + coreclk: mvebu-sar@18230 { >> + compatible = "marvell,mv98dx3236-core-clock"; >> + }; >> + >> + cpuclk: clock-complex@18700 { >> + compatible = "marvell,mv98dx3236-cpu-clock"; >> + }; >> + >> + corediv-clock@18740 { >> + compatible = "marvell,mv98dx3236-corediv-clock"; >> + reg = <0xf8268 0xc>; >> + base = <&dfx>; >> + #clock-cells = <1>; >> + clocks = <&mainpll>; >> + clock-output-names = "nand"; >> + }; > > [...] > >> + }; >> + >> + dfx-registers { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; >> + >> + dfx: dfx@0 { >> + compatible = "simple-bus"; >> + reg = <0 0x100000>; >> + }; >> + }; > > What is this dfx-registers, exactly? I've been trying to get that info out of Marvell for a while I'm not even sure what the "DFX" acronym stands for. The Armdada 38x also has a thing called "DFX" but it seems to be quite different to this one. From what I can tell it contains common elements used by both the CPU and switch chip so there are things related to clocking and IO pad configuration. It is necessary for both the switch and CPU to have a handle to access it. > It has no children, so why is it a > simple-bus? > > From the above, and the patch adding the corediv driver, it looks like > the corediv-clock actually lives in this block, so I don't understand > why the corediv-clock is sitting in internal-regs with a sideband > reference to dfx. Yeah I think the corediv-clock should be a child of this node. I'll move it there. > > Thanks, > Mark. > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Packham Subject: Re: [PATCHv2 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs Date: Thu, 5 Jan 2017 20:10:34 +0000 Message-ID: <13295ed8de3442daa373d1f39ea8b5a5@svr-chch-ex1.atlnz.lc> References: <20170105033641.6212-1-chris.packham@alliedtelesis.co.nz> <20170105033641.6212-5-chris.packham@alliedtelesis.co.nz> <20170105135837.GC25333@leverpostej> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Mark Rutland Cc: Andrew Lunn , Jason Cooper , "devicetree@vger.kernel.org" , Russell King , "linux-kernel@vger.kernel.org" , Rob Herring , Gregory Clement , "linux-arm-kernel@lists.infradead.org" , Sebastian Hesselbarth List-Id: devicetree@vger.kernel.org On 06/01/17 02:59, Mark Rutland wrote: > On Thu, Jan 05, 2017 at 04:36:40PM +1300, Chris Packham wrote: >> + internal-regs { >> + coreclk: mvebu-sar@18230 { >> + compatible = "marvell,mv98dx3236-core-clock"; >> + }; >> + >> + cpuclk: clock-complex@18700 { >> + compatible = "marvell,mv98dx3236-cpu-clock"; >> + }; >> + >> + corediv-clock@18740 { >> + compatible = "marvell,mv98dx3236-corediv-clock"; >> + reg = <0xf8268 0xc>; >> + base = <&dfx>; >> + #clock-cells = <1>; >> + clocks = <&mainpll>; >> + clock-output-names = "nand"; >> + }; > > [...] > >> + }; >> + >> + dfx-registers { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; >> + >> + dfx: dfx@0 { >> + compatible = "simple-bus"; >> + reg = <0 0x100000>; >> + }; >> + }; > > What is this dfx-registers, exactly? I've been trying to get that info out of Marvell for a while I'm not even sure what the "DFX" acronym stands for. The Armdada 38x also has a thing called "DFX" but it seems to be quite different to this one. From what I can tell it contains common elements used by both the CPU and switch chip so there are things related to clocking and IO pad configuration. It is necessary for both the switch and CPU to have a handle to access it. > It has no children, so why is it a > simple-bus? > > From the above, and the patch adding the corediv driver, it looks like > the corediv-clock actually lives in this block, so I don't understand > why the corediv-clock is sitting in internal-regs with a sideband > reference to dfx. Yeah I think the corediv-clock should be a child of this node. I'll move it there. > > Thanks, > Mark. > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris.Packham@alliedtelesis.co.nz (Chris Packham) Date: Thu, 5 Jan 2017 20:10:34 +0000 Subject: [PATCHv2 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs References: <20170105033641.6212-1-chris.packham@alliedtelesis.co.nz> <20170105033641.6212-5-chris.packham@alliedtelesis.co.nz> <20170105135837.GC25333@leverpostej> Message-ID: <13295ed8de3442daa373d1f39ea8b5a5@svr-chch-ex1.atlnz.lc> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 06/01/17 02:59, Mark Rutland wrote: > On Thu, Jan 05, 2017 at 04:36:40PM +1300, Chris Packham wrote: >> + internal-regs { >> + coreclk: mvebu-sar at 18230 { >> + compatible = "marvell,mv98dx3236-core-clock"; >> + }; >> + >> + cpuclk: clock-complex at 18700 { >> + compatible = "marvell,mv98dx3236-cpu-clock"; >> + }; >> + >> + corediv-clock at 18740 { >> + compatible = "marvell,mv98dx3236-corediv-clock"; >> + reg = <0xf8268 0xc>; >> + base = <&dfx>; >> + #clock-cells = <1>; >> + clocks = <&mainpll>; >> + clock-output-names = "nand"; >> + }; > > [...] > >> + }; >> + >> + dfx-registers { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; >> + >> + dfx: dfx at 0 { >> + compatible = "simple-bus"; >> + reg = <0 0x100000>; >> + }; >> + }; > > What is this dfx-registers, exactly? I've been trying to get that info out of Marvell for a while I'm not even sure what the "DFX" acronym stands for. The Armdada 38x also has a thing called "DFX" but it seems to be quite different to this one. From what I can tell it contains common elements used by both the CPU and switch chip so there are things related to clocking and IO pad configuration. It is necessary for both the switch and CPU to have a handle to access it. > It has no children, so why is it a > simple-bus? > > From the above, and the patch adding the corediv driver, it looks like > the corediv-clock actually lives in this block, so I don't understand > why the corediv-clock is sitting in internal-regs with a sideband > reference to dfx. Yeah I think the corediv-clock should be a child of this node. I'll move it there. > > Thanks, > Mark. >