From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55295) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C3p-0007zo-2N for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6C3l-0001R5-MY for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:32 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39832 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C3l-0001QI-3Z for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:29 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 031B88FFEB for ; Sat, 10 Mar 2012 03:29:28 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 10 Mar 2012 03:27:45 +0100 Message-Id: <1331346496-10736-14-git-send-email-afaerber@suse.de> In-Reply-To: <1331346496-10736-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: Don't overuse CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Scripted conversion: sed -i "s/CPUState/CPUAlphaState/g" target-alpha/*.[hc] sed -i "s/#define CPUAlphaState/#define CPUState/" target-alpha/cpu.h Signed-off-by: Andreas F=C3=A4rber --- target-alpha/cpu.h | 24 ++++++++++---------- target-alpha/helper.c | 18 +++++++------- target-alpha/machine.c | 44 ++++++++++++++++++------------------ target-alpha/op_helper.c | 6 ++-- target-alpha/translate.c | 56 +++++++++++++++++++++++-----------------= ------ 5 files changed, 74 insertions(+), 74 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 5cd6fd8..ecc2a35 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -375,7 +375,7 @@ enum { PS_USER_MODE =3D 8 }; =20 -static inline int cpu_mmu_index(CPUState *env) +static inline int cpu_mmu_index(CPUAlphaState *env) { if (env->pal_mode) { return MMU_KERNEL_IDX; @@ -430,16 +430,16 @@ int cpu_alpha_exec(CPUAlphaState *s); is returned if the signal was handled by the virtual CPU. */ int cpu_alpha_signal_handler(int host_signum, void *pinfo, void *puc); -int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw, +int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, in= t rw, int mmu_idx); #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault -void do_interrupt (CPUState *env); +void do_interrupt (CPUAlphaState *env); =20 -uint64_t cpu_alpha_load_fpcr (CPUState *env); -void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); +uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); +void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); #ifndef CONFIG_USER_ONLY -void swap_shadow_regs(CPUState *env); -QEMU_NORETURN void cpu_unassigned_access(CPUState *env1, +void swap_shadow_regs(CPUAlphaState *env); +QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1, target_phys_addr_t addr, int is= _write, int is_exec, int unused, int si= ze); #endif @@ -459,7 +459,7 @@ enum { TB_FLAGS_AMASK_PREFETCH =3D AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT, }; =20 -static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, +static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong= *pc, target_ulong *cs_base, int *pfla= gs) { int flags =3D 0; @@ -481,7 +481,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env= , target_ulong *pc, } =20 #if defined(CONFIG_USER_ONLY) -static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) +static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp= ) { if (newsp) { env->ir[IR_SP] =3D newsp; @@ -490,13 +490,13 @@ static inline void cpu_clone_regs(CPUState *env, ta= rget_ulong newsp) env->ir[IR_A3] =3D 0; } =20 -static inline void cpu_set_tls(CPUState *env, target_ulong newtls) +static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls) { env->unique =3D newtls; } #endif =20 -static inline bool cpu_has_work(CPUState *env) +static inline bool cpu_has_work(CPUAlphaState *env) { /* Here we are checking to see if the CPU should wake up from HALT. We will have gotten into this state only for WTINT from PALmode. = */ @@ -513,7 +513,7 @@ static inline bool cpu_has_work(CPUState *env) =20 #include "exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) +static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *= tb) { env->pc =3D tb->pc; } diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 06d2565..3f2e7c3 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -24,7 +24,7 @@ #include "cpu.h" #include "softfloat.h" =20 -uint64_t cpu_alpha_load_fpcr (CPUState *env) +uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env) { uint64_t r =3D 0; uint8_t t; @@ -94,7 +94,7 @@ uint64_t cpu_alpha_load_fpcr (CPUState *env) return r; } =20 -void cpu_alpha_store_fpcr (CPUState *env, uint64_t val) +void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val) { uint8_t t; =20 @@ -159,7 +159,7 @@ void cpu_alpha_store_fpcr (CPUState *env, uint64_t va= l) } =20 #if defined(CONFIG_USER_ONLY) -int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int= rw, +int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, target_ulong address= , int rw, int mmu_idx) { env->exception_index =3D EXCP_MMFAULT; @@ -167,7 +167,7 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target= _ulong address, int rw, return 1; } #else -void swap_shadow_regs(CPUState *env) +void swap_shadow_regs(CPUAlphaState *env) { uint64_t i0, i1, i2, i3, i4, i5, i6, i7; =20 @@ -200,7 +200,7 @@ void swap_shadow_regs(CPUState *env) } =20 /* Returns the OSF/1 entMM failure indication, or -1 on success. */ -static int get_physical_address(CPUState *env, target_ulong addr, +static int get_physical_address(CPUAlphaState *env, target_ulong addr, int prot_need, int mmu_idx, target_ulong *pphys, int *pprot) { @@ -306,7 +306,7 @@ static int get_physical_address(CPUState *env, target= _ulong addr, return ret; } =20 -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong a= ddr) +target_phys_addr_t cpu_get_phys_page_debug(CPUAlphaState *env, target_ul= ong addr) { target_ulong phys; int prot, fail; @@ -315,7 +315,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *= env, target_ulong addr) return (fail >=3D 0 ? -1 : phys); } =20 -int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw, +int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong addr, in= t rw, int mmu_idx) { target_ulong phys; @@ -336,7 +336,7 @@ int cpu_alpha_handle_mmu_fault(CPUState *env, target_= ulong addr, int rw, } #endif /* USER_ONLY */ =20 -void do_interrupt (CPUState *env) +void do_interrupt (CPUAlphaState *env) { int i =3D env->exception_index; =20 @@ -453,7 +453,7 @@ void do_interrupt (CPUState *env) #endif /* !USER_ONLY */ } =20 -void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprint= f, +void cpu_dump_state (CPUAlphaState *env, FILE *f, fprintf_function cpu_f= printf, int flags) { static const char *linux_reg_names[] =3D { diff --git a/target-alpha/machine.c b/target-alpha/machine.c index 76d70d9..1c9edd1 100644 --- a/target-alpha/machine.c +++ b/target-alpha/machine.c @@ -21,8 +21,8 @@ static const VMStateInfo vmstate_fpcr =3D { }; =20 static VMStateField vmstate_cpu_fields[] =3D { - VMSTATE_UINTTL_ARRAY(ir, CPUState, 31), - VMSTATE_UINTTL_ARRAY(fir, CPUState, 31), + VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31), + VMSTATE_UINTTL_ARRAY(fir, CPUAlphaState, 31), /* Save the architecture value of the fpcr, not the internally expanded version. Since this architecture value does not exist in memory to be stored, this requires a but of hoop @@ -37,33 +37,33 @@ static VMStateField vmstate_cpu_fields[] =3D { .flags =3D VMS_SINGLE, .offset =3D 0 }, - VMSTATE_UINTTL(pc, CPUState), - VMSTATE_UINTTL(unique, CPUState), - VMSTATE_UINTTL(lock_addr, CPUState), - VMSTATE_UINTTL(lock_value, CPUState), + VMSTATE_UINTTL(pc, CPUAlphaState), + VMSTATE_UINTTL(unique, CPUAlphaState), + VMSTATE_UINTTL(lock_addr, CPUAlphaState), + VMSTATE_UINTTL(lock_value, CPUAlphaState), /* Note that lock_st_addr is not saved; it is a temporary used during the execution of the st[lq]_c insns. */ =20 - VMSTATE_UINT8(ps, CPUState), - VMSTATE_UINT8(intr_flag, CPUState), - VMSTATE_UINT8(pal_mode, CPUState), - VMSTATE_UINT8(fen, CPUState), + VMSTATE_UINT8(ps, CPUAlphaState), + VMSTATE_UINT8(intr_flag, CPUAlphaState), + VMSTATE_UINT8(pal_mode, CPUAlphaState), + VMSTATE_UINT8(fen, CPUAlphaState), =20 - VMSTATE_UINT32(pcc_ofs, CPUState), + VMSTATE_UINT32(pcc_ofs, CPUAlphaState), =20 - VMSTATE_UINTTL(trap_arg0, CPUState), - VMSTATE_UINTTL(trap_arg1, CPUState), - VMSTATE_UINTTL(trap_arg2, CPUState), + VMSTATE_UINTTL(trap_arg0, CPUAlphaState), + VMSTATE_UINTTL(trap_arg1, CPUAlphaState), + VMSTATE_UINTTL(trap_arg2, CPUAlphaState), =20 - VMSTATE_UINTTL(exc_addr, CPUState), - VMSTATE_UINTTL(palbr, CPUState), - VMSTATE_UINTTL(ptbr, CPUState), - VMSTATE_UINTTL(vptptr, CPUState), - VMSTATE_UINTTL(sysval, CPUState), - VMSTATE_UINTTL(usp, CPUState), + VMSTATE_UINTTL(exc_addr, CPUAlphaState), + VMSTATE_UINTTL(palbr, CPUAlphaState), + VMSTATE_UINTTL(ptbr, CPUAlphaState), + VMSTATE_UINTTL(vptptr, CPUAlphaState), + VMSTATE_UINTTL(sysval, CPUAlphaState), + VMSTATE_UINTTL(usp, CPUAlphaState), =20 - VMSTATE_UINTTL_ARRAY(shadow, CPUState, 8), - VMSTATE_UINTTL_ARRAY(scratch, CPUState, 24), + VMSTATE_UINTTL_ARRAY(shadow, CPUAlphaState, 8), + VMSTATE_UINTTL_ARRAY(scratch, CPUAlphaState, 24), =20 VMSTATE_END_OF_LIST() }; diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index cc102db..c77f009 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1329,7 +1329,7 @@ static void QEMU_NORETURN do_unaligned_access(targe= t_ulong addr, int is_write, helper_excp(EXCP_UNALIGN, 0); } =20 -void QEMU_NORETURN cpu_unassigned_access(CPUState *env1, +void QEMU_NORETURN cpu_unassigned_access(CPUAlphaState *env1, target_phys_addr_t addr, int is= _write, int is_exec, int unused, int si= ze) { @@ -1360,10 +1360,10 @@ void QEMU_NORETURN cpu_unassigned_access(CPUState= *env1, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_i= dx, +void tlb_fill(CPUAlphaState *env1, target_ulong addr, int is_write, int = mmu_idx, void *retaddr) { - CPUState *saved_env; + CPUAlphaState *saved_env; int ret; =20 saved_env =3D env; diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 1d2142b..b51fe5c 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -105,35 +105,35 @@ static void alpha_translate_init(void) for (i =3D 0; i < 31; i++) { sprintf(p, "ir%d", i); cpu_ir[i] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, ir[i]), p)= ; + offsetof(CPUAlphaState, ir[i]= ), p); p +=3D (i < 10) ? 4 : 5; =20 sprintf(p, "fir%d", i); cpu_fir[i] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, fir[i]), = p); + offsetof(CPUAlphaState, fir[= i]), p); p +=3D (i < 10) ? 5 : 6; } =20 cpu_pc =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, pc), "pc"); + offsetof(CPUAlphaState, pc), "pc"); =20 cpu_lock_addr =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, lock_addr), + offsetof(CPUAlphaState, lock_addr), "lock_addr"); cpu_lock_st_addr =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, lock_st_addr), + offsetof(CPUAlphaState, lock_st_addr), "lock_st_addr"); cpu_lock_value =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, lock_value), + offsetof(CPUAlphaState, lock_value), "lock_value"); =20 cpu_unique =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, unique), "uni= que"); + offsetof(CPUAlphaState, unique),= "unique"); #ifndef CONFIG_USER_ONLY cpu_sysval =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, sysval), "sys= val"); + offsetof(CPUAlphaState, sysval),= "sysval"); cpu_usp =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, usp), "usp"); + offsetof(CPUAlphaState, usp), "usp"= ); #endif =20 /* register helpers */ @@ -611,7 +611,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int= fn11) tcg_gen_movi_i32(tmp, float_round_down); break; case QUAL_RM_D: - tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_dyn_round= )); + tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUAlphaState, fpcr_dyn_= round)); break; } =20 @@ -620,7 +620,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int= fn11) With CONFIG_SOFTFLOAT that expands to an out-of-line call that ju= st sets the one field. */ tcg_gen_st8_i32(tmp, cpu_env, - offsetof(CPUState, fp_status.float_rounding_mode)); + offsetof(CPUAlphaState, fp_status.float_rounding_mod= e)); #else gen_helper_setroundmode(tmp); #endif @@ -641,7 +641,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int= fn11) tmp =3D tcg_temp_new_i32(); if (fn11) { /* Underflow is enabled, use the FPCR setting. */ - tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_flush_to_= zero)); + tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUAlphaState, fpcr_flus= h_to_zero)); } else { /* Underflow is disabled, force flush-to-zero. */ tcg_gen_movi_i32(tmp, 1); @@ -649,7 +649,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int= fn11) =20 #if defined(CONFIG_SOFTFLOAT_INLINE) tcg_gen_st8_i32(tmp, cpu_env, - offsetof(CPUState, fp_status.flush_to_zero)); + offsetof(CPUAlphaState, fp_status.flush_to_zero)); #else gen_helper_setflushzero(tmp); #endif @@ -677,7 +677,7 @@ static void gen_fp_exc_clear(void) #if defined(CONFIG_SOFTFLOAT_INLINE) TCGv_i32 zero =3D tcg_const_i32(0); tcg_gen_st8_i32(zero, cpu_env, - offsetof(CPUState, fp_status.float_exception_flags))= ; + offsetof(CPUAlphaState, fp_status.float_exception_fl= ags)); tcg_temp_free_i32(zero); #else gen_helper_fp_exc_clear(); @@ -696,7 +696,7 @@ static void gen_fp_exc_raise_ignore(int rc, int fn11,= int ignore) =20 #if defined(CONFIG_SOFTFLOAT_INLINE) tcg_gen_ld8u_i32(exc, cpu_env, - offsetof(CPUState, fp_status.float_exception_flags)= ); + offsetof(CPUAlphaState, fp_status.float_exception_f= lags)); #else gen_helper_fp_exc_get(exc); #endif @@ -1456,11 +1456,11 @@ static void gen_rx(int ra, int set) TCGv_i32 tmp; =20 if (ra !=3D 31) { - tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUState, intr_fl= ag)); + tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUAlphaState, in= tr_flag)); } =20 tmp =3D tcg_const_i32(set); - tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUState, intr_flag)); + tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag)); tcg_temp_free_i32(tmp); } =20 @@ -1504,7 +1504,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) break; case 0x2D: /* WRVPTPTR */ - tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUState, vp= tptr)); + tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUAlphaStat= e, vptptr)); break; case 0x31: /* WRVAL */ @@ -1521,19 +1521,19 @@ static ExitStatus gen_call_pal(DisasContext *ctx,= int palcode) =20 /* Note that we already know we're in kernel mode, so we kno= w that PS only contains the 3 IPL bits. */ - tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, = ps)); + tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaSt= ate, ps)); =20 /* But make sure and store only the 3 IPL bits from the user= . */ tmp =3D tcg_temp_new(); tcg_gen_andi_i64(tmp, cpu_ir[IR_A0], PS_INT_MASK); - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUState, ps)); + tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, ps)); tcg_temp_free(tmp); break; } =20 case 0x36: /* RDPS */ - tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, = ps)); + tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaSt= ate, ps)); break; case 0x38: /* WRUSP */ @@ -1546,7 +1546,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) case 0x3C: /* WHAMI */ tcg_gen_ld32s_i64(cpu_ir[IR_V0], cpu_env, - offsetof(CPUState, cpu_index)); + offsetof(CPUAlphaState, cpu_index)); break; =20 default: @@ -1654,7 +1654,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int r= b, int regno) case 253: /* WAIT */ tmp =3D tcg_const_i64(1); - tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUState, halted)); + tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUAlphaState, halted)); return gen_excp(ctx, EXCP_HLT, 0); =20 case 252: @@ -3107,7 +3107,7 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) address from EXC_ADDR. This turns out to be useful f= or our emulation PALcode, so continue to accept it. */ TCGv tmp =3D tcg_temp_new(); - tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, exc_addr= )); + tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc= _addr)); gen_helper_hw_ret(tmp); tcg_temp_free(tmp); } else { @@ -3325,7 +3325,7 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) return ret; } =20 -static inline void gen_intermediate_code_internal(CPUState *env, +static inline void gen_intermediate_code_internal(CPUAlphaState *env, TranslationBlock *tb, int search_pc) { @@ -3450,12 +3450,12 @@ static inline void gen_intermediate_code_internal= (CPUState *env, #endif } =20 -void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) +void gen_intermediate_code (CPUAlphaState *env, struct TranslationBlock = *tb) { gen_intermediate_code_internal(env, tb, 0); } =20 -void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *t= b) +void gen_intermediate_code_pc (CPUAlphaState *env, struct TranslationBlo= ck *tb) { gen_intermediate_code_internal(env, tb, 1); } @@ -3522,7 +3522,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_mod= el) return env; } =20 -void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_po= s) +void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int = pc_pos) { env->pc =3D gen_opc_pc[pc_pos]; } --=20 1.7.7