From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55637) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C4D-0000EK-5C for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:30:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6C3n-0001Re-OL for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:56 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39835 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C3n-0001RE-4y for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:31 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 0EAA58FE2D for ; Sat, 10 Mar 2012 03:29:30 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 10 Mar 2012 03:27:48 +0100 Message-Id: <1331346496-10736-17-git-send-email-afaerber@suse.de> In-Reply-To: <1331346496-10736-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v4 16/44] target-i386: Don't overuse CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Scripted conversion: sed -i "s/CPUState/CPUX86State/g" target-i386/*.[hc] sed -i "s/#define CPUX86State/#define CPUState/" target-i386/cpu.h Signed-off-by: Andreas F=C3=A4rber --- target-i386/cpu.h | 34 +++++----- target-i386/helper.c | 38 +++++----- target-i386/kvm.c | 76 ++++++++++---------- target-i386/machine.c | 172 +++++++++++++++++++++++------------------= ----- target-i386/op_helper.c | 34 +++++----- target-i386/translate.c | 82 +++++++++++----------- 6 files changed, 218 insertions(+), 218 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 196b0c5..f337dd0 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -787,7 +787,7 @@ int cpu_x86_exec(CPUX86State *s); void cpu_x86_close(CPUX86State *s); void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *op= targ); void x86_cpudef_setup(void); -int cpu_x86_support_mca_broadcast(CPUState *env); +int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 int cpu_get_pic_interrupt(CPUX86State *s); /* MSDOS compatibility mode FPU exception support */ @@ -969,7 +969,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUState *env) +static inline int cpu_mmu_index (CPUX86State *env) { return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? 1 : 0; } @@ -1008,7 +1008,7 @@ static inline int cpu_mmu_index (CPUState *env) void optimize_flags_init(void); =20 #if defined(CONFIG_USER_ONLY) -static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) +static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp) { if (newsp) env->regs[R_ESP] =3D newsp; @@ -1023,7 +1023,7 @@ static inline void cpu_clone_regs(CPUState *env, ta= rget_ulong newsp) #include "hw/apic.h" #endif =20 -static inline bool cpu_has_work(CPUState *env) +static inline bool cpu_has_work(CPUX86State *env) { return ((env->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || @@ -1035,12 +1035,12 @@ static inline bool cpu_has_work(CPUState *env) =20 #include "exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) +static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb= ) { env->eip =3D tb->pc - tb->cs_base; } =20 -static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, +static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *= pc, target_ulong *cs_base, int *flag= s) { *cs_base =3D env->segs[R_CS].base; @@ -1049,29 +1049,29 @@ static inline void cpu_get_tb_cpu_state(CPUState = *env, target_ulong *pc, (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK)); } =20 -void do_cpu_init(CPUState *env); -void do_cpu_sipi(CPUState *env); +void do_cpu_init(CPUX86State *env); +void do_cpu_sipi(CPUX86State *env); =20 #define MCE_INJECT_BROADCAST 1 #define MCE_INJECT_UNCOND_AO 2 =20 -void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank, +void cpu_x86_inject_mce(Monitor *mon, CPUX86State *cenv, int bank, uint64_t status, uint64_t mcg_status, uint64_t a= ddr, uint64_t misc, int flags); =20 /* op_helper.c */ -void do_interrupt(CPUState *env); -void do_interrupt_x86_hardirq(CPUState *env, int intno, int is_hw); -void QEMU_NORETURN raise_exception_env(int exception_index, CPUState *ne= nv); -void QEMU_NORETURN raise_exception_err_env(CPUState *nenv, int exception= _index, +void do_interrupt(CPUX86State *env); +void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); +void QEMU_NORETURN raise_exception_env(int exception_index, CPUX86State = *nenv); +void QEMU_NORETURN raise_exception_err_env(CPUX86State *nenv, int except= ion_index, int error_code); =20 -void do_smm_enter(CPUState *env1); +void do_smm_enter(CPUX86State *env1); =20 -void svm_check_intercept(CPUState *env1, uint32_t type); +void svm_check_intercept(CPUX86State *env1, uint32_t type); =20 -uint32_t cpu_cc_compute_all(CPUState *env1, int op); +uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); =20 -void cpu_report_tpr_access(CPUState *env, TPRAccess access); +void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); =20 #endif /* CPU_I386_H */ diff --git a/target-i386/helper.c b/target-i386/helper.c index 0d84c27..c702bd6 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -27,7 +27,7 @@ //#define DEBUG_MMU =20 /* NOTE: must be called outside the CPU execute loop */ -void cpu_state_reset(CPUState *env) +void cpu_state_reset(CPUX86State *env) { int i; =20 @@ -106,7 +106,7 @@ void cpu_x86_close(CPUX86State *env) g_free(env); } =20 -static void cpu_x86_version(CPUState *env, int *family, int *model) +static void cpu_x86_version(CPUX86State *env, int *family, int *model) { int cpuver =3D env->cpuid_version; =20 @@ -119,7 +119,7 @@ static void cpu_x86_version(CPUState *env, int *famil= y, int *model) } =20 /* Broadcast MCA signal for processor version 06H_EH and above */ -int cpu_x86_support_mca_broadcast(CPUState *env) +int cpu_x86_support_mca_broadcast(CPUX86State *env) { int family =3D 0; int model =3D 0; @@ -191,7 +191,7 @@ static const char *cc_op_str[] =3D { }; =20 static void -cpu_x86_dump_seg_cache(CPUState *env, FILE *f, fprintf_function cpu_fpri= ntf, +cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, fprintf_function cpu_f= printf, const char *name, struct SegmentCache *sc) { #ifdef TARGET_X86_64 @@ -248,7 +248,7 @@ done: #define DUMP_CODE_BYTES_TOTAL 50 #define DUMP_CODE_BYTES_BACKWARD 20 =20 -void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf= , +void cpu_dump_state(CPUX86State *env, FILE *f, fprintf_function cpu_fpri= ntf, int flags) { int eflags, i, nb; @@ -857,7 +857,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target= _ulong addr, return 1; } =20 -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong a= ddr) +target_phys_addr_t cpu_get_phys_page_debug(CPUX86State *env, target_ulon= g addr) { target_ulong pde_addr, pte_addr; uint64_t pte; @@ -951,7 +951,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *= env, target_ulong addr) return paddr; } =20 -void hw_breakpoint_insert(CPUState *env, int index) +void hw_breakpoint_insert(CPUX86State *env, int index) { int type, err =3D 0; =20 @@ -979,7 +979,7 @@ void hw_breakpoint_insert(CPUState *env, int index) env->cpu_breakpoint[index] =3D NULL; } =20 -void hw_breakpoint_remove(CPUState *env, int index) +void hw_breakpoint_remove(CPUX86State *env, int index) { if (!env->cpu_breakpoint[index]) return; @@ -998,7 +998,7 @@ void hw_breakpoint_remove(CPUState *env, int index) } } =20 -int check_hw_breakpoints(CPUState *env, int force_dr6_update) +int check_hw_breakpoints(CPUX86State *env, int force_dr6_update) { target_ulong dr6; int reg, type; @@ -1022,7 +1022,7 @@ int check_hw_breakpoints(CPUState *env, int force_d= r6_update) =20 static CPUDebugExcpHandler *prev_debug_excp_handler; =20 -static void breakpoint_handler(CPUState *env) +static void breakpoint_handler(CPUX86State *env) { CPUBreakpoint *bp; =20 @@ -1050,7 +1050,7 @@ static void breakpoint_handler(CPUState *env) =20 typedef struct MCEInjectionParams { Monitor *mon; - CPUState *env; + CPUX86State *env; int bank; uint64_t status; uint64_t mcg_status; @@ -1062,7 +1062,7 @@ typedef struct MCEInjectionParams { static void do_inject_x86_mce(void *data) { MCEInjectionParams *params =3D data; - CPUState *cenv =3D params->env; + CPUX86State *cenv =3D params->env; uint64_t *banks =3D cenv->mce_banks + 4 * params->bank; =20 cpu_synchronize_state(cenv); @@ -1132,7 +1132,7 @@ static void do_inject_x86_mce(void *data) } } =20 -void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank, +void cpu_x86_inject_mce(Monitor *mon, CPUX86State *cenv, int bank, uint64_t status, uint64_t mcg_status, uint64_t a= ddr, uint64_t misc, int flags) { @@ -1147,7 +1147,7 @@ void cpu_x86_inject_mce(Monitor *mon, CPUState *cen= v, int bank, .flags =3D flags, }; unsigned bank_num =3D cenv->mcg_cap & 0xff; - CPUState *env; + CPUX86State *env; =20 if (!cenv->mcg_cap) { monitor_printf(mon, "MCE injection not supported\n"); @@ -1184,7 +1184,7 @@ void cpu_x86_inject_mce(Monitor *mon, CPUState *cen= v, int bank, } } =20 -void cpu_report_tpr_access(CPUState *env, TPRAccess access) +void cpu_report_tpr_access(CPUX86State *env, TPRAccess access) { TranslationBlock *tb; =20 @@ -1276,7 +1276,7 @@ CPUX86State *cpu_x86_init(const char *cpu_model) } =20 #if !defined(CONFIG_USER_ONLY) -void do_cpu_init(CPUState *env) +void do_cpu_init(CPUX86State *env) { int sipi =3D env->interrupt_request & CPU_INTERRUPT_SIPI; uint64_t pat =3D env->pat; @@ -1288,15 +1288,15 @@ void do_cpu_init(CPUState *env) env->halted =3D !cpu_is_bsp(env); } =20 -void do_cpu_sipi(CPUState *env) +void do_cpu_sipi(CPUX86State *env) { apic_sipi(env->apic_state); } #else -void do_cpu_init(CPUState *env) +void do_cpu_init(CPUX86State *env) { } -void do_cpu_sipi(CPUState *env) +void do_cpu_sipi(CPUX86State *env) { } #endif diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 619d773..e74a9e4 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -221,7 +221,7 @@ static int kvm_get_mce_cap_supported(KVMState *s, uin= t64_t *mce_cap, return -ENOSYS; } =20 -static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int = code) +static void kvm_mce_inject(CPUX86State *env, target_phys_addr_t paddr, i= nt code) { uint64_t status =3D MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S= ; @@ -246,7 +246,7 @@ static void hardware_memory_error(void) exit(1); } =20 -int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) +int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr) { ram_addr_t ram_addr; target_phys_addr_t paddr; @@ -306,7 +306,7 @@ int kvm_arch_on_sigbus(int code, void *addr) return 0; } =20 -static int kvm_inject_mce_oldstyle(CPUState *env) +static int kvm_inject_mce_oldstyle(CPUX86State *env) { if (!kvm_has_vcpu_events() && env->exception_injected =3D=3D EXCP12_= MCHK) { unsigned int bank, bank_num =3D env->mcg_cap & 0xff; @@ -338,14 +338,14 @@ static int kvm_inject_mce_oldstyle(CPUState *env) =20 static void cpu_update_state(void *opaque, int running, RunState state) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; =20 if (running) { env->tsc_valid =3D false; } } =20 -int kvm_arch_init_vcpu(CPUState *env) +int kvm_arch_init_vcpu(CPUX86State *env) { struct { struct kvm_cpuid2 cpuid; @@ -577,7 +577,7 @@ int kvm_arch_init_vcpu(CPUState *env) return 0; } =20 -void kvm_arch_reset_vcpu(CPUState *env) +void kvm_arch_reset_vcpu(CPUX86State *env) { env->exception_injected =3D -1; env->interrupt_injected =3D -1; @@ -768,7 +768,7 @@ static void kvm_getput_reg(__u64 *kvm_reg, target_ulo= ng *qemu_reg, int set) } } =20 -static int kvm_getput_regs(CPUState *env, int set) +static int kvm_getput_regs(CPUX86State *env, int set) { struct kvm_regs regs; int ret =3D 0; @@ -809,7 +809,7 @@ static int kvm_getput_regs(CPUState *env, int set) return ret; } =20 -static int kvm_put_fpu(CPUState *env) +static int kvm_put_fpu(CPUX86State *env) { struct kvm_fpu fpu; int i; @@ -841,7 +841,7 @@ static int kvm_put_fpu(CPUState *env) #define XSAVE_XSTATE_BV 128 #define XSAVE_YMMH_SPACE 144 =20 -static int kvm_put_xsave(CPUState *env) +static int kvm_put_xsave(CPUX86State *env) { struct kvm_xsave* xsave =3D env->kvm_xsave_buf; uint16_t cwd, swd, twd; @@ -875,7 +875,7 @@ static int kvm_put_xsave(CPUState *env) return r; } =20 -static int kvm_put_xcrs(CPUState *env) +static int kvm_put_xcrs(CPUX86State *env) { struct kvm_xcrs xcrs; =20 @@ -890,7 +890,7 @@ static int kvm_put_xcrs(CPUState *env) return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); } =20 -static int kvm_put_sregs(CPUState *env) +static int kvm_put_sregs(CPUX86State *env) { struct kvm_sregs sregs; =20 @@ -946,7 +946,7 @@ static void kvm_msr_entry_set(struct kvm_msr_entry *e= ntry, entry->data =3D value; } =20 -static int kvm_put_msrs(CPUState *env, int level) +static int kvm_put_msrs(CPUX86State *env, int level) { struct { struct kvm_msrs info; @@ -1029,7 +1029,7 @@ static int kvm_put_msrs(CPUState *env, int level) } =20 =20 -static int kvm_get_fpu(CPUState *env) +static int kvm_get_fpu(CPUX86State *env) { struct kvm_fpu fpu; int i, ret; @@ -1055,7 +1055,7 @@ static int kvm_get_fpu(CPUState *env) return 0; } =20 -static int kvm_get_xsave(CPUState *env) +static int kvm_get_xsave(CPUX86State *env) { struct kvm_xsave* xsave =3D env->kvm_xsave_buf; int ret, i; @@ -1093,7 +1093,7 @@ static int kvm_get_xsave(CPUState *env) return 0; } =20 -static int kvm_get_xcrs(CPUState *env) +static int kvm_get_xcrs(CPUX86State *env) { int i, ret; struct kvm_xcrs xcrs; @@ -1117,7 +1117,7 @@ static int kvm_get_xcrs(CPUState *env) return 0; } =20 -static int kvm_get_sregs(CPUState *env) +static int kvm_get_sregs(CPUX86State *env) { struct kvm_sregs sregs; uint32_t hflags; @@ -1201,7 +1201,7 @@ static int kvm_get_sregs(CPUState *env) return 0; } =20 -static int kvm_get_msrs(CPUState *env) +static int kvm_get_msrs(CPUX86State *env) { struct { struct kvm_msrs info; @@ -1331,14 +1331,14 @@ static int kvm_get_msrs(CPUState *env) return 0; } =20 -static int kvm_put_mp_state(CPUState *env) +static int kvm_put_mp_state(CPUX86State *env) { struct kvm_mp_state mp_state =3D { .mp_state =3D env->mp_state }; =20 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); } =20 -static int kvm_get_mp_state(CPUState *env) +static int kvm_get_mp_state(CPUX86State *env) { struct kvm_mp_state mp_state; int ret; @@ -1354,7 +1354,7 @@ static int kvm_get_mp_state(CPUState *env) return 0; } =20 -static int kvm_get_apic(CPUState *env) +static int kvm_get_apic(CPUX86State *env) { DeviceState *apic =3D env->apic_state; struct kvm_lapic_state kapic; @@ -1371,7 +1371,7 @@ static int kvm_get_apic(CPUState *env) return 0; } =20 -static int kvm_put_apic(CPUState *env) +static int kvm_put_apic(CPUX86State *env) { DeviceState *apic =3D env->apic_state; struct kvm_lapic_state kapic; @@ -1384,7 +1384,7 @@ static int kvm_put_apic(CPUState *env) return 0; } =20 -static int kvm_put_vcpu_events(CPUState *env, int level) +static int kvm_put_vcpu_events(CPUX86State *env, int level) { struct kvm_vcpu_events events; =20 @@ -1418,7 +1418,7 @@ static int kvm_put_vcpu_events(CPUState *env, int l= evel) return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); } =20 -static int kvm_get_vcpu_events(CPUState *env) +static int kvm_get_vcpu_events(CPUX86State *env) { struct kvm_vcpu_events events; int ret; @@ -1453,7 +1453,7 @@ static int kvm_get_vcpu_events(CPUState *env) return 0; } =20 -static int kvm_guest_debug_workarounds(CPUState *env) +static int kvm_guest_debug_workarounds(CPUX86State *env) { int ret =3D 0; unsigned long reinject_trap =3D 0; @@ -1482,7 +1482,7 @@ static int kvm_guest_debug_workarounds(CPUState *en= v) return ret; } =20 -static int kvm_put_debugregs(CPUState *env) +static int kvm_put_debugregs(CPUX86State *env) { struct kvm_debugregs dbgregs; int i; @@ -1501,7 +1501,7 @@ static int kvm_put_debugregs(CPUState *env) return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); } =20 -static int kvm_get_debugregs(CPUState *env) +static int kvm_get_debugregs(CPUX86State *env) { struct kvm_debugregs dbgregs; int i, ret; @@ -1523,7 +1523,7 @@ static int kvm_get_debugregs(CPUState *env) return 0; } =20 -int kvm_arch_put_registers(CPUState *env, int level) +int kvm_arch_put_registers(CPUX86State *env, int level) { int ret; =20 @@ -1580,7 +1580,7 @@ int kvm_arch_put_registers(CPUState *env, int level= ) return 0; } =20 -int kvm_arch_get_registers(CPUState *env) +int kvm_arch_get_registers(CPUX86State *env) { int ret; =20 @@ -1625,7 +1625,7 @@ int kvm_arch_get_registers(CPUState *env) return 0; } =20 -void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) +void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run) { int ret; =20 @@ -1685,7 +1685,7 @@ void kvm_arch_pre_run(CPUState *env, struct kvm_run= *run) } } =20 -void kvm_arch_post_run(CPUState *env, struct kvm_run *run) +void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run) { if (run->if_flag) { env->eflags |=3D IF_MASK; @@ -1696,7 +1696,7 @@ void kvm_arch_post_run(CPUState *env, struct kvm_ru= n *run) cpu_set_apic_base(env->apic_state, run->apic_base); } =20 -int kvm_arch_process_async_events(CPUState *env) +int kvm_arch_process_async_events(CPUX86State *env) { if (env->interrupt_request & CPU_INTERRUPT_MCE) { /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ @@ -1748,7 +1748,7 @@ int kvm_arch_process_async_events(CPUState *env) return env->halted; } =20 -static int kvm_handle_halt(CPUState *env) +static int kvm_handle_halt(CPUX86State *env) { if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) && @@ -1760,7 +1760,7 @@ static int kvm_handle_halt(CPUState *env) return 0; } =20 -static int kvm_handle_tpr_access(CPUState *env) +static int kvm_handle_tpr_access(CPUX86State *env) { struct kvm_run *run =3D env->kvm_run; =20 @@ -1770,7 +1770,7 @@ static int kvm_handle_tpr_access(CPUState *env) return 1; } =20 -int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoin= t *bp) +int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakp= oint *bp) { static const uint8_t int3 =3D 0xcc; =20 @@ -1781,7 +1781,7 @@ int kvm_arch_insert_sw_breakpoint(CPUState *env, st= ruct kvm_sw_breakpoint *bp) return 0; } =20 -int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoin= t *bp) +int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakp= oint *bp) { uint8_t int3; =20 @@ -1924,7 +1924,7 @@ static int kvm_handle_debug(struct kvm_debug_exit_a= rch *arch_info) return ret; } =20 -void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *= dbg) +void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debu= g *dbg) { const uint8_t type_code[] =3D { [GDB_BREAKPOINT_HW] =3D 0x0, @@ -1961,7 +1961,7 @@ static bool host_supports_vmx(void) =20 #define VMX_INVALID_GUEST_STATE 0x80000021 =20 -int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) +int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run) { uint64_t code; int ret; @@ -2012,7 +2012,7 @@ int kvm_arch_handle_exit(CPUState *env, struct kvm_= run *run) return ret; } =20 -bool kvm_arch_stop_on_emulation_error(CPUState *env) +bool kvm_arch_stop_on_emulation_error(CPUX86State *env) { kvm_cpu_synchronize_state(env); return !(env->cr[0] & CR0_PE_MASK) || diff --git a/target-i386/machine.c b/target-i386/machine.c index d6e98ff..a8be058 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -171,14 +171,14 @@ static const VMStateInfo vmstate_fpreg_1_no_mmx =3D= { =20 static bool fpregs_is_0(void *opaque, int version_id) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; =20 return (env->fpregs_format_vmstate =3D=3D 0); } =20 static bool fpregs_is_1_mmx(void *opaque, int version_id) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; int guess_mmx; =20 guess_mmx =3D ((env->fptag_vmstate =3D=3D 0xff) && @@ -188,7 +188,7 @@ static bool fpregs_is_1_mmx(void *opaque, int version= _id) =20 static bool fpregs_is_1_no_mmx(void *opaque, int version_id) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; int guess_mmx; =20 guess_mmx =3D ((env->fptag_vmstate =3D=3D 0xff) && @@ -237,7 +237,7 @@ static const VMStateInfo vmstate_hack_uint64_as_uint3= 2 =3D { =20 static void cpu_pre_save(void *opaque) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; int i; =20 /* FPU */ @@ -252,7 +252,7 @@ static void cpu_pre_save(void *opaque) =20 static int cpu_post_load(void *opaque, int version_id) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; int i; =20 /* XXX: restore FPU round state */ @@ -274,7 +274,7 @@ static int cpu_post_load(void *opaque, int version_id= ) =20 static bool async_pf_msr_needed(void *opaque) { - CPUState *cpu =3D opaque; + CPUX86State *cpu =3D opaque; =20 return cpu->async_pf_en_msr !=3D 0; } @@ -285,14 +285,14 @@ static const VMStateDescription vmstate_async_pf_ms= r =3D { .minimum_version_id =3D 1, .minimum_version_id_old =3D 1, .fields =3D (VMStateField []) { - VMSTATE_UINT64(async_pf_en_msr, CPUState), + VMSTATE_UINT64(async_pf_en_msr, CPUX86State), VMSTATE_END_OF_LIST() } }; =20 static bool fpop_ip_dp_needed(void *opaque) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; =20 return env->fpop !=3D 0 || env->fpip !=3D 0 || env->fpdp !=3D 0; } @@ -303,16 +303,16 @@ static const VMStateDescription vmstate_fpop_ip_dp = =3D { .minimum_version_id =3D 1, .minimum_version_id_old =3D 1, .fields =3D (VMStateField []) { - VMSTATE_UINT16(fpop, CPUState), - VMSTATE_UINT64(fpip, CPUState), - VMSTATE_UINT64(fpdp, CPUState), + VMSTATE_UINT16(fpop, CPUX86State), + VMSTATE_UINT64(fpip, CPUX86State), + VMSTATE_UINT64(fpdp, CPUX86State), VMSTATE_END_OF_LIST() } }; =20 static bool tscdeadline_needed(void *opaque) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; =20 return env->tsc_deadline !=3D 0; } @@ -323,14 +323,14 @@ static const VMStateDescription vmstate_msr_tscdead= line =3D { .minimum_version_id =3D 1, .minimum_version_id_old =3D 1, .fields =3D (VMStateField []) { - VMSTATE_UINT64(tsc_deadline, CPUState), + VMSTATE_UINT64(tsc_deadline, CPUX86State), VMSTATE_END_OF_LIST() } }; =20 static bool misc_enable_needed(void *opaque) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; =20 return env->msr_ia32_misc_enable !=3D MSR_IA32_MISC_ENABLE_DEFAULT; } @@ -341,7 +341,7 @@ static const VMStateDescription vmstate_msr_ia32_misc= _enable =3D { .minimum_version_id =3D 1, .minimum_version_id_old =3D 1, .fields =3D (VMStateField []) { - VMSTATE_UINT64(msr_ia32_misc_enable, CPUState), + VMSTATE_UINT64(msr_ia32_misc_enable, CPUX86State), VMSTATE_END_OF_LIST() } }; @@ -354,98 +354,98 @@ static const VMStateDescription vmstate_cpu =3D { .pre_save =3D cpu_pre_save, .post_load =3D cpu_post_load, .fields =3D (VMStateField []) { - VMSTATE_UINTTL_ARRAY(regs, CPUState, CPU_NB_REGS), - VMSTATE_UINTTL(eip, CPUState), - VMSTATE_UINTTL(eflags, CPUState), - VMSTATE_UINT32(hflags, CPUState), + VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS), + VMSTATE_UINTTL(eip, CPUX86State), + VMSTATE_UINTTL(eflags, CPUX86State), + VMSTATE_UINT32(hflags, CPUX86State), /* FPU */ - VMSTATE_UINT16(fpuc, CPUState), - VMSTATE_UINT16(fpus_vmstate, CPUState), - VMSTATE_UINT16(fptag_vmstate, CPUState), - VMSTATE_UINT16(fpregs_format_vmstate, CPUState), - VMSTATE_FP_REGS(fpregs, CPUState, 8), + VMSTATE_UINT16(fpuc, CPUX86State), + VMSTATE_UINT16(fpus_vmstate, CPUX86State), + VMSTATE_UINT16(fptag_vmstate, CPUX86State), + VMSTATE_UINT16(fpregs_format_vmstate, CPUX86State), + VMSTATE_FP_REGS(fpregs, CPUX86State, 8), =20 - VMSTATE_SEGMENT_ARRAY(segs, CPUState, 6), - VMSTATE_SEGMENT(ldt, CPUState), - VMSTATE_SEGMENT(tr, CPUState), - VMSTATE_SEGMENT(gdt, CPUState), - VMSTATE_SEGMENT(idt, CPUState), + VMSTATE_SEGMENT_ARRAY(segs, CPUX86State, 6), + VMSTATE_SEGMENT(ldt, CPUX86State), + VMSTATE_SEGMENT(tr, CPUX86State), + VMSTATE_SEGMENT(gdt, CPUX86State), + VMSTATE_SEGMENT(idt, CPUX86State), =20 - VMSTATE_UINT32(sysenter_cs, CPUState), + VMSTATE_UINT32(sysenter_cs, CPUX86State), #ifdef TARGET_X86_64 /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */ - VMSTATE_HACK_UINT32(sysenter_esp, CPUState, less_than_7), - VMSTATE_HACK_UINT32(sysenter_eip, CPUState, less_than_7), - VMSTATE_UINTTL_V(sysenter_esp, CPUState, 7), - VMSTATE_UINTTL_V(sysenter_eip, CPUState, 7), + VMSTATE_HACK_UINT32(sysenter_esp, CPUX86State, less_than_7), + VMSTATE_HACK_UINT32(sysenter_eip, CPUX86State, less_than_7), + VMSTATE_UINTTL_V(sysenter_esp, CPUX86State, 7), + VMSTATE_UINTTL_V(sysenter_eip, CPUX86State, 7), #else - VMSTATE_UINTTL(sysenter_esp, CPUState), - VMSTATE_UINTTL(sysenter_eip, CPUState), + VMSTATE_UINTTL(sysenter_esp, CPUX86State), + VMSTATE_UINTTL(sysenter_eip, CPUX86State), #endif =20 - VMSTATE_UINTTL(cr[0], CPUState), - VMSTATE_UINTTL(cr[2], CPUState), - VMSTATE_UINTTL(cr[3], CPUState), - VMSTATE_UINTTL(cr[4], CPUState), - VMSTATE_UINTTL_ARRAY(dr, CPUState, 8), + VMSTATE_UINTTL(cr[0], CPUX86State), + VMSTATE_UINTTL(cr[2], CPUX86State), + VMSTATE_UINTTL(cr[3], CPUX86State), + VMSTATE_UINTTL(cr[4], CPUX86State), + VMSTATE_UINTTL_ARRAY(dr, CPUX86State, 8), /* MMU */ - VMSTATE_INT32(a20_mask, CPUState), + VMSTATE_INT32(a20_mask, CPUX86State), /* XMM */ - VMSTATE_UINT32(mxcsr, CPUState), - VMSTATE_XMM_REGS(xmm_regs, CPUState, CPU_NB_REGS), + VMSTATE_UINT32(mxcsr, CPUX86State), + VMSTATE_XMM_REGS(xmm_regs, CPUX86State, CPU_NB_REGS), =20 #ifdef TARGET_X86_64 - VMSTATE_UINT64(efer, CPUState), - VMSTATE_UINT64(star, CPUState), - VMSTATE_UINT64(lstar, CPUState), - VMSTATE_UINT64(cstar, CPUState), - VMSTATE_UINT64(fmask, CPUState), - VMSTATE_UINT64(kernelgsbase, CPUState), + VMSTATE_UINT64(efer, CPUX86State), + VMSTATE_UINT64(star, CPUX86State), + VMSTATE_UINT64(lstar, CPUX86State), + VMSTATE_UINT64(cstar, CPUX86State), + VMSTATE_UINT64(fmask, CPUX86State), + VMSTATE_UINT64(kernelgsbase, CPUX86State), #endif - VMSTATE_UINT32_V(smbase, CPUState, 4), + VMSTATE_UINT32_V(smbase, CPUX86State, 4), =20 - VMSTATE_UINT64_V(pat, CPUState, 5), - VMSTATE_UINT32_V(hflags2, CPUState, 5), + VMSTATE_UINT64_V(pat, CPUX86State, 5), + VMSTATE_UINT32_V(hflags2, CPUX86State, 5), =20 - VMSTATE_UINT32_TEST(halted, CPUState, version_is_5), - VMSTATE_UINT64_V(vm_hsave, CPUState, 5), - VMSTATE_UINT64_V(vm_vmcb, CPUState, 5), - VMSTATE_UINT64_V(tsc_offset, CPUState, 5), - VMSTATE_UINT64_V(intercept, CPUState, 5), - VMSTATE_UINT16_V(intercept_cr_read, CPUState, 5), - VMSTATE_UINT16_V(intercept_cr_write, CPUState, 5), - VMSTATE_UINT16_V(intercept_dr_read, CPUState, 5), - VMSTATE_UINT16_V(intercept_dr_write, CPUState, 5), - VMSTATE_UINT32_V(intercept_exceptions, CPUState, 5), - VMSTATE_UINT8_V(v_tpr, CPUState, 5), + VMSTATE_UINT32_TEST(halted, CPUX86State, version_is_5), + VMSTATE_UINT64_V(vm_hsave, CPUX86State, 5), + VMSTATE_UINT64_V(vm_vmcb, CPUX86State, 5), + VMSTATE_UINT64_V(tsc_offset, CPUX86State, 5), + VMSTATE_UINT64_V(intercept, CPUX86State, 5), + VMSTATE_UINT16_V(intercept_cr_read, CPUX86State, 5), + VMSTATE_UINT16_V(intercept_cr_write, CPUX86State, 5), + VMSTATE_UINT16_V(intercept_dr_read, CPUX86State, 5), + VMSTATE_UINT16_V(intercept_dr_write, CPUX86State, 5), + VMSTATE_UINT32_V(intercept_exceptions, CPUX86State, 5), + VMSTATE_UINT8_V(v_tpr, CPUX86State, 5), /* MTRRs */ - VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUState, 11, 8), - VMSTATE_UINT64_V(mtrr_deftype, CPUState, 8), - VMSTATE_MTRR_VARS(mtrr_var, CPUState, 8, 8), + VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUX86State, 11, 8), + VMSTATE_UINT64_V(mtrr_deftype, CPUX86State, 8), + VMSTATE_MTRR_VARS(mtrr_var, CPUX86State, 8, 8), /* KVM-related states */ - VMSTATE_INT32_V(interrupt_injected, CPUState, 9), - VMSTATE_UINT32_V(mp_state, CPUState, 9), - VMSTATE_UINT64_V(tsc, CPUState, 9), - VMSTATE_INT32_V(exception_injected, CPUState, 11), - VMSTATE_UINT8_V(soft_interrupt, CPUState, 11), - VMSTATE_UINT8_V(nmi_injected, CPUState, 11), - VMSTATE_UINT8_V(nmi_pending, CPUState, 11), - VMSTATE_UINT8_V(has_error_code, CPUState, 11), - VMSTATE_UINT32_V(sipi_vector, CPUState, 11), + VMSTATE_INT32_V(interrupt_injected, CPUX86State, 9), + VMSTATE_UINT32_V(mp_state, CPUX86State, 9), + VMSTATE_UINT64_V(tsc, CPUX86State, 9), + VMSTATE_INT32_V(exception_injected, CPUX86State, 11), + VMSTATE_UINT8_V(soft_interrupt, CPUX86State, 11), + VMSTATE_UINT8_V(nmi_injected, CPUX86State, 11), + VMSTATE_UINT8_V(nmi_pending, CPUX86State, 11), + VMSTATE_UINT8_V(has_error_code, CPUX86State, 11), + VMSTATE_UINT32_V(sipi_vector, CPUX86State, 11), /* MCE */ - VMSTATE_UINT64_V(mcg_cap, CPUState, 10), - VMSTATE_UINT64_V(mcg_status, CPUState, 10), - VMSTATE_UINT64_V(mcg_ctl, CPUState, 10), - VMSTATE_UINT64_ARRAY_V(mce_banks, CPUState, MCE_BANKS_DEF *4, 10= ), + VMSTATE_UINT64_V(mcg_cap, CPUX86State, 10), + VMSTATE_UINT64_V(mcg_status, CPUX86State, 10), + VMSTATE_UINT64_V(mcg_ctl, CPUX86State, 10), + VMSTATE_UINT64_ARRAY_V(mce_banks, CPUX86State, MCE_BANKS_DEF *4,= 10), /* rdtscp */ - VMSTATE_UINT64_V(tsc_aux, CPUState, 11), + VMSTATE_UINT64_V(tsc_aux, CPUX86State, 11), /* KVM pvclock msr */ - VMSTATE_UINT64_V(system_time_msr, CPUState, 11), - VMSTATE_UINT64_V(wall_clock_msr, CPUState, 11), + VMSTATE_UINT64_V(system_time_msr, CPUX86State, 11), + VMSTATE_UINT64_V(wall_clock_msr, CPUX86State, 11), /* XSAVE related fields */ - VMSTATE_UINT64_V(xcr0, CPUState, 12), - VMSTATE_UINT64_V(xstate_bv, CPUState, 12), - VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUState, CPU_NB_REGS, 12), + VMSTATE_UINT64_V(xcr0, CPUX86State, 12), + VMSTATE_UINT64_V(xstate_bv, CPUX86State, 12), + VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUX86State, CPU_NB_REGS, 12), VMSTATE_END_OF_LIST() /* The above list is not sorted /wrt version numbers, watch out!= */ }, diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index 63a08d6..c04ae44 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -125,7 +125,7 @@ static inline void load_eflags(int eflags, int update= _mask) =20 /* load efer and update the corresponding hflags. XXX: do consistency checks with cpuid bits ? */ -static inline void cpu_load_efer(CPUState *env, uint64_t val) +static inline void cpu_load_efer(CPUX86State *env, uint64_t val) { env->efer =3D val; env->hflags &=3D ~(HF_LMA_MASK | HF_SVME_MASK); @@ -1376,9 +1376,9 @@ static void do_interrupt_all(int intno, int is_int,= int error_code, #endif } =20 -void do_interrupt(CPUState *env1) +void do_interrupt(CPUX86State *env1) { - CPUState *saved_env; + CPUX86State *saved_env; =20 saved_env =3D env; env =3D env1; @@ -1406,9 +1406,9 @@ void do_interrupt(CPUState *env1) env =3D saved_env; } =20 -void do_interrupt_x86_hardirq(CPUState *env1, int intno, int is_hw) +void do_interrupt_x86_hardirq(CPUX86State *env1, int intno, int is_hw) { - CPUState *saved_env; + CPUX86State *saved_env; =20 saved_env =3D env; env =3D env1; @@ -1492,7 +1492,7 @@ static void QEMU_NORETURN raise_exception_err(int e= xception_index, raise_interrupt(exception_index, 0, error_code, 0); } =20 -void raise_exception_err_env(CPUState *nenv, int exception_index, +void raise_exception_err_env(CPUX86State *nenv, int exception_index, int error_code) { env =3D nenv; @@ -1504,7 +1504,7 @@ static void QEMU_NORETURN raise_exception(int excep= tion_index) raise_interrupt(exception_index, 0, 0, 0); } =20 -void raise_exception_env(int exception_index, CPUState *nenv) +void raise_exception_env(int exception_index, CPUX86State *nenv) { env =3D nenv; raise_exception(exception_index); @@ -1513,7 +1513,7 @@ void raise_exception_env(int exception_index, CPUSt= ate *nenv) =20 #if defined(CONFIG_USER_ONLY) =20 -void do_smm_enter(CPUState *env1) +void do_smm_enter(CPUX86State *env1) { } =20 @@ -1529,12 +1529,12 @@ void helper_rsm(void) #define SMM_REVISION_ID 0x00020000 #endif =20 -void do_smm_enter(CPUState *env1) +void do_smm_enter(CPUX86State *env1) { target_ulong sm_state; SegmentCache *dt; int i, offset; - CPUState *saved_env; + CPUX86State *saved_env; =20 saved_env =3D env; env =3D env1; @@ -5002,7 +5002,7 @@ void helper_boundl(target_ulong a0, int v) NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_i= dx, +void tlb_fill(CPUX86State *env1, target_ulong addr, int is_write, int mm= u_idx, void *retaddr) { TranslationBlock *tb; @@ -5066,7 +5066,7 @@ void helper_svm_check_intercept_param(uint32_t type= , uint64_t param) { } =20 -void svm_check_intercept(CPUState *env1, uint32_t type) +void svm_check_intercept(CPUX86State *env1, uint32_t type) { } =20 @@ -5101,7 +5101,7 @@ static inline void svm_load_seg(target_phys_addr_t = addr, SegmentCache *sc) } =20 static inline void svm_load_seg_cache(target_phys_addr_t addr,=20 - CPUState *env, int seg_reg) + CPUX86State *env, int seg_reg) { SegmentCache sc1, *sc =3D &sc1; svm_load_seg(addr, sc); @@ -5460,9 +5460,9 @@ void helper_svm_check_intercept_param(uint32_t type= , uint64_t param) } } =20 -void svm_check_intercept(CPUState *env1, uint32_t type) +void svm_check_intercept(CPUX86State *env1, uint32_t type) { - CPUState *saved_env; + CPUX86State *saved_env; =20 saved_env =3D env; env =3D env1; @@ -5840,9 +5840,9 @@ uint32_t helper_cc_compute_all(int op) } } =20 -uint32_t cpu_cc_compute_all(CPUState *env1, int op) +uint32_t cpu_cc_compute_all(CPUX86State *env1, int op) { - CPUState *saved_env; + CPUX86State *saved_env; uint32_t ret; =20 saved_env =3D env; diff --git a/target-i386/translate.c b/target-i386/translate.c index 860b4a3..c1ede1a 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -388,7 +388,7 @@ static inline void gen_op_addl_T0_T1(void) =20 static inline void gen_op_jmp_T0(void) { - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip)); + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip)); } =20 static inline void gen_op_add_reg_im(int size, int reg, int32_t val) @@ -453,12 +453,12 @@ static inline void gen_op_addl_A0_reg_sN(int shift,= int reg) =20 static inline void gen_op_movl_A0_seg(int reg) { - tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base)= + REG_L_OFFSET); + tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].ba= se) + REG_L_OFFSET); } =20 static inline void gen_op_addl_A0_seg(int reg) { - tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base))= ; + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].bas= e)); tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); #ifdef TARGET_X86_64 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); @@ -468,12 +468,12 @@ static inline void gen_op_addl_A0_seg(int reg) #ifdef TARGET_X86_64 static inline void gen_op_movq_A0_seg(int reg) { - tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base)); + tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base)= ); } =20 static inline void gen_op_addq_A0_seg(int reg) { - tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base))= ; + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].bas= e)); tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); } =20 @@ -583,7 +583,7 @@ static inline void gen_op_st_T1_A0(int idx) static inline void gen_jmp_im(target_ulong pc) { tcg_gen_movi_tl(cpu_tmp0, pc); - tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip)); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip)); } =20 static inline void gen_string_movl_A0_ESI(DisasContext *s) @@ -644,7 +644,7 @@ static inline void gen_string_movl_A0_EDI(DisasContex= t *s) =20 static inline void gen_op_movl_T0_Dshift(int ot)=20 { - tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df)); + tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df)); tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); }; =20 @@ -6466,11 +6466,11 @@ static target_ulong disas_insn(DisasContext *s, t= arget_ulong pc_start) break; case 0xfc: /* cld */ tcg_gen_movi_i32(cpu_tmp2_i32, 1); - tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); + tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df))= ; break; case 0xfd: /* std */ tcg_gen_movi_i32(cpu_tmp2_i32, -1); - tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); + tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df))= ; break; =20 /************************/ @@ -7645,64 +7645,64 @@ void optimize_flags_init(void) { cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); cpu_cc_op =3D tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, cc_op), "cc_op= "); - cpu_cc_src =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_s= rc), + offsetof(CPUX86State, cc_op), "cc= _op"); + cpu_cc_src =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, c= c_src), "cc_src"); - cpu_cc_dst =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_d= st), + cpu_cc_dst =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, c= c_dst), "cc_dst"); - cpu_cc_tmp =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_t= mp), + cpu_cc_tmp =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, c= c_tmp), "cc_tmp"); =20 #ifdef TARGET_X86_64 cpu_regs[R_EAX] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[R_E= AX]), "rax"); + offsetof(CPUX86State, regs[= R_EAX]), "rax"); cpu_regs[R_ECX] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[R_E= CX]), "rcx"); + offsetof(CPUX86State, regs[= R_ECX]), "rcx"); cpu_regs[R_EDX] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[R_E= DX]), "rdx"); + offsetof(CPUX86State, regs[= R_EDX]), "rdx"); cpu_regs[R_EBX] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[R_E= BX]), "rbx"); + offsetof(CPUX86State, regs[= R_EBX]), "rbx"); cpu_regs[R_ESP] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[R_E= SP]), "rsp"); + offsetof(CPUX86State, regs[= R_ESP]), "rsp"); cpu_regs[R_EBP] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[R_E= BP]), "rbp"); + offsetof(CPUX86State, regs[= R_EBP]), "rbp"); cpu_regs[R_ESI] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[R_E= SI]), "rsi"); + offsetof(CPUX86State, regs[= R_ESI]), "rsi"); cpu_regs[R_EDI] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[R_E= DI]), "rdi"); + offsetof(CPUX86State, regs[= R_EDI]), "rdi"); cpu_regs[8] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[8]), "r= 8"); + offsetof(CPUX86State, regs[8]),= "r8"); cpu_regs[9] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[9]), "= r9"); + offsetof(CPUX86State, regs[9])= , "r9"); cpu_regs[10] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[10]), = "r10"); + offsetof(CPUX86State, regs[10]= ), "r10"); cpu_regs[11] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[11]), = "r11"); + offsetof(CPUX86State, regs[11]= ), "r11"); cpu_regs[12] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[12]), = "r12"); + offsetof(CPUX86State, regs[12]= ), "r12"); cpu_regs[13] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[13]), = "r13"); + offsetof(CPUX86State, regs[13]= ), "r13"); cpu_regs[14] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[14]), = "r14"); + offsetof(CPUX86State, regs[14]= ), "r14"); cpu_regs[15] =3D tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, regs[15]), = "r15"); + offsetof(CPUX86State, regs[15]= ), "r15"); #else cpu_regs[R_EAX] =3D tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[R_E= AX]), "eax"); + offsetof(CPUX86State, regs[= R_EAX]), "eax"); cpu_regs[R_ECX] =3D tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[R_E= CX]), "ecx"); + offsetof(CPUX86State, regs[= R_ECX]), "ecx"); cpu_regs[R_EDX] =3D tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[R_E= DX]), "edx"); + offsetof(CPUX86State, regs[= R_EDX]), "edx"); cpu_regs[R_EBX] =3D tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[R_E= BX]), "ebx"); + offsetof(CPUX86State, regs[= R_EBX]), "ebx"); cpu_regs[R_ESP] =3D tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[R_E= SP]), "esp"); + offsetof(CPUX86State, regs[= R_ESP]), "esp"); cpu_regs[R_EBP] =3D tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[R_E= BP]), "ebp"); + offsetof(CPUX86State, regs[= R_EBP]), "ebp"); cpu_regs[R_ESI] =3D tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[R_E= SI]), "esi"); + offsetof(CPUX86State, regs[= R_ESI]), "esi"); cpu_regs[R_EDI] =3D tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[R_E= DI]), "edi"); + offsetof(CPUX86State, regs[= R_EDI]), "edi"); #endif =20 /* register helpers */ @@ -7713,7 +7713,7 @@ void optimize_flags_init(void) /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline void gen_intermediate_code_internal(CPUState *env, +static inline void gen_intermediate_code_internal(CPUX86State *env, TranslationBlock *tb, int search_pc) { @@ -7890,17 +7890,17 @@ static inline void gen_intermediate_code_internal= (CPUState *env, } } =20 -void gen_intermediate_code(CPUState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 0); } =20 -void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) +void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 1); } =20 -void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_po= s) +void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc= _pos) { int cc_op; #ifdef DEBUG_DISAS --=20 1.7.7