From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55579) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C4A-00006f-Mm for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:30:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6C3x-0001Ub-0i for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:54 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39852 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C3w-0001U8-KM for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:40 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 83DFB8FE2D for ; Sat, 10 Mar 2012 03:29:39 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 10 Mar 2012 03:28:05 +0100 Message-Id: <1331346496-10736-34-git-send-email-afaerber@suse.de> In-Reply-To: <1331346496-10736-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v4 33/44] i386 hw/: Don't use CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Scripted conversion: for file in hw/apic.h hw/kvm/apic.c hw/kvmvapic.c hw/pc.c hw/vmport.c h= w/xen_machine_pv.c; do sed -i "s/CPUState/CPUX86State/g" $file done Signed-off-by: Andreas F=C3=A4rber --- hw/apic.h | 2 +- hw/kvm/apic.c | 2 +- hw/kvmvapic.c | 22 +++++++++++----------- hw/pc.c | 20 ++++++++++---------- hw/vmport.c | 12 ++++++------ hw/xen_machine_pv.c | 2 +- 6 files changed, 30 insertions(+), 30 deletions(-) diff --git a/hw/apic.h b/hw/apic.h index d6d6d44..62179ce 100644 --- a/hw/apic.h +++ b/hw/apic.h @@ -22,7 +22,7 @@ void apic_handle_tpr_access_report(DeviceState *d, targ= et_ulong ip, TPRAccess access); =20 /* pc.c */ -int cpu_is_bsp(CPUState *env); +int cpu_is_bsp(CPUX86State *env); DeviceState *cpu_get_current_apic(void); =20 #endif diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c index 9ca68f8..ffe7a52 100644 --- a/hw/kvm/apic.c +++ b/hw/kvm/apic.c @@ -124,7 +124,7 @@ static void kvm_apic_vapic_base_update(APICCommonStat= e *s) static void do_inject_external_nmi(void *data) { APICCommonState *s =3D data; - CPUState *env =3D s->cpu_env; + CPUX86State *env =3D s->cpu_env; uint32_t lvt; int ret; =20 diff --git a/hw/kvmvapic.c b/hw/kvmvapic.c index 36ccfbc..c8c1c86 100644 --- a/hw/kvmvapic.c +++ b/hw/kvmvapic.c @@ -142,7 +142,7 @@ static void update_guest_rom_state(VAPICROMState *s) write_guest_rom_state(s); } =20 -static int find_real_tpr_addr(VAPICROMState *s, CPUState *env) +static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) { target_phys_addr_t paddr; target_ulong addr; @@ -185,7 +185,7 @@ static bool opcode_matches(uint8_t *opcode, const TPR= Instruction *instr) modrm_reg(opcode[1]) =3D=3D instr->modrm_reg); } =20 -static int evaluate_tpr_instruction(VAPICROMState *s, CPUState *env, +static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env, target_ulong *pip, TPRAccess access) { const TPRInstruction *instr; @@ -267,7 +267,7 @@ instruction_ok: return 0; } =20 -static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ul= ong ip) +static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target= _ulong ip) { target_phys_addr_t paddr; uint32_t rom_state_vaddr; @@ -330,7 +330,7 @@ static int update_rom_mapping(VAPICROMState *s, CPUSt= ate *env, target_ulong ip) * cannot be accessed or is considered invalid. This also ensures that w= e are * not patching the wrong guest. */ -static int get_kpcr_number(CPUState *env) +static int get_kpcr_number(CPUX86State *env) { struct kpcr { uint8_t fill1[0x1c]; @@ -347,7 +347,7 @@ static int get_kpcr_number(CPUState *env) return kpcr.number; } =20 -static int vapic_enable(VAPICROMState *s, CPUState *env) +static int vapic_enable(VAPICROMState *s, CPUX86State *env) { int cpu_number =3D get_kpcr_number(env); target_phys_addr_t vapic_paddr; @@ -367,12 +367,12 @@ static int vapic_enable(VAPICROMState *s, CPUState = *env) return 0; } =20 -static void patch_byte(CPUState *env, target_ulong addr, uint8_t byte) +static void patch_byte(CPUX86State *env, target_ulong addr, uint8_t byte= ) { cpu_memory_rw_debug(env, addr, &byte, 1, 1); } =20 -static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip, +static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong = ip, uint32_t target) { uint32_t offset; @@ -382,7 +382,7 @@ static void patch_call(VAPICROMState *s, CPUState *en= v, target_ulong ip, cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1)= ; } =20 -static void patch_instruction(VAPICROMState *s, CPUState *env, target_ul= ong ip) +static void patch_instruction(VAPICROMState *s, CPUX86State *env, target= _ulong ip) { target_phys_addr_t paddr; VAPICHandlers *handlers; @@ -439,7 +439,7 @@ void vapic_report_tpr_access(DeviceState *dev, void *= cpu, target_ulong ip, TPRAccess access) { VAPICROMState *s =3D DO_UPCAST(VAPICROMState, busdev.qdev, dev); - CPUState *env =3D cpu; + CPUX86State *env =3D cpu; =20 cpu_synchronize_state(env); =20 @@ -475,7 +475,7 @@ static void vapic_enable_tpr_reporting(bool enable) VAPICEnableTPRReporting info =3D { .enable =3D enable, }; - CPUState *env; + CPUX86State *env; =20 for (env =3D first_cpu; env !=3D NULL; env =3D env->next_cpu) { info.apic =3D env->apic_state; @@ -604,7 +604,7 @@ static int vapic_prepare(VAPICROMState *s) static void vapic_write(void *opaque, target_phys_addr_t addr, uint64_t = data, unsigned int size) { - CPUState *env =3D cpu_single_env; + CPUX86State *env =3D cpu_single_env; target_phys_addr_t rom_paddr; VAPICROMState *s =3D opaque; =20 diff --git a/hw/pc.c b/hw/pc.c index aca4460..83a1b5b 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -140,7 +140,7 @@ void cpu_smm_register(cpu_set_smm_t callback, void *a= rg) smm_arg =3D arg; } =20 -void cpu_smm_update(CPUState *env) +void cpu_smm_update(CPUX86State *env) { if (smm_set && smm_arg && env =3D=3D first_cpu) smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); @@ -148,7 +148,7 @@ void cpu_smm_update(CPUState *env) =20 =20 /* IRQ handling */ -int cpu_get_pic_interrupt(CPUState *env) +int cpu_get_pic_interrupt(CPUX86State *env) { int intno; =20 @@ -167,7 +167,7 @@ int cpu_get_pic_interrupt(CPUState *env) =20 static void pic_irq_request(void *opaque, int irq, int level) { - CPUState *env =3D first_cpu; + CPUX86State *env =3D first_cpu; =20 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); if (env->apic_state) { @@ -522,7 +522,7 @@ type_init(port92_register_types) =20 static void handle_a20_line_change(void *opaque, int irq, int level) { - CPUState *cpu =3D opaque; + CPUX86State *cpu =3D opaque; =20 /* XXX: send to all CPUs ? */ /* XXX: add logic to handle multiple A20 line sources */ @@ -869,7 +869,7 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) nb_ne2k++; } =20 -int cpu_is_bsp(CPUState *env) +int cpu_is_bsp(CPUX86State *env) { /* We hard-wire the BSP to the first CPU. */ return env->cpu_index =3D=3D 0; @@ -917,7 +917,7 @@ static DeviceState *apic_init(void *env, uint8_t apic= _id) =20 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) { - CPUState *s =3D opaque; + CPUX86State *s =3D opaque; =20 if (level) { cpu_interrupt(s, CPU_INTERRUPT_SMI); @@ -926,15 +926,15 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, i= nt level) =20 static void pc_cpu_reset(void *opaque) { - CPUState *env =3D opaque; + CPUX86State *env =3D opaque; =20 cpu_state_reset(env); env->halted =3D !cpu_is_bsp(env); } =20 -static CPUState *pc_new_cpu(const char *cpu_model) +static CPUX86State *pc_new_cpu(const char *cpu_model) { - CPUState *env; + CPUX86State *env; =20 env =3D cpu_init(cpu_model); if (!env) { @@ -1070,7 +1070,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *p= ci_bus) =20 static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env =3D cpu_single_env; + CPUX86State *env =3D cpu_single_env; =20 if (env && level) { cpu_exit(env); diff --git a/hw/vmport.c b/hw/vmport.c index 9373be9..a4f52ee 100644 --- a/hw/vmport.c +++ b/hw/vmport.c @@ -57,7 +57,7 @@ void vmport_register(unsigned char command, IOPortReadF= unc *func, void *opaque) static uint32_t vmport_ioport_read(void *opaque, uint32_t addr) { VMPortState *s =3D opaque; - CPUState *env =3D cpu_single_env; + CPUX86State *env =3D cpu_single_env; unsigned char command; uint32_t eax; =20 @@ -83,21 +83,21 @@ static uint32_t vmport_ioport_read(void *opaque, uint= 32_t addr) =20 static void vmport_ioport_write(void *opaque, uint32_t addr, uint32_t va= l) { - CPUState *env =3D cpu_single_env; + CPUX86State *env =3D cpu_single_env; =20 env->regs[R_EAX] =3D vmport_ioport_read(opaque, addr); } =20 static uint32_t vmport_cmd_get_version(void *opaque, uint32_t addr) { - CPUState *env =3D cpu_single_env; + CPUX86State *env =3D cpu_single_env; env->regs[R_EBX] =3D VMPORT_MAGIC; return 6; } =20 static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr) { - CPUState *env =3D cpu_single_env; + CPUX86State *env =3D cpu_single_env; env->regs[R_EBX] =3D 0x1177; return ram_size; } @@ -105,7 +105,7 @@ static uint32_t vmport_cmd_ram_size(void *opaque, uin= t32_t addr) /* vmmouse helpers */ void vmmouse_get_data(uint32_t *data) { - CPUState *env =3D cpu_single_env; + CPUX86State *env =3D cpu_single_env; =20 data[0] =3D env->regs[R_EAX]; data[1] =3D env->regs[R_EBX]; data[2] =3D env->regs[R_ECX]; data[3] =3D env->regs[R_EDX]; @@ -114,7 +114,7 @@ void vmmouse_get_data(uint32_t *data) =20 void vmmouse_set_data(const uint32_t *data) { - CPUState *env =3D cpu_single_env; + CPUX86State *env =3D cpu_single_env; =20 env->regs[R_EAX] =3D data[0]; env->regs[R_EBX] =3D data[1]; env->regs[R_ECX] =3D data[2]; env->regs[R_EDX] =3D data[3]; diff --git a/hw/xen_machine_pv.c b/hw/xen_machine_pv.c index 7985d11..7eee770 100644 --- a/hw/xen_machine_pv.c +++ b/hw/xen_machine_pv.c @@ -36,7 +36,7 @@ static void xen_init_pv(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUX86State *env; DriveInfo *dinfo; int i; =20 --=20 1.7.7