From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C4B-00009k-Me for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:30:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6C3y-0001V2-5k for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:55 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39855 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C3x-0001Uf-Sx for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:42 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id C641D8FC92 for ; Sat, 10 Mar 2012 03:29:40 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 10 Mar 2012 03:28:08 +0100 Message-Id: <1331346496-10736-37-git-send-email-afaerber@suse.de> In-Reply-To: <1331346496-10736-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v4 36/44] microblaze hw/: Don't use CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Scripted conversion: for file in hw/microblaze_*.[hc] hw/petalogix_ml605_mmu.c hw/petalogix_= s3adsp1800_mmu.c; do sed -i "s/CPUState/CPUMBState/g" $file done Signed-off-by: Andreas F=C3=A4rber --- hw/microblaze_boot.c | 8 ++++---- hw/microblaze_boot.h | 4 ++-- hw/microblaze_pic_cpu.c | 4 ++-- hw/microblaze_pic_cpu.h | 2 +- hw/petalogix_ml605_mmu.c | 4 ++-- hw/petalogix_s3adsp1800_mmu.c | 4 ++-- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c index 7ce04dc..b4fbb10 100644 --- a/hw/microblaze_boot.c +++ b/hw/microblaze_boot.c @@ -35,7 +35,7 @@ =20 static struct { - void (*machine_cpu_reset)(CPUState *); + void (*machine_cpu_reset)(CPUMBState *); uint32_t bootstrap_pc; uint32_t cmdline; uint32_t fdt; @@ -43,7 +43,7 @@ static struct =20 static void main_cpu_reset(void *opaque) { - CPUState *env =3D opaque; + CPUMBState *env =3D opaque; =20 cpu_state_reset(env); env->regs[5] =3D boot_info.cmdline; @@ -99,9 +99,9 @@ static uint64_t translate_kernel_address(void *opaque, = uint64_t addr) return addr - 0x30000000LL; } =20 -void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base= , uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUState *)) + void (*machine_cpu_reset)(CPUMBState *= )) { =20 QemuOpts *machine_opts; diff --git a/hw/microblaze_boot.h b/hw/microblaze_boot.h index 69d4ac6..bf9d136 100644 --- a/hw/microblaze_boot.h +++ b/hw/microblaze_boot.h @@ -3,8 +3,8 @@ =20 #include "hw.h" =20 -void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base= , uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUState *))= ; + void (*machine_cpu_reset)(CPUMBState *= )); =20 #endif /* __MICROBLAZE_BOOT __ */ diff --git a/hw/microblaze_pic_cpu.c b/hw/microblaze_pic_cpu.c index 8b5623c..ff36a52 100644 --- a/hw/microblaze_pic_cpu.c +++ b/hw/microblaze_pic_cpu.c @@ -29,7 +29,7 @@ =20 static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) { - CPUState *env =3D (CPUState *)opaque; + CPUMBState *env =3D (CPUMBState *)opaque; int type =3D irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; =20 if (level) @@ -38,7 +38,7 @@ static void microblaze_pic_cpu_handler(void *opaque, in= t irq, int level) cpu_reset_interrupt(env, type); } =20 -qemu_irq *microblaze_pic_init_cpu(CPUState *env) +qemu_irq *microblaze_pic_init_cpu(CPUMBState *env) { return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2); } diff --git a/hw/microblaze_pic_cpu.h b/hw/microblaze_pic_cpu.h index 4c76275..43090a4 100644 --- a/hw/microblaze_pic_cpu.h +++ b/hw/microblaze_pic_cpu.h @@ -3,6 +3,6 @@ =20 #include "qemu-common.h" =20 -qemu_irq *microblaze_pic_init_cpu(CPUState *env); +qemu_irq *microblaze_pic_init_cpu(CPUMBState *env); =20 #endif /* MICROBLAZE_PIC_CPU_H */ diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index c87fa11..31a4348 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -54,7 +54,7 @@ #define AXIENET_BASEADDR 0x82780000 #define AXIDMA_BASEADDR 0x84600000 =20 -static void machine_cpu_reset(CPUState *env) +static void machine_cpu_reset(CPUMBState *env) { env->pvr.regs[10] =3D 0x0e000000; /* virtex 6 */ /* setup pvr to match kernel setting */ @@ -75,7 +75,7 @@ petalogix_ml605_init(ram_addr_t ram_size, { MemoryRegion *address_space_mem =3D get_system_memory(); DeviceState *dev; - CPUState *env; + CPUMBState *env; DriveInfo *dinfo; int i; target_phys_addr_t ddr_base =3D MEMORY_BASEADDR; diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.= c index 2cb0b1f..ff154c7 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -49,7 +49,7 @@ #define UARTLITE_BASEADDR 0x84000000 #define ETHLITE_BASEADDR 0x81000000 =20 -static void machine_cpu_reset(CPUState *env) +static void machine_cpu_reset(CPUMBState *env) { /* FIXME: move to machine specfic cpu reset */ env->pvr.regs[10] =3D 0x0c000000; /* spartan 3a dsp family. */ @@ -63,7 +63,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_m= odel) { DeviceState *dev; - CPUState *env; + CPUMBState *env; DriveInfo *dinfo; int i; target_phys_addr_t ddr_base =3D MEMORY_BASEADDR; --=20 1.7.7