From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55731) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C4I-0000UM-Uc for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:30:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6C40-0001Vr-PL for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:30:02 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39860 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C40-0001VJ-Fv for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:44 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 610298FFEB for ; Sat, 10 Mar 2012 03:29:43 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 10 Mar 2012 03:28:13 +0100 Message-Id: <1331346496-10736-42-git-send-email-afaerber@suse.de> In-Reply-To: <1331346496-10736-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v4 41/44] sparc hw/: Don't use CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Scripted conversion: for file in hw/sun4m.c hw/sun4u.c hw/grlib.h hw/leon3.c; do sed -i "s/CPUState/CPUSPARCState/g" $file done Signed-off-by: Andreas F=C3=A4rber --- hw/grlib.h | 2 +- hw/leon3.c | 8 ++++---- hw/sun4m.c | 12 ++++++------ hw/sun4u.c | 24 ++++++++++++------------ 4 files changed, 23 insertions(+), 23 deletions(-) diff --git a/hw/grlib.h b/hw/grlib.h index fdf4b11..e1c4137 100644 --- a/hw/grlib.h +++ b/hw/grlib.h @@ -42,7 +42,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno); =20 static inline DeviceState *grlib_irqmp_create(target_phys_addr_t base, - CPUState *env, + CPUSPARCState *env, qemu_irq **cpu_irqs, uint32_t nr_irqs, set_pil_in_fn set_pil_in) diff --git a/hw/leon3.c b/hw/leon3.c index 1dc5a02..0a5ff16 100644 --- a/hw/leon3.c +++ b/hw/leon3.c @@ -42,14 +42,14 @@ #define MAX_PILS 16 =20 typedef struct ResetData { - CPUState *env; + CPUSPARCState *env; uint32_t entry; /* save kernel entry in case of reset */ } ResetData; =20 static void main_cpu_reset(void *opaque) { ResetData *s =3D (ResetData *)opaque; - CPUState *env =3D s->env; + CPUSPARCState *env =3D s->env; =20 cpu_state_reset(env); =20 @@ -65,7 +65,7 @@ void leon3_irq_ack(void *irq_manager, int intno) =20 static void leon3_set_pil_in(void *opaque, uint32_t pil_in) { - CPUState *env =3D (CPUState *)opaque; + CPUSPARCState *env =3D (CPUSPARCState *)opaque; =20 assert(env !=3D NULL); =20 @@ -101,7 +101,7 @@ static void leon3_generic_hw_init(ram_addr_t ram_siz= e, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUSPARCState *env; MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *ram =3D g_new(MemoryRegion, 1); MemoryRegion *prom =3D g_new(MemoryRegion, 1); diff --git a/hw/sun4m.c b/hw/sun4m.c index 4045740..7bcbf37 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -228,7 +228,7 @@ void sun4m_irq_info(Monitor *mon) slavio_irq_info(mon, slavio_intctl); } =20 -void cpu_check_irqs(CPUState *env) +void cpu_check_irqs(CPUSPARCState *env) { if (env->pil_in && (env->interrupt_index =3D=3D 0 || (env->interrupt_index & ~15) =3D=3D TT_EXTINT)) = { @@ -253,7 +253,7 @@ void cpu_check_irqs(CPUState *env) } } =20 -static void cpu_kick_irq(CPUState *env) +static void cpu_kick_irq(CPUSPARCState *env) { env->halted =3D 0; cpu_check_irqs(env); @@ -262,7 +262,7 @@ static void cpu_kick_irq(CPUState *env) =20 static void cpu_set_irq(void *opaque, int irq, int level) { - CPUState *env =3D opaque; + CPUSPARCState *env =3D opaque; =20 if (level) { trace_sun4m_cpu_set_irq_raise(irq); @@ -281,7 +281,7 @@ static void dummy_cpu_set_irq(void *opaque, int irq, = int level) =20 static void main_cpu_reset(void *opaque) { - CPUState *env =3D opaque; + CPUSPARCState *env =3D opaque; =20 cpu_state_reset(env); env->halted =3D 0; @@ -289,7 +289,7 @@ static void main_cpu_reset(void *opaque) =20 static void secondary_cpu_reset(void *opaque) { - CPUState *env =3D opaque; + CPUSPARCState *env =3D opaque; =20 cpu_state_reset(env); env->halted =3D 1; @@ -809,7 +809,7 @@ static TypeInfo ram_info =3D { static void cpu_devinit(const char *cpu_model, unsigned int id, uint64_t prom_addr, qemu_irq **cpu_irqs) { - CPUState *env; + CPUSPARCState *env; =20 env =3D cpu_init(cpu_model); if (!env) { diff --git a/hw/sun4u.c b/hw/sun4u.c index 8b043f2..c32eddb 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -243,7 +243,7 @@ static unsigned long sun4u_load_kernel(const char *ke= rnel_filename, return kernel_size; } =20 -void cpu_check_irqs(CPUState *env) +void cpu_check_irqs(CPUSPARCState *env) { uint32_t pil =3D env->pil_in | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); @@ -297,7 +297,7 @@ void cpu_check_irqs(CPUState *env) } } =20 -static void cpu_kick_irq(CPUState *env) +static void cpu_kick_irq(CPUSPARCState *env) { env->halted =3D 0; cpu_check_irqs(env); @@ -306,7 +306,7 @@ static void cpu_kick_irq(CPUState *env) =20 static void cpu_set_irq(void *opaque, int irq, int level) { - CPUState *env =3D opaque; + CPUSPARCState *env =3D opaque; =20 if (level) { CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq); @@ -320,7 +320,7 @@ static void cpu_set_irq(void *opaque, int irq, int le= vel) } =20 typedef struct ResetData { - CPUState *env; + CPUSPARCState *env; uint64_t prom_addr; } ResetData; =20 @@ -344,7 +344,7 @@ void cpu_get_timer(QEMUFile *f, CPUTimer *s) qemu_get_timer(f, s->qtimer); } =20 -static CPUTimer* cpu_timer_create(const char* name, CPUState *env, +static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env, QEMUBHFunc *cb, uint32_t frequency, uint64_t disabled_mask) { @@ -373,7 +373,7 @@ static void cpu_timer_reset(CPUTimer *timer) static void main_cpu_reset(void *opaque) { ResetData *s =3D (ResetData *)opaque; - CPUState *env =3D s->env; + CPUSPARCState *env =3D s->env; static unsigned int nr_resets; =20 cpu_state_reset(env); @@ -396,7 +396,7 @@ static void main_cpu_reset(void *opaque) =20 static void tick_irq(void *opaque) { - CPUState *env =3D opaque; + CPUSPARCState *env =3D opaque; =20 CPUTimer* timer =3D env->tick; =20 @@ -413,7 +413,7 @@ static void tick_irq(void *opaque) =20 static void stick_irq(void *opaque) { - CPUState *env =3D opaque; + CPUSPARCState *env =3D opaque; =20 CPUTimer* timer =3D env->stick; =20 @@ -430,7 +430,7 @@ static void stick_irq(void *opaque) =20 static void hstick_irq(void *opaque) { - CPUState *env =3D opaque; + CPUSPARCState *env =3D opaque; =20 CPUTimer* timer =3D env->hstick; =20 @@ -714,9 +714,9 @@ static TypeInfo ram_info =3D { .class_init =3D ram_class_init, }; =20 -static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *= hwdef) +static CPUSPARCState *cpu_devinit(const char *cpu_model, const struct hw= def *hwdef) { - CPUState *env; + CPUSPARCState *env; ResetData *reset_info; =20 uint32_t tick_frequency =3D 100*1000000; @@ -755,7 +755,7 @@ static void sun4uv_init(MemoryRegion *address_space_m= em, const char *initrd_filename, const char *cpu_mod= el, const struct hwdef *hwdef) { - CPUState *env; + CPUSPARCState *env; M48t59State *nvram; unsigned int i; long initrd_size, kernel_size; --=20 1.7.7