From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41586) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYZ-0006UN-VH for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6PYX-0001U5-Ov for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:11 -0500 Received: from cantor2.suse.de ([195.135.220.15]:42659 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYX-0001TY-CS for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:09 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 10 Mar 2012 17:53:49 +0100 Message-Id: <1331398436-20761-14-git-send-email-afaerber@suse.de> In-Reply-To: <1331398436-20761-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331398436-20761-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v4 13/20] target-arm: Store VFP FPSID register in ARMCPUClass List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Signed-off-by: Andreas F=C3=A4rber Cc: Peter Maydell --- target-arm/cpu-qom.h | 3 +++ target-arm/cpu.c | 11 +++++++++++ target-arm/cpu.h | 1 - target-arm/helper.c | 12 ------------ 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 3832986..6cb7891 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -53,6 +53,9 @@ typedef struct ARMCPUClass { uint32_t c0_c2[8]; uint32_t c1_sys; } cp15; + struct { + uint32_t fpsid; + } vfp; =20 uint32_t features; } ARMCPUClass; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1614be4..ad4a90a 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -52,6 +52,7 @@ static void arm_cpu_reset(CPUState *c) =20 /* Genuine reset */ env->cp15.c1_sys =3D klass->cp15.c1_sys; + env->vfp.xregs[ARM_VFP_FPSID] =3D klass->vfp.fpsid; =20 #if defined(CONFIG_USER_ONLY) env->uncached_cpsr =3D ARM_CPU_MODE_USR; @@ -177,6 +178,7 @@ typedef struct ARMCPUInfo { uint32_t cp15_c0_c1[8]; uint32_t cp15_c0_c2[8]; uint32_t cp15_c1_sys; + uint32_t vfp_fpsid; uint32_t features; void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info= ); } ARMCPUInfo; @@ -263,6 +265,7 @@ static const ARMCPUInfo arm_cpus[] =3D { .id =3D 0x41069265, .cp15_c0_cachetype =3D 0x1dd20d2, .cp15_c1_sys =3D 0x00090078, + .vfp_fpsid =3D 0x41011090, .features =3D ARM_FEATURE(V5) | ARM_FEATURE(VFP), }, @@ -279,6 +282,7 @@ static const ARMCPUInfo arm_cpus[] =3D { .id =3D 0x4106a262, .cp15_c0_cachetype =3D 0x1dd20d2, .cp15_c1_sys =3D 0x00090078, + .vfp_fpsid =3D 0x410110a0, .features =3D ARM_FEATURE(V5) | ARM_FEATURE(VFP) | ARM_FEATURE(AUXCR), @@ -305,6 +309,7 @@ static const ARMCPUInfo arm_cpus[] =3D { 0x141, 0, 0, 0 }, .cp15_c1_sys =3D 0x00050078, + .vfp_fpsid =3D 0x410120b4, .features =3D ARM_FEATURE(V6) | ARM_FEATURE(VFP), }, @@ -321,6 +326,7 @@ static const ARMCPUInfo arm_cpus[] =3D { 0x01141, 0, 0, 0 }, .cp15_c1_sys =3D 0x00050078, + .vfp_fpsid =3D 0x410120b5, .features =3D ARM_FEATURE(V6K) | ARM_FEATURE(VFP) | ARM_FEATURE(VAPA), @@ -337,6 +343,7 @@ static const ARMCPUInfo arm_cpus[] =3D { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 }, + .vfp_fpsid =3D 0x410120b4, .features =3D ARM_FEATURE(V6K) | ARM_FEATURE(VFP) | ARM_FEATURE(VAPA), @@ -360,6 +367,7 @@ static const ARMCPUInfo arm_cpus[] =3D { 0x00111142, 0, 0, 0 }, .cp15_c1_sys =3D 0x00c50078, + .vfp_fpsid =3D 0x410330c0, .features =3D ARM_FEATURE(V7) | ARM_FEATURE(VFP3) | ARM_FEATURE(NEON) | @@ -378,6 +386,7 @@ static const ARMCPUInfo arm_cpus[] =3D { 0x00111142, 0, 0, 0 }, .cp15_c1_sys =3D 0x00c50078, + .vfp_fpsid =3D 0x41033090, .features =3D ARM_FEATURE(V7) | ARM_FEATURE(VFP3) | ARM_FEATURE(VFP_FP16) | @@ -402,6 +411,7 @@ static const ARMCPUInfo arm_cpus[] =3D { 0x10011142, 0, 0, 0 }, .cp15_c1_sys =3D 0x00c50078, + .vfp_fpsid =3D 0x410430f0, .features =3D ARM_FEATURE(V7) | ARM_FEATURE(VFP4) | ARM_FEATURE(VFP_FP16) | @@ -526,6 +536,7 @@ static void arm_cpu_class_init(ObjectClass *klass, vo= id *data) memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t)); k->cp15.c1_sys =3D info->cp15_c1_sys; + k->vfp.fpsid =3D info->vfp_fpsid; k->features =3D info->features; =20 if (info->class_init !=3D NULL) { diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d135221..e0d711f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -403,7 +403,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID(env) (env->cp15.c0_cpuid) =20 #define ARM_CPUID_ARM1026 0x4106a262 -#define ARM_CPUID_ARM926 0x41069265 #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 #define ARM_CPUID_ARM1136 0x4117b363 diff --git a/target-arm/helper.c b/target-arm/helper.c index 421ce98..6ea656c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -8,12 +8,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { - case ARM_CPUID_ARM926: - env->vfp.xregs[ARM_VFP_FPSID] =3D 0x41011090; - break; - case ARM_CPUID_ARM1026: - env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410110a0; - break; case ARM_CPUID_ARM1136: /* This is the 1136 r1, which is a v6K core */ /* Fall through */ @@ -26,22 +20,18 @@ static void cpu_reset_model_id(CPUARMState *env, uint= 32_t id) * for 1136_r2 (in particular r0p2 does not actually implement m= ost * of the ID registers). */ - env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x00000000; break; case ARM_CPUID_ARM1176: - env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x00000000; break; case ARM_CPUID_ARM11MPCORE: - env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x00000000; break; case ARM_CPUID_CORTEXA8: - env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410330c0; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x00011100; env->cp15.c0_clid =3D (1 << 27) | (2 << 24) | 3; @@ -50,7 +40,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32= _t id) env->cp15.c0_ccsid[2] =3D 0xf0000000; /* No L2 icache. */ break; case ARM_CPUID_CORTEXA9: - env->vfp.xregs[ARM_VFP_FPSID] =3D 0x41033090; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x01111111; env->cp15.c0_clid =3D (1 << 27) | (1 << 24) | 3; @@ -58,7 +47,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32= _t id) env->cp15.c0_ccsid[1] =3D 0x200fe015; /* 16k L1 icache. */ break; case ARM_CPUID_CORTEXA15: - env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410430f0; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x10110222; env->vfp.xregs[ARM_VFP_MVFR1] =3D 0x11111111; env->cp15.c0_clid =3D 0x0a200023; --=20 1.7.7