From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41630) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYc-0006cm-Fb for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6PYa-0001Xs-Ay for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:14 -0500 Received: from cantor2.suse.de ([195.135.220.15]:42675 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYa-0001Ue-11 for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:12 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 10 Mar 2012 17:53:54 +0100 Message-Id: <1331398436-20761-19-git-send-email-afaerber@suse.de> In-Reply-To: <1331398436-20761-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331398436-20761-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Allow to inspect and manipulate MIDR variant and revision fields. Signed-off-by: Andreas F=C3=A4rber Cc: Peter Maydell --- target-arm/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 48 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8917a20..ad33742 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -20,6 +20,7 @@ =20 #include "cpu-qom.h" #include "qemu-common.h" +#include "qapi/qapi-visit-core.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif @@ -173,6 +174,46 @@ static inline void unset_class_feature(ARMCPUClass *= klass, int feature) klass->features &=3D ~(1u << feature); } =20 +static void arm_cpuid_variant_get(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + int64_t value =3D (cpu->env.cp15.c0_cpuid >> 20) & 0xf; + + visit_type_int(v, &value, name, errp); +} + +static void arm_cpuid_variant_set(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + int64_t value; + + visit_type_int(v, &value, name, errp); + cpu->env.cp15.c0_cpuid &=3D ~(0xf << 20); + cpu->env.cp15.c0_cpuid |=3D (value << 20) & 0xf; +} + +static void arm_cpuid_revision_get(Object *obj, Visitor *v, void *opaque= , + const char *name, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + int64_t value =3D cpu->env.cp15.c0_cpuid & 0xf; + + visit_type_int(v, &value, name, errp); +} + +static void arm_cpuid_revision_set(Object *obj, Visitor *v, void *opaque= , + const char *name, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + int64_t value; + + visit_type_int(v, &value, name, errp); + cpu->env.cp15.c0_cpuid &=3D ~0xf; + cpu->env.cp15.c0_cpuid |=3D value & 0xf; +} + /* CPU models */ =20 typedef struct ARMCPUInfo { @@ -554,6 +595,13 @@ static void arm_cpu_initfn(Object *obj) cpu->env.cp15.c0_cpuid =3D cpu_class->cp15.c0_cpuid; =20 cpu_reset(CPU(cpu)); + + object_property_add(obj, "cpuid-variant", "uint4", + arm_cpuid_variant_get, + arm_cpuid_variant_set, NULL, NULL, NULL); + object_property_add(obj, "cpuid-revision", "uint4", + arm_cpuid_revision_get, + arm_cpuid_revision_set, NULL, NULL, NULL); } =20 static void arm_cpu_class_init(ObjectClass *klass, void *data) --=20 1.7.7