From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41712) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYn-0007Bc-H9 for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6PYT-0001PL-3m for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:25 -0500 Received: from cantor2.suse.de ([195.135.220.15]:42631 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYS-0001Oq-QO for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:05 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 10 Mar 2012 17:53:41 +0100 Message-Id: <1331398436-20761-6-git-send-email-afaerber@suse.de> In-Reply-To: <1331398436-20761-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331398436-20761-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v4 05/20] target-arm: Overwrite reset handler for ti925t List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook The OMAPCP feature allows to switch between TI915T and TI925T via cp15 c15_ticonfig register. Move reset into ti925t-specific callback. Signed-off-by: Andreas F=C3=A4rber Cc: Peter Maydell --- target-arm/cpu.c | 18 ++++++++++++++++++ target-arm/helper.c | 1 - 2 files changed, 18 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1e34cba..097701f 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -105,6 +105,23 @@ typedef struct ARMCPUInfo { void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info= ); } ARMCPUInfo; =20 +static void ti925t_reset(CPUState *c) +{ + ARMCPU *cpu =3D ARM_CPU(c); + CPUARMState *env =3D &cpu->env; + + arm_cpu_reset(c); + + env->cp15.c0_cpuid =3D ARM_CPUID_TI925T; /* Depends on wiring. */ +} + +static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info= ) +{ + CPUClass *cpu_class =3D CPU_CLASS(klass); + + cpu_class->reset =3D ti925t_reset; +} + static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm926", @@ -157,6 +174,7 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "ti925t", .id =3D 0x54029252, + .class_init =3D ti925t_class_init, }, { .name =3D "sa1100", diff --git a/target-arm/helper.c b/target-arm/helper.c index 39f3c40..5ebe308 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -196,7 +196,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint= 32_t id) case ARM_CPUID_TI925T: set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_OMAPCP); - env->cp15.c0_cpuid =3D ARM_CPUID_TI925T; /* Depends on wiring. = */ env->cp15.c0_cachetype =3D 0x5109149; env->cp15.c1_sys =3D 0x00000070; env->cp15.c15_i_max =3D 0x000; --=20 1.7.7